drm/i915: Program GMBUS Frequency based on the CDCLK for VLV.

CDCLK is used to generate the gmbus clock.  This is normally done by
BIOS. Program the value if the BIOS-less system doesn't do it.

v2: Move this to intel_i2c_reset to allow reprogram the gmbus frequency
during resume. (Daniel)

v3: Change GMBUS_FREQ to GMBUSFREQ_VLV, and use VLV_DISPLAY_BASE.
(Ville).
	Remove cdclk_ratio[] table, and calculate the cdclk ratio instead.
(Ville).
 	Change the shift then mask for reg read, to mask first, then shift.
(Ville).
	Remove the gmbus frequency calculation = cdclk/1.01.  Based on BIOS
programming, gmbus frequency = cdclk frequency. (Ville)
	Add get_disp_clk_div, which can use to get cdclk/czclk divide.

v4: Fix the mmio_offset base for CZCLK_CDCLK_FREQ_RATIO, gmbus_freq
calculation, and duplicate check for gmbus_freq. (Ville)

In VLV, the spec is wrong about 4Mhz reference frequency for GMBUS. It
should be 1Mhz.

Signed-off-by: Chon Ming Lee <chon.ming.lee@intel.com>
[danvet: Add the comment Ville suggested. Also appease checkpatch a
bit.]
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

1 files changed, 8 insertions, 0 deletions

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 00fda45728d7..33bb4750516a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -382,6 +382,8 @@
 #define   FB_FMAX_VMIN_FREQ_LO_MASK             0xf8000000
 
 /* vlv2 north clock has */
+#define CCK_FUSE_REG                            0x8
+#define  CCK_FUSE_HPLL_FREQ_MASK                0x3
 #define CCK_REG_DSI_PLL_FUSE                    0x44
 #define CCK_REG_DSI_PLL_CONTROL                 0x48
 #define  DSI_PLL_VCO_EN                         (1 << 31)
@@ -1429,6 +1431,12 @@
 
 #define MI_ARB_VLV              (VLV_DISPLAY_BASE + 0x6504)
 
+#define CZCLK_CDCLK_FREQ_RATIO  (VLV_DISPLAY_BASE + 0x6508)
+#define   CDCLK_FREQ_SHIFT      4
+#define   CDCLK_FREQ_MASK       (0x1f << CDCLK_FREQ_SHIFT)
+#define   CZCLK_FREQ_MASK       0xf
+#define GMBUSFREQ_VLV           (VLV_DISPLAY_BASE + 0x6510)
+
 /*
  * Palette regs
  */