drm/i915: More s/IS_IRONLAKE/HAS_PCH_SPLIT for Sandybridge.

I think this is pretty much correct.  Not really tested.

Signed-off-by: Eric Anholt <eric@anholt.net>

1 files changed, 1 insertions, 1 deletions

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index f93f822fa72c..5388354da0d1 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -166,7 +166,7 @@ void intel_enable_asle (struct drm_device *dev)
 {
         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 
-        if (IS_IRONLAKE(dev))
+        if (HAS_PCH_SPLIT(dev))
                 ironlake_enable_display_irq(dev_priv, DE_GSE);
         else
                 i915_enable_pipestat(dev_priv, 1,