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authorDaniel Vetter <daniel.vetter@ffwll.ch>2014-11-04 09:52:22 -0500
committerDaniel Vetter <daniel.vetter@ffwll.ch>2014-12-03 03:29:36 -0500
commitaaecdf611a05cac26a94713bad25297e60225c29 (patch)
tree50d4612d4e0b23820b68a80b5d529bcf0e18549b /drivers/gpu/drm/i915/i915_irq.c
parentd472fcc8379c062bd56a3876fc6ef22258f14a91 (diff)
drm/i915: Stop gathering error states for CS error interrupts
There's quite a few bug reports with error states where the error reasons makes just about no sense at all. Like dying on tlbs for a display plane that's not even there. Also users don't really report a lot of bad side effects generally, just the error states. Furthermore we don't even enable these interrupts any more on gen5+ (though the handling code is still there). So this mostly concerns old platforms. Given all that lets make our lives a bit easier and stop capturing error states, in the hopes that we can just ignore them. In case that's not true and the gpu indeed dies the hangcheck should eventually kick in. And I've left some debug log in to make this case noticeble. Referenced bug is just an example. v2: Fix missing \n Jani spotted. References: https://bugs.freedesktop.org/show_bug.cgi?id=82095 References: https://bugs.freedesktop.org/show_bug.cgi?id=85944 Signed-off-by: Daniel Vetter <daniel.vetter@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_irq.c')
-rw-r--r--drivers/gpu/drm/i915/i915_irq.c25
1 files changed, 7 insertions, 18 deletions
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 5908580d7c15..85c15ba6e735 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1339,10 +1339,8 @@ static void snb_gt_irq_handler(struct drm_device *dev,
1339 1339
1340 if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT | 1340 if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
1341 GT_BSD_CS_ERROR_INTERRUPT | 1341 GT_BSD_CS_ERROR_INTERRUPT |
1342 GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) { 1342 GT_RENDER_CS_MASTER_ERROR_INTERRUPT))
1343 i915_handle_error(dev, false, "GT error interrupt 0x%08x", 1343 DRM_DEBUG("Command parser error, gt_iir 0x%08x\n", gt_iir);
1344 gt_iir);
1345 }
1346 1344
1347 if (gt_iir & GT_PARITY_ERROR(dev)) 1345 if (gt_iir & GT_PARITY_ERROR(dev))
1348 ivybridge_parity_error_irq_handler(dev, gt_iir); 1346 ivybridge_parity_error_irq_handler(dev, gt_iir);
@@ -1731,11 +1729,8 @@ static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1731 if (pm_iir & PM_VEBOX_USER_INTERRUPT) 1729 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
1732 notify_ring(dev_priv->dev, &dev_priv->ring[VECS]); 1730 notify_ring(dev_priv->dev, &dev_priv->ring[VECS]);
1733 1731
1734 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) { 1732 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT)
1735 i915_handle_error(dev_priv->dev, false, 1733 DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir);
1736 "VEBOX CS error interrupt 0x%08x",
1737 pm_iir);
1738 }
1739 } 1734 }
1740} 1735}
1741 1736
@@ -3746,9 +3741,7 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg)
3746 */ 3741 */
3747 spin_lock(&dev_priv->irq_lock); 3742 spin_lock(&dev_priv->irq_lock);
3748 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) 3743 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3749 i915_handle_error(dev, false, 3744 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
3750 "Command parser error, iir 0x%08x",
3751 iir);
3752 3745
3753 for_each_pipe(dev_priv, pipe) { 3746 for_each_pipe(dev_priv, pipe) {
3754 int reg = PIPESTAT(pipe); 3747 int reg = PIPESTAT(pipe);
@@ -3929,9 +3922,7 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
3929 */ 3922 */
3930 spin_lock(&dev_priv->irq_lock); 3923 spin_lock(&dev_priv->irq_lock);
3931 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) 3924 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3932 i915_handle_error(dev, false, 3925 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
3933 "Command parser error, iir 0x%08x",
3934 iir);
3935 3926
3936 for_each_pipe(dev_priv, pipe) { 3927 for_each_pipe(dev_priv, pipe) {
3937 int reg = PIPESTAT(pipe); 3928 int reg = PIPESTAT(pipe);
@@ -4154,9 +4145,7 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
4154 */ 4145 */
4155 spin_lock(&dev_priv->irq_lock); 4146 spin_lock(&dev_priv->irq_lock);
4156 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) 4147 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
4157 i915_handle_error(dev, false, 4148 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
4158 "Command parser error, iir 0x%08x",
4159 iir);
4160 4149
4161 for_each_pipe(dev_priv, pipe) { 4150 for_each_pipe(dev_priv, pipe) {
4162 int reg = PIPESTAT(pipe); 4151 int reg = PIPESTAT(pipe);