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authorKristian Høgsberg <krh@bitplanet.net>2009-11-18 11:25:18 -0500
committerEric Anholt <eric@anholt.net>2009-12-01 12:10:35 -0500
commit6b95a207c1fd552e7d017837c5eaf1b0173a48c9 (patch)
tree02aed1633ab954faa3eea4b2a12775c28a1c5410 /drivers/gpu/drm/i915/i915_irq.c
parentf40d6817a5c2bf84f5fe7b5d1a83f1e8f8669951 (diff)
drm/i915: Add intel implementation of the pageflip ioctl
Acked-by: Jakob Bornecrantz <jakob@vmware.com> Acked-by: Thomas Hellström <thomas@shipmail.org> Review-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Jesse "Orange Smoothie" Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Kristian Høgsberg <krh@bitplanet.net> Signed-off-by: Eric Anholt <eric@anholt.net>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_irq.c')
-rw-r--r--drivers/gpu/drm/i915/i915_irq.c19
1 files changed, 15 insertions, 4 deletions
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 77bc1d28f744..e2d01b3fa171 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -43,10 +43,13 @@
43 * we leave them always unmasked in IMR and then control enabling them through 43 * we leave them always unmasked in IMR and then control enabling them through
44 * PIPESTAT alone. 44 * PIPESTAT alone.
45 */ 45 */
46#define I915_INTERRUPT_ENABLE_FIX (I915_ASLE_INTERRUPT | \ 46#define I915_INTERRUPT_ENABLE_FIX \
47 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \ 47 (I915_ASLE_INTERRUPT | \
48 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | \ 48 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \
49 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) 49 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | \
50 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | \
51 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | \
52 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
50 53
51/** Interrupts that we mask and unmask at runtime. */ 54/** Interrupts that we mask and unmask at runtime. */
52#define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT) 55#define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT)
@@ -643,14 +646,22 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
643 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD); 646 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
644 } 647 }
645 648
649 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT)
650 intel_prepare_page_flip(dev, 0);
651
652 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT)
653 intel_prepare_page_flip(dev, 1);
654
646 if (pipea_stats & vblank_status) { 655 if (pipea_stats & vblank_status) {
647 vblank++; 656 vblank++;
648 drm_handle_vblank(dev, 0); 657 drm_handle_vblank(dev, 0);
658 intel_finish_page_flip(dev, 0);
649 } 659 }
650 660
651 if (pipeb_stats & vblank_status) { 661 if (pipeb_stats & vblank_status) {
652 vblank++; 662 vblank++;
653 drm_handle_vblank(dev, 1); 663 drm_handle_vblank(dev, 1);
664 intel_finish_page_flip(dev, 1);
654 } 665 }
655 666
656 if ((pipeb_stats & I915_LEGACY_BLC_EVENT_STATUS) || 667 if ((pipeb_stats & I915_LEGACY_BLC_EVENT_STATUS) ||