diff options
author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2014-04-09 06:28:49 -0400 |
---|---|---|
committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2014-05-20 09:29:15 -0400 |
commit | 3278f67fa7c99d6739304ffe3c04fadd6d74ff80 (patch) | |
tree | 872272096412d99757b90ea0d96e780072c5b339 /drivers/gpu/drm/i915/i915_irq.c | |
parent | 724a6905eabf513aa2544c32625d0a5cbea38845 (diff) |
drrm/i915/chv: Use valleyview_pipestat_irq_handler() for CHV
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Antti Koskipää <antti.koskipaa@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_irq.c')
-rw-r--r-- | drivers/gpu/drm/i915/i915_irq.c | 90 |
1 files changed, 17 insertions, 73 deletions
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 443062faff5e..4811908ee551 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c | |||
@@ -1672,6 +1672,9 @@ static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir) | |||
1672 | case PIPE_B: | 1672 | case PIPE_B: |
1673 | iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT; | 1673 | iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT; |
1674 | break; | 1674 | break; |
1675 | case PIPE_C: | ||
1676 | iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT; | ||
1677 | break; | ||
1675 | } | 1678 | } |
1676 | if (iir & iir_bit) | 1679 | if (iir & iir_bit) |
1677 | mask |= dev_priv->pipestat_irq_mask[pipe]; | 1680 | mask |= dev_priv->pipestat_irq_mask[pipe]; |
@@ -1783,78 +1786,22 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg) | |||
1783 | struct drm_i915_private *dev_priv = dev->dev_private; | 1786 | struct drm_i915_private *dev_priv = dev->dev_private; |
1784 | u32 master_ctl, iir; | 1787 | u32 master_ctl, iir; |
1785 | irqreturn_t ret = IRQ_NONE; | 1788 | irqreturn_t ret = IRQ_NONE; |
1786 | unsigned int pipes = 0; | ||
1787 | |||
1788 | master_ctl = I915_READ(GEN8_MASTER_IRQ); | ||
1789 | |||
1790 | I915_WRITE(GEN8_MASTER_IRQ, 0); | ||
1791 | |||
1792 | ret = gen8_gt_irq_handler(dev, dev_priv, master_ctl); | ||
1793 | 1789 | ||
1790 | master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~DE_MASTER_IRQ_CONTROL; | ||
1794 | iir = I915_READ(VLV_IIR); | 1791 | iir = I915_READ(VLV_IIR); |
1795 | 1792 | ||
1796 | if (iir & (I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT)) | 1793 | if (master_ctl == 0 && iir == 0) |
1797 | pipes |= 1 << 0; | 1794 | return IRQ_NONE; |
1798 | if (iir & (I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT)) | ||
1799 | pipes |= 1 << 1; | ||
1800 | if (iir & (I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT | I915_DISPLAY_PIPE_C_EVENT_INTERRUPT)) | ||
1801 | pipes |= 1 << 2; | ||
1802 | |||
1803 | if (pipes) { | ||
1804 | u32 pipe_stats[I915_MAX_PIPES] = {}; | ||
1805 | unsigned long irqflags; | ||
1806 | int pipe; | ||
1807 | |||
1808 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | ||
1809 | for_each_pipe(pipe) { | ||
1810 | unsigned int reg; | ||
1811 | |||
1812 | if (!(pipes & (1 << pipe))) | ||
1813 | continue; | ||
1814 | |||
1815 | reg = PIPESTAT(pipe); | ||
1816 | pipe_stats[pipe] = I915_READ(reg); | ||
1817 | |||
1818 | /* | ||
1819 | * Clear the PIPE*STAT regs before the IIR | ||
1820 | */ | ||
1821 | if (pipe_stats[pipe] & 0x8000ffff) { | ||
1822 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) | ||
1823 | DRM_DEBUG_DRIVER("pipe %c underrun\n", | ||
1824 | pipe_name(pipe)); | ||
1825 | I915_WRITE(reg, pipe_stats[pipe]); | ||
1826 | } | ||
1827 | } | ||
1828 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | ||
1829 | 1795 | ||
1830 | for_each_pipe(pipe) { | 1796 | I915_WRITE(GEN8_MASTER_IRQ, 0); |
1831 | if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS) | ||
1832 | drm_handle_vblank(dev, pipe); | ||
1833 | 1797 | ||
1834 | if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) { | 1798 | gen8_gt_irq_handler(dev, dev_priv, master_ctl); |
1835 | intel_prepare_page_flip(dev, pipe); | ||
1836 | intel_finish_page_flip(dev, pipe); | ||
1837 | } | ||
1838 | } | ||
1839 | 1799 | ||
1840 | if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) | 1800 | valleyview_pipestat_irq_handler(dev, iir); |
1841 | gmbus_irq_handler(dev); | ||
1842 | |||
1843 | ret = IRQ_HANDLED; | ||
1844 | } | ||
1845 | 1801 | ||
1846 | /* Consume port. Then clear IIR or we'll miss events */ | 1802 | /* Consume port. Then clear IIR or we'll miss events */ |
1847 | if (iir & I915_DISPLAY_PORT_INTERRUPT) { | 1803 | if (iir & I915_DISPLAY_PORT_INTERRUPT) { |
1848 | u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); | 1804 | i9xx_hpd_irq_handler(dev); |
1849 | |||
1850 | I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); | ||
1851 | |||
1852 | DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n", | ||
1853 | hotplug_status); | ||
1854 | if (hotplug_status & HOTPLUG_INT_STATUS_I915) | ||
1855 | queue_work(dev_priv->wq, | ||
1856 | &dev_priv->hotplug_work); | ||
1857 | |||
1858 | ret = IRQ_HANDLED; | 1805 | ret = IRQ_HANDLED; |
1859 | } | 1806 | } |
1860 | 1807 | ||
@@ -1863,6 +1810,8 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg) | |||
1863 | I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL); | 1810 | I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL); |
1864 | POSTING_READ(GEN8_MASTER_IRQ); | 1811 | POSTING_READ(GEN8_MASTER_IRQ); |
1865 | 1812 | ||
1813 | ret = IRQ_HANDLED; | ||
1814 | |||
1866 | return ret; | 1815 | return ret; |
1867 | } | 1816 | } |
1868 | 1817 | ||
@@ -3492,12 +3441,10 @@ static int cherryview_irq_postinstall(struct drm_device *dev) | |||
3492 | struct drm_i915_private *dev_priv = dev->dev_private; | 3441 | struct drm_i915_private *dev_priv = dev->dev_private; |
3493 | u32 enable_mask = I915_DISPLAY_PORT_INTERRUPT | | 3442 | u32 enable_mask = I915_DISPLAY_PORT_INTERRUPT | |
3494 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | 3443 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | |
3495 | I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT | | ||
3496 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | 3444 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | |
3497 | I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT | | 3445 | I915_DISPLAY_PIPE_C_EVENT_INTERRUPT; |
3498 | I915_DISPLAY_PIPE_C_EVENT_INTERRUPT | | 3446 | u32 pipestat_enable = PLANE_FLIP_DONE_INT_STATUS_VLV | |
3499 | I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT; | 3447 | PIPE_CRC_DONE_INTERRUPT_STATUS; |
3500 | u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV; | ||
3501 | unsigned long irqflags; | 3448 | unsigned long irqflags; |
3502 | int pipe; | 3449 | int pipe; |
3503 | 3450 | ||
@@ -3505,16 +3452,13 @@ static int cherryview_irq_postinstall(struct drm_device *dev) | |||
3505 | * Leave vblank interrupts masked initially. enable/disable will | 3452 | * Leave vblank interrupts masked initially. enable/disable will |
3506 | * toggle them based on usage. | 3453 | * toggle them based on usage. |
3507 | */ | 3454 | */ |
3508 | dev_priv->irq_mask = ~enable_mask | | 3455 | dev_priv->irq_mask = ~enable_mask; |
3509 | I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT | | ||
3510 | I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT | | ||
3511 | I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT; | ||
3512 | 3456 | ||
3513 | for_each_pipe(pipe) | 3457 | for_each_pipe(pipe) |
3514 | I915_WRITE(PIPESTAT(pipe), 0xffff); | 3458 | I915_WRITE(PIPESTAT(pipe), 0xffff); |
3515 | 3459 | ||
3516 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | 3460 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
3517 | i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE); | 3461 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); |
3518 | for_each_pipe(pipe) | 3462 | for_each_pipe(pipe) |
3519 | i915_enable_pipestat(dev_priv, pipe, pipestat_enable); | 3463 | i915_enable_pipestat(dev_priv, pipe, pipestat_enable); |
3520 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | 3464 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |