diff options
author | Daniel Vetter <daniel.vetter@ffwll.ch> | 2013-01-24 17:44:57 -0500 |
---|---|---|
committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2013-01-31 05:50:06 -0500 |
commit | 960e3e429f0c7d9e27e60cf8fa2f51ada71e717e (patch) | |
tree | 9c03c6f729fc300ec977a29833c48d1e4f463628 /drivers/gpu/drm/i915/i915_gem_gtt.c | |
parent | def886c3768d24c4e0aa56ff98b5a468c2b5c9bf (diff) |
drm/i915: pte_encode is gen6+
All the other gen6+ hw code has the gen6_ prefix, so be consistent
about it.
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_gem_gtt.c')
-rw-r--r-- | drivers/gpu/drm/i915/i915_gem_gtt.c | 24 |
1 files changed, 14 insertions, 10 deletions
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index f63dbc7a89ce..d17198210568 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c | |||
@@ -44,9 +44,9 @@ typedef uint32_t gtt_pte_t; | |||
44 | #define GEN6_PTE_CACHE_LLC_MLC (3 << 1) | 44 | #define GEN6_PTE_CACHE_LLC_MLC (3 << 1) |
45 | #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) | 45 | #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) |
46 | 46 | ||
47 | static inline gtt_pte_t pte_encode(struct drm_device *dev, | 47 | static inline gtt_pte_t gen6_pte_encode(struct drm_device *dev, |
48 | dma_addr_t addr, | 48 | dma_addr_t addr, |
49 | enum i915_cache_level level) | 49 | enum i915_cache_level level) |
50 | { | 50 | { |
51 | gtt_pte_t pte = GEN6_PTE_VALID; | 51 | gtt_pte_t pte = GEN6_PTE_VALID; |
52 | pte |= GEN6_PTE_ADDR_ENCODE(addr); | 52 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
@@ -87,8 +87,9 @@ static void gen6_ppgtt_clear_range(struct i915_hw_ppgtt *ppgtt, | |||
87 | unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES; | 87 | unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES; |
88 | unsigned last_pte, i; | 88 | unsigned last_pte, i; |
89 | 89 | ||
90 | scratch_pte = pte_encode(ppgtt->dev, ppgtt->scratch_page_dma_addr, | 90 | scratch_pte = gen6_pte_encode(ppgtt->dev, |
91 | I915_CACHE_LLC); | 91 | ppgtt->scratch_page_dma_addr, |
92 | I915_CACHE_LLC); | ||
92 | 93 | ||
93 | while (num_entries) { | 94 | while (num_entries) { |
94 | last_pte = first_pte + num_entries; | 95 | last_pte = first_pte + num_entries; |
@@ -131,8 +132,8 @@ static void gen6_ppgtt_insert_entries(struct i915_hw_ppgtt *ppgtt, | |||
131 | 132 | ||
132 | for (j = first_pte; j < I915_PPGTT_PT_ENTRIES; j++) { | 133 | for (j = first_pte; j < I915_PPGTT_PT_ENTRIES; j++) { |
133 | page_addr = sg_dma_address(sg) + (m << PAGE_SHIFT); | 134 | page_addr = sg_dma_address(sg) + (m << PAGE_SHIFT); |
134 | pt_vaddr[j] = pte_encode(ppgtt->dev, page_addr, | 135 | pt_vaddr[j] = gen6_pte_encode(ppgtt->dev, page_addr, |
135 | cache_level); | 136 | cache_level); |
136 | 137 | ||
137 | /* grab the next page */ | 138 | /* grab the next page */ |
138 | if (++m == segment_len) { | 139 | if (++m == segment_len) { |
@@ -421,7 +422,8 @@ static void gen6_ggtt_insert_entries(struct drm_device *dev, | |||
421 | len = sg_dma_len(sg) >> PAGE_SHIFT; | 422 | len = sg_dma_len(sg) >> PAGE_SHIFT; |
422 | for (m = 0; m < len; m++) { | 423 | for (m = 0; m < len; m++) { |
423 | addr = sg_dma_address(sg) + (m << PAGE_SHIFT); | 424 | addr = sg_dma_address(sg) + (m << PAGE_SHIFT); |
424 | iowrite32(pte_encode(dev, addr, level), >t_entries[i]); | 425 | iowrite32(gen6_pte_encode(dev, addr, level), |
426 | >t_entries[i]); | ||
425 | i++; | 427 | i++; |
426 | } | 428 | } |
427 | } | 429 | } |
@@ -433,7 +435,8 @@ static void gen6_ggtt_insert_entries(struct drm_device *dev, | |||
433 | * hardware should work, we must keep this posting read for paranoia. | 435 | * hardware should work, we must keep this posting read for paranoia. |
434 | */ | 436 | */ |
435 | if (i != 0) | 437 | if (i != 0) |
436 | WARN_ON(readl(>t_entries[i-1]) != pte_encode(dev, addr, level)); | 438 | WARN_ON(readl(>t_entries[i-1]) |
439 | != gen6_pte_encode(dev, addr, level)); | ||
437 | 440 | ||
438 | /* This next bit makes the above posting read even more important. We | 441 | /* This next bit makes the above posting read even more important. We |
439 | * want to flush the TLBs only after we're certain all the PTE updates | 442 | * want to flush the TLBs only after we're certain all the PTE updates |
@@ -458,7 +461,8 @@ static void gen6_ggtt_clear_range(struct drm_device *dev, | |||
458 | first_entry, num_entries, max_entries)) | 461 | first_entry, num_entries, max_entries)) |
459 | num_entries = max_entries; | 462 | num_entries = max_entries; |
460 | 463 | ||
461 | scratch_pte = pte_encode(dev, dev_priv->gtt.scratch_page_dma, I915_CACHE_LLC); | 464 | scratch_pte = gen6_pte_encode(dev, dev_priv->gtt.scratch_page_dma, |
465 | I915_CACHE_LLC); | ||
462 | for (i = 0; i < num_entries; i++) | 466 | for (i = 0; i < num_entries; i++) |
463 | iowrite32(scratch_pte, >t_base[i]); | 467 | iowrite32(scratch_pte, >t_base[i]); |
464 | readl(gtt_base); | 468 | readl(gtt_base); |