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authorChris Wilson <chris@chris-wilson.co.uk>2011-02-03 06:57:46 -0500
committerChris Wilson <chris@chris-wilson.co.uk>2011-02-07 09:59:18 -0500
commitdb53a302611c06bde01851f61fa0675a84ca018c (patch)
treec1504cf7929af3372a3d96c3a87ee754ceb1eff9 /drivers/gpu/drm/i915/i915_gem_execbuffer.c
parentd9bc7e9f32716901c617e1f0fb6ce0f74f172686 (diff)
drm/i915: Refine tracepoints
A lot of minor tweaks to fix the tracepoints, improve the outputting for ftrace, and to generally make the tracepoints useful again. It is a start and enough to begin identifying performance issues and gaps in our coverage. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_gem_execbuffer.c')
-rw-r--r--drivers/gpu/drm/i915/i915_gem_execbuffer.c58
1 files changed, 13 insertions, 45 deletions
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index b0a0238c36d1..84fa24e6cca8 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -282,21 +282,6 @@ i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj,
282 282
283 target_offset = to_intel_bo(target_obj)->gtt_offset; 283 target_offset = to_intel_bo(target_obj)->gtt_offset;
284 284
285#if WATCH_RELOC
286 DRM_INFO("%s: obj %p offset %08x target %d "
287 "read %08x write %08x gtt %08x "
288 "presumed %08x delta %08x\n",
289 __func__,
290 obj,
291 (int) reloc->offset,
292 (int) reloc->target_handle,
293 (int) reloc->read_domains,
294 (int) reloc->write_domain,
295 (int) target_offset,
296 (int) reloc->presumed_offset,
297 reloc->delta);
298#endif
299
300 /* The target buffer should have appeared before us in the 285 /* The target buffer should have appeared before us in the
301 * exec_object list, so it should have a GTT space bound by now. 286 * exec_object list, so it should have a GTT space bound by now.
302 */ 287 */
@@ -747,8 +732,7 @@ i915_gem_execbuffer_flush(struct drm_device *dev,
747 if ((flush_domains | invalidate_domains) & I915_GEM_GPU_DOMAINS) { 732 if ((flush_domains | invalidate_domains) & I915_GEM_GPU_DOMAINS) {
748 for (i = 0; i < I915_NUM_RINGS; i++) 733 for (i = 0; i < I915_NUM_RINGS; i++)
749 if (flush_rings & (1 << i)) { 734 if (flush_rings & (1 << i)) {
750 ret = i915_gem_flush_ring(dev, 735 ret = i915_gem_flush_ring(&dev_priv->ring[i],
751 &dev_priv->ring[i],
752 invalidate_domains, 736 invalidate_domains,
753 flush_domains); 737 flush_domains);
754 if (ret) 738 if (ret)
@@ -787,7 +771,7 @@ i915_gem_execbuffer_sync_rings(struct drm_i915_gem_object *obj,
787 if (request == NULL) 771 if (request == NULL)
788 return -ENOMEM; 772 return -ENOMEM;
789 773
790 ret = i915_add_request(obj->base.dev, NULL, request, from); 774 ret = i915_add_request(from, NULL, request);
791 if (ret) { 775 if (ret) {
792 kfree(request); 776 kfree(request);
793 return ret; 777 return ret;
@@ -815,12 +799,6 @@ i915_gem_execbuffer_move_to_gpu(struct intel_ring_buffer *ring,
815 i915_gem_object_set_to_gpu_domain(obj, ring, &cd); 799 i915_gem_object_set_to_gpu_domain(obj, ring, &cd);
816 800
817 if (cd.invalidate_domains | cd.flush_domains) { 801 if (cd.invalidate_domains | cd.flush_domains) {
818#if WATCH_EXEC
819 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
820 __func__,
821 cd.invalidate_domains,
822 cd.flush_domains);
823#endif
824 ret = i915_gem_execbuffer_flush(ring->dev, 802 ret = i915_gem_execbuffer_flush(ring->dev,
825 cd.invalidate_domains, 803 cd.invalidate_domains,
826 cd.flush_domains, 804 cd.flush_domains,
@@ -924,6 +902,10 @@ i915_gem_execbuffer_move_to_active(struct list_head *objects,
924 struct drm_i915_gem_object *obj; 902 struct drm_i915_gem_object *obj;
925 903
926 list_for_each_entry(obj, objects, exec_list) { 904 list_for_each_entry(obj, objects, exec_list) {
905 u32 old_read = obj->base.read_domains;
906 u32 old_write = obj->base.write_domain;
907
908
927 obj->base.read_domains = obj->base.pending_read_domains; 909 obj->base.read_domains = obj->base.pending_read_domains;
928 obj->base.write_domain = obj->base.pending_write_domain; 910 obj->base.write_domain = obj->base.pending_write_domain;
929 obj->fenced_gpu_access = obj->pending_fenced_gpu_access; 911 obj->fenced_gpu_access = obj->pending_fenced_gpu_access;
@@ -937,9 +919,7 @@ i915_gem_execbuffer_move_to_active(struct list_head *objects,
937 intel_mark_busy(ring->dev, obj); 919 intel_mark_busy(ring->dev, obj);
938 } 920 }
939 921
940 trace_i915_gem_object_change_domain(obj, 922 trace_i915_gem_object_change_domain(obj, old_read, old_write);
941 obj->base.read_domains,
942 obj->base.write_domain);
943 } 923 }
944} 924}
945 925
@@ -961,14 +941,14 @@ i915_gem_execbuffer_retire_commands(struct drm_device *dev,
961 if (INTEL_INFO(dev)->gen >= 4) 941 if (INTEL_INFO(dev)->gen >= 4)
962 invalidate |= I915_GEM_DOMAIN_SAMPLER; 942 invalidate |= I915_GEM_DOMAIN_SAMPLER;
963 if (ring->flush(ring, invalidate, 0)) { 943 if (ring->flush(ring, invalidate, 0)) {
964 i915_gem_next_request_seqno(dev, ring); 944 i915_gem_next_request_seqno(ring);
965 return; 945 return;
966 } 946 }
967 947
968 /* Add a breadcrumb for the completion of the batch buffer */ 948 /* Add a breadcrumb for the completion of the batch buffer */
969 request = kzalloc(sizeof(*request), GFP_KERNEL); 949 request = kzalloc(sizeof(*request), GFP_KERNEL);
970 if (request == NULL || i915_add_request(dev, file, request, ring)) { 950 if (request == NULL || i915_add_request(ring, file, request)) {
971 i915_gem_next_request_seqno(dev, ring); 951 i915_gem_next_request_seqno(ring);
972 kfree(request); 952 kfree(request);
973 } 953 }
974} 954}
@@ -998,10 +978,6 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
998 if (ret) 978 if (ret)
999 return ret; 979 return ret;
1000 980
1001#if WATCH_EXEC
1002 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
1003 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
1004#endif
1005 switch (args->flags & I915_EXEC_RING_MASK) { 981 switch (args->flags & I915_EXEC_RING_MASK) {
1006 case I915_EXEC_DEFAULT: 982 case I915_EXEC_DEFAULT:
1007 case I915_EXEC_RENDER: 983 case I915_EXEC_RENDER:
@@ -1172,7 +1148,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
1172 if (ret) 1148 if (ret)
1173 goto err; 1149 goto err;
1174 1150
1175 seqno = i915_gem_next_request_seqno(dev, ring); 1151 seqno = i915_gem_next_request_seqno(ring);
1176 for (i = 0; i < ARRAY_SIZE(ring->sync_seqno); i++) { 1152 for (i = 0; i < ARRAY_SIZE(ring->sync_seqno); i++) {
1177 if (seqno < ring->sync_seqno[i]) { 1153 if (seqno < ring->sync_seqno[i]) {
1178 /* The GPU can not handle its semaphore value wrapping, 1154 /* The GPU can not handle its semaphore value wrapping,
@@ -1187,6 +1163,8 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
1187 } 1163 }
1188 } 1164 }
1189 1165
1166 trace_i915_gem_ring_dispatch(ring, seqno);
1167
1190 exec_start = batch_obj->gtt_offset + args->batch_start_offset; 1168 exec_start = batch_obj->gtt_offset + args->batch_start_offset;
1191 exec_len = args->batch_len; 1169 exec_len = args->batch_len;
1192 if (cliprects) { 1170 if (cliprects) {
@@ -1243,11 +1221,6 @@ i915_gem_execbuffer(struct drm_device *dev, void *data,
1243 struct drm_i915_gem_exec_object2 *exec2_list = NULL; 1221 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
1244 int ret, i; 1222 int ret, i;
1245 1223
1246#if WATCH_EXEC
1247 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
1248 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
1249#endif
1250
1251 if (args->buffer_count < 1) { 1224 if (args->buffer_count < 1) {
1252 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count); 1225 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
1253 return -EINVAL; 1226 return -EINVAL;
@@ -1328,11 +1301,6 @@ i915_gem_execbuffer2(struct drm_device *dev, void *data,
1328 struct drm_i915_gem_exec_object2 *exec2_list = NULL; 1301 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
1329 int ret; 1302 int ret;
1330 1303
1331#if WATCH_EXEC
1332 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
1333 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
1334#endif
1335
1336 if (args->buffer_count < 1) { 1304 if (args->buffer_count < 1) {
1337 DRM_ERROR("execbuf2 with %d buffers\n", args->buffer_count); 1305 DRM_ERROR("execbuf2 with %d buffers\n", args->buffer_count);
1338 return -EINVAL; 1306 return -EINVAL;