drm/i915: Allow DRM_ROOT_ONLY|DRM_MASTER to submit privileged batchbuffers

With the introduction of per-process GTT space, the hardware designers
thought it wise to also limit the ability to write to MMIO space to only
a "secure" batch buffer. The ability to rewrite registers is the only
way to program the hardware to perform certain operations like scanline
waits (required for tear-free windowed updates). So we either have a
choice of adding an interface to perform those synchronized updates
inside the kernel, or we permit certain processes the ability to write
to the "safe" registers from within its command stream. This patch
exposes the ability to submit a SECURE batch buffer to
DRM_ROOT_ONLY|DRM_MASTER processes.

v2: Haswell split up bit8 into a ppgtt bit (still bit8) and a security
bit (bit 13, accidentally not set). Also add a comment explaining why
secure batches need a global gtt binding.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> (v1)
[danvet: added hsw fixup.]
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

1 files changed, 22 insertions, 3 deletions

diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 6a2f3e50c714..afbc9240a992 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -801,6 +801,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
         u32 exec_start, exec_len;
         u32 seqno;
         u32 mask;
+        u32 flags;
         int ret, mode, i;
 
         if (!i915_gem_check_execbuffer(args)) {
@@ -812,6 +813,14 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
         if (ret)
                 return ret;
 
+        flags = 0;
+        if (args->flags & I915_EXEC_SECURE) {
+                if (!file->is_master || !capable(CAP_SYS_ADMIN))
+                    return -EPERM;
+
+                flags |= I915_DISPATCH_SECURE;
+        }
+
         switch (args->flags & I915_EXEC_RING_MASK) {
         case I915_EXEC_DEFAULT:
         case I915_EXEC_RENDER:
@@ -984,6 +993,13 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
         }
         batch_obj->base.pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
 
+        /* snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure
+         * batch" bit. Hence we need to pin secure batches into the global gtt.
+         * hsw should have this fixed, but let's be paranoid and do it
+         * unconditionally for now. */
+        if (flags & I915_DISPATCH_SECURE && !batch_obj->has_global_gtt_mapping)
+                i915_gem_gtt_bind_object(batch_obj, batch_obj->cache_level);
+
         ret = i915_gem_execbuffer_move_to_gpu(ring, &objects);
         if (ret)
                 goto err;
@@ -1029,7 +1045,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
                         goto err;
         }
 
-        trace_i915_gem_ring_dispatch(ring, seqno);
+        trace_i915_gem_ring_dispatch(ring, seqno, flags);
 
         exec_start = batch_obj->gtt_offset + args->batch_start_offset;
         exec_len = args->batch_len;
@@ -1041,12 +1057,15 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
                                 goto err;
 
                         ret = ring->dispatch_execbuffer(ring,
-                                                        exec_start, exec_len);
+                                                        exec_start, exec_len,
+                                                        flags);
                         if (ret)
                                 goto err;
                 }
         } else {
-                ret = ring->dispatch_execbuffer(ring, exec_start, exec_len);
+                ret = ring->dispatch_execbuffer(ring,
+                                                exec_start, exec_len,
+                                                flags);
                 if (ret)
                         goto err;
         }