drm/i915: possibly invalidate TLB before context switch

From http://intellinuxgraphics.org/documentation/SNB/IHD_OS_Vol1_Part3.pdf

[DevSNB] If Flush TLB invalidation Mode is enabled it's the driver's
responsibility to invalidate the TLBs at least once after the previous
context switch after any GTT mappings changed (including new GTT
entries).  This can be done by a pipelined PIPE_CONTROL with TLB inv bit
set immediately before MI_SET_CONTEXT.

On GEN7 the invalidation mode is explicitly set, but this appears to be
lacking for GEN6. Since I don't know the history on this, I've decided
to dynamically read the value at ring init time, and use that value
throughout.

v2: better comment (daniel)

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>

1 files changed, 11 insertions, 0 deletions

diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index d49d5fc0a592..fb1e1d22572c 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -324,6 +324,17 @@ mi_set_context(struct intel_ring_buffer *ring,
 {
         int ret;
 
+        /* w/a: If Flush TLB Invalidation Mode is enabled, driver must do a TLB
+         * invalidation prior to MI_SET_CONTEXT. On GEN6 we don't set the value
+         * explicitly, so we rely on the value at ring init, stored in
+         * itlb_before_ctx_switch.
+         */
+        if (IS_GEN6(ring->dev) && ring->itlb_before_ctx_switch) {
+                ret = ring->flush(ring, 0, 0);
+                if (ret)
+                        return ret;
+        }
+
         ret = intel_ring_begin(ring, 6);
         if (ret)
                 return ret;