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authorChris Wilson <chris@chris-wilson.co.uk>2010-11-12 05:46:37 -0500
committerChris Wilson <chris@chris-wilson.co.uk>2010-11-23 15:19:14 -0500
commitb6913e4bdb09134dbdccd613e880d413b5911591 (patch)
tree6e9cc939576ecff515c749c7e938bb2c2881fe12 /drivers/gpu/drm/i915/i915_gem.c
parent748ebc6017a943ec065e653e975a5e8dace77ac6 (diff)
drm/i915: Move the implementation details of PIPE_CONTROL to the ringbuffer
The pipe control object is allocated by the device for the sole use of the render ringbuffer. Move this detail from the general code to the render ring buffer initialisation. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_gem.c')
-rw-r--r--drivers/gpu/drm/i915/i915_gem.c70
1 files changed, 1 insertions, 69 deletions
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 8e3f1de681ed..027212e5c34a 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4625,78 +4625,15 @@ i915_gem_idle(struct drm_device *dev)
4625 return 0; 4625 return 0;
4626} 4626}
4627 4627
4628/*
4629 * 965+ support PIPE_CONTROL commands, which provide finer grained control
4630 * over cache flushing.
4631 */
4632static int
4633i915_gem_init_pipe_control(struct drm_device *dev)
4634{
4635 drm_i915_private_t *dev_priv = dev->dev_private;
4636 struct drm_i915_gem_object *obj;
4637 int ret;
4638
4639 obj = i915_gem_alloc_object(dev, 4096);
4640 if (obj == NULL) {
4641 DRM_ERROR("Failed to allocate seqno page\n");
4642 ret = -ENOMEM;
4643 goto err;
4644 }
4645 obj->agp_type = AGP_USER_CACHED_MEMORY;
4646
4647 ret = i915_gem_object_pin(obj, 4096, true);
4648 if (ret)
4649 goto err_unref;
4650
4651 dev_priv->seqno_gfx_addr = obj->gtt_offset;
4652 dev_priv->seqno_page = kmap(obj->pages[0]);
4653 if (dev_priv->seqno_page == NULL)
4654 goto err_unpin;
4655
4656 dev_priv->seqno_obj = obj;
4657 memset(dev_priv->seqno_page, 0, PAGE_SIZE);
4658
4659 return 0;
4660
4661err_unpin:
4662 i915_gem_object_unpin(obj);
4663err_unref:
4664 drm_gem_object_unreference(&obj->base);
4665err:
4666 return ret;
4667}
4668
4669
4670static void
4671i915_gem_cleanup_pipe_control(struct drm_device *dev)
4672{
4673 drm_i915_private_t *dev_priv = dev->dev_private;
4674 struct drm_i915_gem_object *obj;
4675
4676 obj = dev_priv->seqno_obj;
4677 kunmap(obj->pages[0]);
4678 i915_gem_object_unpin(obj);
4679 drm_gem_object_unreference(&obj->base);
4680 dev_priv->seqno_obj = NULL;
4681
4682 dev_priv->seqno_page = NULL;
4683}
4684
4685int 4628int
4686i915_gem_init_ringbuffer(struct drm_device *dev) 4629i915_gem_init_ringbuffer(struct drm_device *dev)
4687{ 4630{
4688 drm_i915_private_t *dev_priv = dev->dev_private; 4631 drm_i915_private_t *dev_priv = dev->dev_private;
4689 int ret; 4632 int ret;
4690 4633
4691 if (HAS_PIPE_CONTROL(dev)) {
4692 ret = i915_gem_init_pipe_control(dev);
4693 if (ret)
4694 return ret;
4695 }
4696
4697 ret = intel_init_render_ring_buffer(dev); 4634 ret = intel_init_render_ring_buffer(dev);
4698 if (ret) 4635 if (ret)
4699 goto cleanup_pipe_control; 4636 return ret;
4700 4637
4701 if (HAS_BSD(dev)) { 4638 if (HAS_BSD(dev)) {
4702 ret = intel_init_bsd_ring_buffer(dev); 4639 ret = intel_init_bsd_ring_buffer(dev);
@@ -4718,9 +4655,6 @@ cleanup_bsd_ring:
4718 intel_cleanup_ring_buffer(&dev_priv->bsd_ring); 4655 intel_cleanup_ring_buffer(&dev_priv->bsd_ring);
4719cleanup_render_ring: 4656cleanup_render_ring:
4720 intel_cleanup_ring_buffer(&dev_priv->render_ring); 4657 intel_cleanup_ring_buffer(&dev_priv->render_ring);
4721cleanup_pipe_control:
4722 if (HAS_PIPE_CONTROL(dev))
4723 i915_gem_cleanup_pipe_control(dev);
4724 return ret; 4658 return ret;
4725} 4659}
4726 4660
@@ -4732,8 +4666,6 @@ i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4732 intel_cleanup_ring_buffer(&dev_priv->render_ring); 4666 intel_cleanup_ring_buffer(&dev_priv->render_ring);
4733 intel_cleanup_ring_buffer(&dev_priv->bsd_ring); 4667 intel_cleanup_ring_buffer(&dev_priv->bsd_ring);
4734 intel_cleanup_ring_buffer(&dev_priv->blt_ring); 4668 intel_cleanup_ring_buffer(&dev_priv->blt_ring);
4735 if (HAS_PIPE_CONTROL(dev))
4736 i915_gem_cleanup_pipe_control(dev);
4737} 4669}
4738 4670
4739int 4671int