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authorRodrigo Vivi <rodrigo.vivi@gmail.com>2013-08-28 15:45:46 -0400
committerDaniel Vetter <daniel.vetter@ffwll.ch>2013-09-04 11:34:51 -0400
commit9435373ef8870e0a84b6fec0ad89b952bf3097fa (patch)
treeb3dc336376cce918843d011068107b2bd73a63c9 /drivers/gpu/drm/i915/i915_gem.c
parent3e33a8408117088c873ebc4b3ca0e1e440c0b697 (diff)
drm/i915: Report enabled slices on Haswell GT3
Batchbuffers constructed by userspace can conditionalise their URB allocations through the use of the MI_SET_PREDICATE command. This command can read the MI_PREDICATE_RESULT_2 register to see how many slices are enabled on GT3, and by virtue of the result, scale their memory allocations to fit enabled memory. Of course, this only works if the kernel sets the appropriate bit in the register first. v2: Better commit subject and message by Chris Wilson. Cc: Chris Wilson <chris@chris-wilson.co.uk> Credits-to: Yejun Guo <yejun.guo@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_gem.c')
-rw-r--r--drivers/gpu/drm/i915/i915_gem.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index d57368d5fc1d..2d4b72ab1229 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4331,6 +4331,11 @@ i915_gem_init_hw(struct drm_device *dev)
4331 if (dev_priv->ellc_size) 4331 if (dev_priv->ellc_size)
4332 I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf)); 4332 I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
4333 4333
4334 if (IS_HSW_GT3(dev))
4335 I915_WRITE(MI_PREDICATE_RESULT_2, LOWER_SLICE_ENABLED);
4336 else
4337 I915_WRITE(MI_PREDICATE_RESULT_2, LOWER_SLICE_DISABLED);
4338
4334 if (HAS_PCH_NOP(dev)) { 4339 if (HAS_PCH_NOP(dev)) {
4335 u32 temp = I915_READ(GEN7_MSG_CTL); 4340 u32 temp = I915_READ(GEN7_MSG_CTL);
4336 temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK); 4341 temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);