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authorDave Airlie <airlied@redhat.com>2013-07-18 21:56:14 -0400
committerDave Airlie <airlied@redhat.com>2013-07-18 22:12:21 -0400
commite13af9a8340685cfe25d0c9f708da7121e0f51dd (patch)
tree43511021ce5e60c03ee4c2c68c3dc9ffcdc3d399 /drivers/gpu/drm/i915/i915_drv.h
parentee114b97e67b2a572f94982567a21ac4ee17c133 (diff)
parent50b44a449ff1a19712ebc36ffccf9ac0a68033bf (diff)
Merge tag 'drm-intel-next-2013-07-12' of git://people.freedesktop.org/~danvet/drm-intel into drm-next
Highlights: - follow-up refactoring after the shared dpll rework that landed in 3.11 - oddball prep cleanups from Ben for ppgtt - encoder->get_config state tracking infrastructure from Jesse - used by the experimental fastboot support from Jesse (disabled by default) - make the error state file official and add it to our sysfs interface (Mika) - drm_mm prep changes from Ben, prepares to embedd the drm_mm_node (which will be used by the vma rework later on) - interrupt handling rework, follow up cleanups to the VECS enabling, hpd storm handling and fifo underrun reporting. - Big pile of smaller cleanups, code improvements and related stuff. * tag 'drm-intel-next-2013-07-12' of git://people.freedesktop.org/~danvet/drm-intel: (72 commits) drm/i915: clear DPLL reg when disabling i9xx dplls drm/i915: Fix up cpt pixel multiplier enable sequence drm/i915: clean up vlv ->pre_pll_enable and pll enable sequence drm/i915: move error state to own compilation unit drm/i915: Don't attempt to read an unitialized stack value drm/i915: Use for_each_pipe() when possible drm/i915: don't enable PM_VEBOX_CS_ERROR_INTERRUPT drm/i915: unify ring irq refcounts (again) drm/i915: kill dev_priv->rps.lock drm/i915: queue work outside spinlock in hsw_pm_irq_handler drm/i915: streamline hsw_pm_irq_handler drm/i915: irq handlers don't need interrupt-safe spinlocks drm/i915: kill lpt pch transcoder->crtc mapping code for fifo underruns drm/i915: improve GEN7_ERR_INT clearing for fifo underrun reporting drm/i915: improve SERR_INT clearing for fifo underrun reporting drm/i915: extract ibx_display_interrupt_update drm/i915: remove unused members from drm_i915_private drm/i915: don't frob mm.suspended when not using ums drm/i915: Fix VLV DP RBR/HDMI/DAC PLL LPF coefficients drm/i915: WARN if the bios reserved range is bigger than stolen size ... Conflicts: drivers/gpu/drm/i915/i915_gem.c
Diffstat (limited to 'drivers/gpu/drm/i915/i915_drv.h')
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h184
1 files changed, 117 insertions, 67 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a416645bcd23..cef35d3ab37b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -144,6 +144,7 @@ enum intel_dpll_id {
144 144
145struct intel_dpll_hw_state { 145struct intel_dpll_hw_state {
146 uint32_t dpll; 146 uint32_t dpll;
147 uint32_t dpll_md;
147 uint32_t fp0; 148 uint32_t fp0;
148 uint32_t fp1; 149 uint32_t fp1;
149}; 150};
@@ -156,6 +157,8 @@ struct intel_shared_dpll {
156 /* should match the index in the dev_priv->shared_dplls array */ 157 /* should match the index in the dev_priv->shared_dplls array */
157 enum intel_dpll_id id; 158 enum intel_dpll_id id;
158 struct intel_dpll_hw_state hw_state; 159 struct intel_dpll_hw_state hw_state;
160 void (*mode_set)(struct drm_i915_private *dev_priv,
161 struct intel_shared_dpll *pll);
159 void (*enable)(struct drm_i915_private *dev_priv, 162 void (*enable)(struct drm_i915_private *dev_priv,
160 struct intel_shared_dpll *pll); 163 struct intel_shared_dpll *pll);
161 void (*disable)(struct drm_i915_private *dev_priv, 164 void (*disable)(struct drm_i915_private *dev_priv,
@@ -364,6 +367,7 @@ struct drm_i915_display_funcs {
364 * fills out the pipe-config with the hw state. */ 367 * fills out the pipe-config with the hw state. */
365 bool (*get_pipe_config)(struct intel_crtc *, 368 bool (*get_pipe_config)(struct intel_crtc *,
366 struct intel_crtc_config *); 369 struct intel_crtc_config *);
370 void (*get_clock)(struct intel_crtc *, struct intel_crtc_config *);
367 int (*crtc_mode_set)(struct drm_crtc *crtc, 371 int (*crtc_mode_set)(struct drm_crtc *crtc,
368 int x, int y, 372 int x, int y,
369 struct drm_framebuffer *old_fb); 373 struct drm_framebuffer *old_fb);
@@ -462,8 +466,12 @@ struct i915_gtt {
462 void __iomem *gsm; 466 void __iomem *gsm;
463 467
464 bool do_idle_maps; 468 bool do_idle_maps;
465 dma_addr_t scratch_page_dma; 469 struct {
466 struct page *scratch_page; 470 dma_addr_t addr;
471 struct page *page;
472 } scratch;
473
474 int mtrr;
467 475
468 /* global gtt ops */ 476 /* global gtt ops */
469 int (*gtt_probe)(struct drm_device *dev, size_t *gtt_total, 477 int (*gtt_probe)(struct drm_device *dev, size_t *gtt_total,
@@ -477,21 +485,17 @@ struct i915_gtt {
477 struct sg_table *st, 485 struct sg_table *st,
478 unsigned int pg_start, 486 unsigned int pg_start,
479 enum i915_cache_level cache_level); 487 enum i915_cache_level cache_level);
480 gen6_gtt_pte_t (*pte_encode)(struct drm_device *dev, 488 gen6_gtt_pte_t (*pte_encode)(dma_addr_t addr,
481 dma_addr_t addr,
482 enum i915_cache_level level); 489 enum i915_cache_level level);
483}; 490};
484#define gtt_total_entries(gtt) ((gtt).total >> PAGE_SHIFT) 491#define gtt_total_entries(gtt) ((gtt).total >> PAGE_SHIFT)
485 492
486#define I915_PPGTT_PD_ENTRIES 512
487#define I915_PPGTT_PT_ENTRIES 1024
488struct i915_hw_ppgtt { 493struct i915_hw_ppgtt {
489 struct drm_device *dev; 494 struct drm_device *dev;
490 unsigned num_pd_entries; 495 unsigned num_pd_entries;
491 struct page **pt_pages; 496 struct page **pt_pages;
492 uint32_t pd_offset; 497 uint32_t pd_offset;
493 dma_addr_t *pt_dma_addr; 498 dma_addr_t *pt_dma_addr;
494 dma_addr_t scratch_page_dma_addr;
495 499
496 /* pte functions, mirroring the interface of the global gtt. */ 500 /* pte functions, mirroring the interface of the global gtt. */
497 void (*clear_range)(struct i915_hw_ppgtt *ppgtt, 501 void (*clear_range)(struct i915_hw_ppgtt *ppgtt,
@@ -501,8 +505,7 @@ struct i915_hw_ppgtt {
501 struct sg_table *st, 505 struct sg_table *st,
502 unsigned int pg_start, 506 unsigned int pg_start,
503 enum i915_cache_level cache_level); 507 enum i915_cache_level cache_level);
504 gen6_gtt_pte_t (*pte_encode)(struct drm_device *dev, 508 gen6_gtt_pte_t (*pte_encode)(dma_addr_t addr,
505 dma_addr_t addr,
506 enum i915_cache_level level); 509 enum i915_cache_level level);
507 int (*enable)(struct drm_device *dev); 510 int (*enable)(struct drm_device *dev);
508 void (*cleanup)(struct i915_hw_ppgtt *ppgtt); 511 void (*cleanup)(struct i915_hw_ppgtt *ppgtt);
@@ -528,17 +531,36 @@ struct i915_hw_context {
528 struct i915_ctx_hang_stats hang_stats; 531 struct i915_ctx_hang_stats hang_stats;
529}; 532};
530 533
531enum no_fbc_reason { 534struct i915_fbc {
532 FBC_NO_OUTPUT, /* no outputs enabled to compress */ 535 unsigned long size;
533 FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */ 536 unsigned int fb_id;
534 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */ 537 enum plane plane;
535 FBC_MODE_TOO_LARGE, /* mode too large for compression */ 538 int y;
536 FBC_BAD_PLANE, /* fbc not supported on plane */ 539
537 FBC_NOT_TILED, /* buffer not tiled */ 540 struct drm_mm_node *compressed_fb;
538 FBC_MULTIPLE_PIPES, /* more than one pipe active */ 541 struct drm_mm_node *compressed_llb;
539 FBC_MODULE_PARAM, 542
543 struct intel_fbc_work {
544 struct delayed_work work;
545 struct drm_crtc *crtc;
546 struct drm_framebuffer *fb;
547 int interval;
548 } *fbc_work;
549
550 enum {
551 FBC_NO_OUTPUT, /* no outputs enabled to compress */
552 FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */
553 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
554 FBC_MODE_TOO_LARGE, /* mode too large for compression */
555 FBC_BAD_PLANE, /* fbc not supported on plane */
556 FBC_NOT_TILED, /* buffer not tiled */
557 FBC_MULTIPLE_PIPES, /* more than one pipe active */
558 FBC_MODULE_PARAM,
559 FBC_CHIP_DEFAULT, /* disabled by default on this chip */
560 } no_fbc_reason;
540}; 561};
541 562
563
542enum intel_pch { 564enum intel_pch {
543 PCH_NONE = 0, /* No PCH present */ 565 PCH_NONE = 0, /* No PCH present */
544 PCH_IBX, /* Ibexpeak PCH */ 566 PCH_IBX, /* Ibexpeak PCH */
@@ -721,12 +743,12 @@ struct i915_suspend_saved_registers {
721}; 743};
722 744
723struct intel_gen6_power_mgmt { 745struct intel_gen6_power_mgmt {
746 /* work and pm_iir are protected by dev_priv->irq_lock */
724 struct work_struct work; 747 struct work_struct work;
725 struct delayed_work vlv_work;
726 u32 pm_iir; 748 u32 pm_iir;
727 /* lock - irqsave spinlock that protectects the work_struct and 749
728 * pm_iir. */ 750 /* On vlv we need to manually drop to Vmin with a delayed work. */
729 spinlock_t lock; 751 struct delayed_work vlv_work;
730 752
731 /* The below variables an all the rps hw state are protected by 753 /* The below variables an all the rps hw state are protected by
732 * dev->struct mutext. */ 754 * dev->struct mutext. */
@@ -792,6 +814,18 @@ struct i915_dri1_state {
792 uint32_t counter; 814 uint32_t counter;
793}; 815};
794 816
817struct i915_ums_state {
818 /**
819 * Flag if the X Server, and thus DRM, is not currently in
820 * control of the device.
821 *
822 * This is set between LeaveVT and EnterVT. It needs to be
823 * replaced with a semaphore. It also needs to be
824 * transitioned away from for kernel modesetting.
825 */
826 int mm_suspended;
827};
828
795struct intel_l3_parity { 829struct intel_l3_parity {
796 u32 *remap_info; 830 u32 *remap_info;
797 struct work_struct error_work; 831 struct work_struct error_work;
@@ -815,8 +849,6 @@ struct i915_gem_mm {
815 /** Usable portion of the GTT for GEM */ 849 /** Usable portion of the GTT for GEM */
816 unsigned long stolen_base; /* limited to low memory (32-bit) */ 850 unsigned long stolen_base; /* limited to low memory (32-bit) */
817 851
818 int gtt_mtrr;
819
820 /** PPGTT used for aliasing the PPGTT with the GTT */ 852 /** PPGTT used for aliasing the PPGTT with the GTT */
821 struct i915_hw_ppgtt *aliasing_ppgtt; 853 struct i915_hw_ppgtt *aliasing_ppgtt;
822 854
@@ -864,16 +896,6 @@ struct i915_gem_mm {
864 */ 896 */
865 bool interruptible; 897 bool interruptible;
866 898
867 /**
868 * Flag if the X Server, and thus DRM, is not currently in
869 * control of the device.
870 *
871 * This is set between LeaveVT and EnterVT. It needs to be
872 * replaced with a semaphore. It also needs to be
873 * transitioned away from for kernel modesetting.
874 */
875 int suspended;
876
877 /** Bit 6 swizzling required for X tiling */ 899 /** Bit 6 swizzling required for X tiling */
878 uint32_t bit_6_swizzle_x; 900 uint32_t bit_6_swizzle_x;
879 /** Bit 6 swizzling required for Y tiling */ 901 /** Bit 6 swizzling required for Y tiling */
@@ -896,6 +918,11 @@ struct drm_i915_error_state_buf {
896 loff_t pos; 918 loff_t pos;
897}; 919};
898 920
921struct i915_error_state_file_priv {
922 struct drm_device *dev;
923 struct drm_i915_error_state *error;
924};
925
899struct i915_gpu_error { 926struct i915_gpu_error {
900 /* For hangcheck timer */ 927 /* For hangcheck timer */
901#define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */ 928#define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
@@ -1058,12 +1085,7 @@ typedef struct drm_i915_private {
1058 1085
1059 int num_plane; 1086 int num_plane;
1060 1087
1061 unsigned long cfb_size; 1088 struct i915_fbc fbc;
1062 unsigned int cfb_fb;
1063 enum plane cfb_plane;
1064 int cfb_y;
1065 struct intel_fbc_work *fbc_work;
1066
1067 struct intel_opregion opregion; 1089 struct intel_opregion opregion;
1068 struct intel_vbt_data vbt; 1090 struct intel_vbt_data vbt;
1069 1091
@@ -1080,8 +1102,6 @@ typedef struct drm_i915_private {
1080 } backlight; 1102 } backlight;
1081 1103
1082 /* LVDS info */ 1104 /* LVDS info */
1083 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1084 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1085 bool no_aux_handshake; 1105 bool no_aux_handshake;
1086 1106
1087 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */ 1107 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
@@ -1141,11 +1161,6 @@ typedef struct drm_i915_private {
1141 /* Haswell power well */ 1161 /* Haswell power well */
1142 struct i915_power_well power_well; 1162 struct i915_power_well power_well;
1143 1163
1144 enum no_fbc_reason no_fbc_reason;
1145
1146 struct drm_mm_node *compressed_fb;
1147 struct drm_mm_node *compressed_llb;
1148
1149 struct i915_gpu_error gpu_error; 1164 struct i915_gpu_error gpu_error;
1150 1165
1151 struct drm_i915_gem_object *vlv_pctx; 1166 struct drm_i915_gem_object *vlv_pctx;
@@ -1172,6 +1187,8 @@ typedef struct drm_i915_private {
1172 /* Old dri1 support infrastructure, beware the dragons ya fools entering 1187 /* Old dri1 support infrastructure, beware the dragons ya fools entering
1173 * here! */ 1188 * here! */
1174 struct i915_dri1_state dri1; 1189 struct i915_dri1_state dri1;
1190 /* Old ums support infrastructure, same warning applies. */
1191 struct i915_ums_state ums;
1175} drm_i915_private_t; 1192} drm_i915_private_t;
1176 1193
1177/* Iterate over initialised rings */ 1194/* Iterate over initialised rings */
@@ -1186,7 +1203,7 @@ enum hdmi_force_audio {
1186 HDMI_AUDIO_ON, /* force turn on HDMI audio */ 1203 HDMI_AUDIO_ON, /* force turn on HDMI audio */
1187}; 1204};
1188 1205
1189#define I915_GTT_RESERVED ((struct drm_mm_node *)0x1) 1206#define I915_GTT_OFFSET_NONE ((u32)-1)
1190 1207
1191struct drm_i915_gem_object_ops { 1208struct drm_i915_gem_object_ops {
1192 /* Interface between the GEM object and its backing storage. 1209 /* Interface between the GEM object and its backing storage.
@@ -1212,7 +1229,7 @@ struct drm_i915_gem_object {
1212 const struct drm_i915_gem_object_ops *ops; 1229 const struct drm_i915_gem_object_ops *ops;
1213 1230
1214 /** Current space allocated to this object in the GTT, if any. */ 1231 /** Current space allocated to this object in the GTT, if any. */
1215 struct drm_mm_node *gtt_space; 1232 struct drm_mm_node gtt_space;
1216 /** Stolen memory for this object, instead of being backed by shmem. */ 1233 /** Stolen memory for this object, instead of being backed by shmem. */
1217 struct drm_mm_node *stolen; 1234 struct drm_mm_node *stolen;
1218 struct list_head global_list; 1235 struct list_head global_list;
@@ -1313,13 +1330,6 @@ struct drm_i915_gem_object {
1313 unsigned long exec_handle; 1330 unsigned long exec_handle;
1314 struct drm_i915_gem_exec_object2 *exec_entry; 1331 struct drm_i915_gem_exec_object2 *exec_entry;
1315 1332
1316 /**
1317 * Current offset of the object in GTT space.
1318 *
1319 * This is the same as gtt_space->start
1320 */
1321 uint32_t gtt_offset;
1322
1323 struct intel_ring_buffer *ring; 1333 struct intel_ring_buffer *ring;
1324 1334
1325 /** Breadcrumb of last rendering to the buffer. */ 1335 /** Breadcrumb of last rendering to the buffer. */
@@ -1345,6 +1355,37 @@ struct drm_i915_gem_object {
1345 1355
1346#define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base) 1356#define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
1347 1357
1358/* Offset of the first PTE pointing to this object */
1359static inline unsigned long
1360i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *o)
1361{
1362 return o->gtt_space.start;
1363}
1364
1365/* Whether or not this object is currently mapped by the translation tables */
1366static inline bool
1367i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *o)
1368{
1369 return drm_mm_node_allocated(&o->gtt_space);
1370}
1371
1372/* The size used in the translation tables may be larger than the actual size of
1373 * the object on GEN2/GEN3 because of the way tiling is handled. See
1374 * i915_gem_get_gtt_size() for more details.
1375 */
1376static inline unsigned long
1377i915_gem_obj_ggtt_size(struct drm_i915_gem_object *o)
1378{
1379 return o->gtt_space.size;
1380}
1381
1382static inline void
1383i915_gem_obj_ggtt_set_color(struct drm_i915_gem_object *o,
1384 enum i915_cache_level color)
1385{
1386 o->gtt_space.color = color;
1387}
1388
1348/** 1389/**
1349 * Request queue structure. 1390 * Request queue structure.
1350 * 1391 *
@@ -1542,6 +1583,7 @@ extern int i915_enable_ppgtt __read_mostly;
1542extern unsigned int i915_preliminary_hw_support __read_mostly; 1583extern unsigned int i915_preliminary_hw_support __read_mostly;
1543extern int i915_disable_power_well __read_mostly; 1584extern int i915_disable_power_well __read_mostly;
1544extern int i915_enable_ips __read_mostly; 1585extern int i915_enable_ips __read_mostly;
1586extern bool i915_fastboot __read_mostly;
1545 1587
1546extern int i915_suspend(struct drm_device *dev, pm_message_t state); 1588extern int i915_suspend(struct drm_device *dev, pm_message_t state);
1547extern int i915_resume(struct drm_device *dev); 1589extern int i915_resume(struct drm_device *dev);
@@ -1585,21 +1627,12 @@ extern void intel_hpd_init(struct drm_device *dev);
1585extern void intel_gt_init(struct drm_device *dev); 1627extern void intel_gt_init(struct drm_device *dev);
1586extern void intel_gt_reset(struct drm_device *dev); 1628extern void intel_gt_reset(struct drm_device *dev);
1587 1629
1588void i915_error_state_free(struct kref *error_ref);
1589
1590void 1630void
1591i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); 1631i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1592 1632
1593void 1633void
1594i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); 1634i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1595 1635
1596#ifdef CONFIG_DEBUG_FS
1597extern void i915_destroy_error_state(struct drm_device *dev);
1598#else
1599#define i915_destroy_error_state(x)
1600#endif
1601
1602
1603/* i915_gem.c */ 1636/* i915_gem.c */
1604int i915_gem_init_ioctl(struct drm_device *dev, void *data, 1637int i915_gem_init_ioctl(struct drm_device *dev, void *data,
1605 struct drm_file *file_priv); 1638 struct drm_file *file_priv);
@@ -1910,8 +1943,27 @@ void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1910/* i915_debugfs.c */ 1943/* i915_debugfs.c */
1911int i915_debugfs_init(struct drm_minor *minor); 1944int i915_debugfs_init(struct drm_minor *minor);
1912void i915_debugfs_cleanup(struct drm_minor *minor); 1945void i915_debugfs_cleanup(struct drm_minor *minor);
1946
1947/* i915_gpu_error.c */
1913__printf(2, 3) 1948__printf(2, 3)
1914void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...); 1949void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
1950int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
1951 const struct i915_error_state_file_priv *error);
1952int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
1953 size_t count, loff_t pos);
1954static inline void i915_error_state_buf_release(
1955 struct drm_i915_error_state_buf *eb)
1956{
1957 kfree(eb->buf);
1958}
1959void i915_capture_error_state(struct drm_device *dev);
1960void i915_error_state_get(struct drm_device *dev,
1961 struct i915_error_state_file_priv *error_priv);
1962void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
1963void i915_destroy_error_state(struct drm_device *dev);
1964
1965void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone);
1966const char *i915_cache_level_str(int type);
1915 1967
1916/* i915_suspend.c */ 1968/* i915_suspend.c */
1917extern int i915_save_state(struct drm_device *dev); 1969extern int i915_save_state(struct drm_device *dev);
@@ -1991,7 +2043,6 @@ int i915_reg_read_ioctl(struct drm_device *dev, void *data,
1991 struct drm_file *file); 2043 struct drm_file *file);
1992 2044
1993/* overlay */ 2045/* overlay */
1994#ifdef CONFIG_DEBUG_FS
1995extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev); 2046extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
1996extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e, 2047extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
1997 struct intel_overlay_error_state *error); 2048 struct intel_overlay_error_state *error);
@@ -2000,7 +2051,6 @@ extern struct intel_display_error_state *intel_display_capture_error_state(struc
2000extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e, 2051extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
2001 struct drm_device *dev, 2052 struct drm_device *dev,
2002 struct intel_display_error_state *error); 2053 struct intel_display_error_state *error);
2003#endif
2004 2054
2005/* On SNB platform, before reading ring registers forcewake bit 2055/* On SNB platform, before reading ring registers forcewake bit
2006 * must be set to prevent GT core from power down and stale values being 2056 * must be set to prevent GT core from power down and stale values being