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authorIngo Molnar <mingo@elte.hu>2008-12-08 09:07:49 -0500
committerIngo Molnar <mingo@elte.hu>2008-12-08 09:07:49 -0500
commitaa9c9b8c584a42a094202b7e0f63497e888f86a7 (patch)
tree3cb3b022054a7c1722657288518f495e0c4d9983 /drivers/gpu/drm/i915/i915_drv.h
parent87f7606591aea6a8a38ea4c8911b5eeeee2740b8 (diff)
parent218d11a8b071b23b76c484fd5f72a4fe3306801e (diff)
Merge branch 'linus' into x86/quirks
Diffstat (limited to 'drivers/gpu/drm/i915/i915_drv.h')
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h26
1 files changed, 21 insertions, 5 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ef1c0b8f8d07..adc972cc6bfc 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -47,6 +47,8 @@ enum pipe {
47 PIPE_B, 47 PIPE_B,
48}; 48};
49 49
50#define I915_NUM_PIPE 2
51
50/* Interface history: 52/* Interface history:
51 * 53 *
52 * 1.1: Original. 54 * 1.1: Original.
@@ -132,6 +134,7 @@ typedef struct drm_i915_private {
132 int user_irq_refcount; 134 int user_irq_refcount;
133 /** Cached value of IMR to avoid reads in updating the bitfield */ 135 /** Cached value of IMR to avoid reads in updating the bitfield */
134 u32 irq_mask_reg; 136 u32 irq_mask_reg;
137 u32 pipestat[2];
135 138
136 int tex_lru_log_granularity; 139 int tex_lru_log_granularity;
137 int allow_batchbuffer; 140 int allow_batchbuffer;
@@ -147,6 +150,7 @@ typedef struct drm_i915_private {
147 u32 saveDSPBCNTR; 150 u32 saveDSPBCNTR;
148 u32 saveDSPARB; 151 u32 saveDSPARB;
149 u32 saveRENDERSTANDBY; 152 u32 saveRENDERSTANDBY;
153 u32 saveHWS;
150 u32 savePIPEACONF; 154 u32 savePIPEACONF;
151 u32 savePIPEBCONF; 155 u32 savePIPEBCONF;
152 u32 savePIPEASRC; 156 u32 savePIPEASRC;
@@ -240,6 +244,10 @@ typedef struct drm_i915_private {
240 * List of objects currently involved in rendering from the 244 * List of objects currently involved in rendering from the
241 * ringbuffer. 245 * ringbuffer.
242 * 246 *
247 * Includes buffers having the contents of their GPU caches
248 * flushed, not necessarily primitives. last_rendering_seqno
249 * represents when the rendering involved will be completed.
250 *
243 * A reference is held on the buffer while on this list. 251 * A reference is held on the buffer while on this list.
244 */ 252 */
245 struct list_head active_list; 253 struct list_head active_list;
@@ -249,6 +257,8 @@ typedef struct drm_i915_private {
249 * still have a write_domain which needs to be flushed before 257 * still have a write_domain which needs to be flushed before
250 * unbinding. 258 * unbinding.
251 * 259 *
260 * last_rendering_seqno is 0 while an object is in this list.
261 *
252 * A reference is held on the buffer while on this list. 262 * A reference is held on the buffer while on this list.
253 */ 263 */
254 struct list_head flushing_list; 264 struct list_head flushing_list;
@@ -257,6 +267,8 @@ typedef struct drm_i915_private {
257 * LRU list of objects which are not in the ringbuffer and 267 * LRU list of objects which are not in the ringbuffer and
258 * are ready to unbind, but are still in the GTT. 268 * are ready to unbind, but are still in the GTT.
259 * 269 *
270 * last_rendering_seqno is 0 while an object is in this list.
271 *
260 * A reference is not held on the buffer while on this list, 272 * A reference is not held on the buffer while on this list,
261 * as merely being GTT-bound shouldn't prevent its being 273 * as merely being GTT-bound shouldn't prevent its being
262 * freed, and we'll pull it off the list in the free path. 274 * freed, and we'll pull it off the list in the free path.
@@ -367,8 +379,8 @@ struct drm_i915_gem_object {
367 uint32_t agp_type; 379 uint32_t agp_type;
368 380
369 /** 381 /**
370 * Flagging of which individual pages are valid in GEM_DOMAIN_CPU when 382 * If present, while GEM_DOMAIN_CPU is in the read domain this array
371 * GEM_DOMAIN_CPU is not in the object's read domain. 383 * flags which individual pages are valid.
372 */ 384 */
373 uint8_t *page_cpu_valid; 385 uint8_t *page_cpu_valid;
374}; 386};
@@ -390,9 +402,6 @@ struct drm_i915_gem_request {
390 /** Time at which this request was emitted, in jiffies. */ 402 /** Time at which this request was emitted, in jiffies. */
391 unsigned long emitted_jiffies; 403 unsigned long emitted_jiffies;
392 404
393 /** Cache domains that were flushed at the start of the request. */
394 uint32_t flush_domains;
395
396 struct list_head list; 405 struct list_head list;
397}; 406};
398 407
@@ -446,6 +455,13 @@ extern int i915_vblank_swap(struct drm_device *dev, void *data,
446 struct drm_file *file_priv); 455 struct drm_file *file_priv);
447extern void i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask); 456extern void i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask);
448 457
458void
459i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
460
461void
462i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
463
464
449/* i915_mem.c */ 465/* i915_mem.c */
450extern int i915_mem_alloc(struct drm_device *dev, void *data, 466extern int i915_mem_alloc(struct drm_device *dev, void *data,
451 struct drm_file *file_priv); 467 struct drm_file *file_priv);