drm/i915: Report enabled slices on Haswell GT3

Batchbuffers constructed by userspace can conditionalise their URB
allocations through the use of the MI_SET_PREDICATE command. This
command can read the MI_PREDICATE_RESULT_2 register to see how many
slices are enabled on GT3, and by virtue of the result, scale their
memory allocations to fit enabled memory.

Of course, this only works if the kernel sets the appropriate bit in the
register first.

v2: Better commit subject and message by Chris Wilson.

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Credits-to: Yejun Guo <yejun.guo@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

1 files changed, 2 insertions, 0 deletions

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2cf9dabbfe5d..e52648927475 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1603,6 +1603,8 @@ struct drm_i915_file_private {
                                  ((dev)->pci_device & 0xFF00) == 0x0C00)
 #define IS_ULT(dev)             (IS_HASWELL(dev) && \
                                  ((dev)->pci_device & 0xFF00) == 0x0A00)
+#define IS_HSW_GT3(dev)         (IS_HASWELL(dev) && \
+                                 ((dev)->pci_device & 0x00F0) == 0x0020)
 
 /*
  * The genX designation typically refers to the render engine, so render