diff options
author | Sourab Gupta <sourab.gupta@intel.com> | 2014-06-02 07:17:17 -0400 |
---|---|---|
committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2014-06-17 10:16:20 -0400 |
commit | 84c33a64b4e29757d04ba1b285b96ee160d5ff93 (patch) | |
tree | f9f4db1e9ab6eac283676bb0c9ae0c2311802ef9 /drivers/gpu/drm/i915/i915_drv.h | |
parent | f02a326e32edae40e7837824db6d1b3aae7c29b2 (diff) |
drm/i915: Replaced Blitter ring based flips with MMIO flips
This patch enables the framework for using MMIO based flip calls,
in contrast with the CS based flip calls which are being used currently.
MMIO based flip calls can be enabled on architectures where
Render and Blitter engines reside in different power wells. The
decision to use MMIO flips can be made based on workloads to give
100% residency for Media power well.
v2: The MMIO flips now use the interrupt driven mechanism for issuing the
flips when target seqno is reached. (Incorporating Ville's idea)
v3: Rebasing on latest code. Code restructuring after incorporating
Damien's comments
v4: Addressing Ville's review comments
-general cleanup
-updating only base addr instead of calling update_primary_plane
-extending patch for gen5+ platforms
v5: Addressed Ville's review comments
-Making mmio flip vs cs flip selection based on module parameter
-Adding check for DRIVER_MODESET feature in notify_ring before calling
notify mmio flip.
-Other changes mostly in function arguments
v6: -Having a seperate function to check condition for using mmio flips (Ville)
-propogating error code from i915_gem_check_olr (Ville)
v7: -Adding __must_check with i915_gem_check_olr (Chris)
-Renaming mmio_flip_data to mmio_flip (Chris)
-Rebasing on latest nightly
v8: -Rebasing on latest code
-squash 3rd patch in series(mmio setbase vs page flip race) with this patch
-Added new tiling mode update in intel_do_mmio_flip (Chris)
v9: -check for obj->last_write_seqno being 0 instead of obj->ring being NULL in
intel_postpone_flip, as this is a more restrictive condition (Chris)
v10: -Applied Chris's suggestions for squashing patches 2,3 into this patch.
These patches make the selection of CS vs MMIO flip at the page flip time, and
make the module parameter for using mmio flips as tristate, the states being
'force CS flips', 'force mmio flips', 'driver discretion'.
Changed the logic for driver discretion (Chris)
v11: Minor code cleanup(better readability, fixing whitespace errors, using
lockdep to check mutex locked status in postpone_flip, removal of __must_check
in function definition) (Chris)
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Sourab Gupta <sourab.gupta@intel.com>
Signed-off-by: Akash Goel <akash.goel@intel.com>
Tested-by: Chris Wilson <chris@chris-wilson.co.uk> # snb, ivb
[danvet: Fix up parameter alignement checkpatch spotted.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_drv.h')
-rw-r--r-- | drivers/gpu/drm/i915/i915_drv.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index c5b02159898b..9bfc242af87f 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h | |||
@@ -1370,6 +1370,9 @@ struct drm_i915_private { | |||
1370 | /* protects the irq masks */ | 1370 | /* protects the irq masks */ |
1371 | spinlock_t irq_lock; | 1371 | spinlock_t irq_lock; |
1372 | 1372 | ||
1373 | /* protects the mmio flip data */ | ||
1374 | spinlock_t mmio_flip_lock; | ||
1375 | |||
1373 | bool display_irqs_enabled; | 1376 | bool display_irqs_enabled; |
1374 | 1377 | ||
1375 | /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */ | 1378 | /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */ |
@@ -2043,6 +2046,7 @@ struct i915_params { | |||
2043 | bool reset; | 2046 | bool reset; |
2044 | bool disable_display; | 2047 | bool disable_display; |
2045 | bool disable_vtd_wa; | 2048 | bool disable_vtd_wa; |
2049 | int use_mmio_flip; | ||
2046 | }; | 2050 | }; |
2047 | extern struct i915_params i915 __read_mostly; | 2051 | extern struct i915_params i915 __read_mostly; |
2048 | 2052 | ||
@@ -2239,6 +2243,8 @@ bool i915_gem_retire_requests(struct drm_device *dev); | |||
2239 | void i915_gem_retire_requests_ring(struct intel_engine_cs *ring); | 2243 | void i915_gem_retire_requests_ring(struct intel_engine_cs *ring); |
2240 | int __must_check i915_gem_check_wedge(struct i915_gpu_error *error, | 2244 | int __must_check i915_gem_check_wedge(struct i915_gpu_error *error, |
2241 | bool interruptible); | 2245 | bool interruptible); |
2246 | int __must_check i915_gem_check_olr(struct intel_engine_cs *ring, u32 seqno); | ||
2247 | |||
2242 | static inline bool i915_reset_in_progress(struct i915_gpu_error *error) | 2248 | static inline bool i915_reset_in_progress(struct i915_gpu_error *error) |
2243 | { | 2249 | { |
2244 | return unlikely(atomic_read(&error->reset_counter) | 2250 | return unlikely(atomic_read(&error->reset_counter) |
@@ -2608,6 +2614,8 @@ int i915_reg_read_ioctl(struct drm_device *dev, void *data, | |||
2608 | int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data, | 2614 | int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data, |
2609 | struct drm_file *file); | 2615 | struct drm_file *file); |
2610 | 2616 | ||
2617 | void intel_notify_mmio_flip(struct intel_engine_cs *ring); | ||
2618 | |||
2611 | /* overlay */ | 2619 | /* overlay */ |
2612 | extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev); | 2620 | extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev); |
2613 | extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e, | 2621 | extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e, |