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authorDave Airlie <airlied@redhat.com>2012-04-12 05:27:01 -0400
committerDave Airlie <airlied@redhat.com>2012-04-12 05:27:01 -0400
commiteffbc4fd8e37e41d6f2bb6bcc611c14b4fbdcf9b (patch)
tree8bc2a6a2116f1031b0033bf1a8f9fbe92201c5c1 /drivers/gpu/drm/i915/i915_drv.c
parent6a7068b4ef17dfb9de3191321f1adc91fa1659ca (diff)
parentec34a01de31128e5c08e5f05c47f4a787f45a33c (diff)
Merge branch 'drm-intel-next' of git://people.freedesktop.org/~danvet/drm-intel into drm-core-next
Daniel Vetter wrote First pull request for 3.5-next, slightly large than usual because new things kept coming in since the last pull for 3.4. Highlights: - first batch of hw enablement for vlv (Jesse et al) and hsw (Eugeni). pci ids are not yet added, and there's still quite a few patches to merge (mostly modesetting). To make QA easier I've decided to merge this stuff in pieces. - loads of cleanups and prep patches spurred by the above. Especially vlv is a real frankenstein chip, but also hsw is stretching our driver's code design. Expect more to come in this area for 3.5. - more gmbus fixes, cleanups and improvements by Daniel Kurtz. Again, there are more patches needed (and some already queued up), but I wanted to split this a bit for better testing. - pwrite/pread rework and retuning. This series has been in the works for a few months already and a lot of i-g-t tests have been created for it. Now it's finally ready to be merged. Note that one patch in this series touches include/pagemap.h, that patch is acked-by akpm. - reduce mappable pressure and relocation throughput improvements from Chris. - mmap offset exhaustion mitigation by Chris Wilson. - a start at figuring out which codepaths in our messy dri1/ums+gem/kms driver we actually need to support by bailing out of unsupported case. The driver now refuses to load without kms on gen6+ and disallows a few ioctls that userspace never used in certain cases. More of this will definitely come. - More decoupling of global gtt and ppgtt. - Improved dual-link lvds detection by Takashi Iwai. - Shut up the compiler + plus fix the fallout (Ben) - Inverted panel brightness handling (mostly Acer manages to break things in this way). - Small fixlets and adjustements and some minor things to help debugging. Regression-wise QA reported quite a few issues on ivb, but all of them turned out to be hw stability issues which are already fixed in drm-intel-fixes (QA runs the nightly regression tests on -next alone, without -fixes automatically merged in). There's still one issue open on snb, it looks like occlusion query writes are not quite as cache coherent as we've expected. With some of the pwrite adjustements we can now reliably hit this. Kernel workaround for it is in the works." * 'drm-intel-next' of git://people.freedesktop.org/~danvet/drm-intel: (101 commits) drm/i915: VCS is not the last ring drm/i915: Add a dual link lvds quirk for MacBook Pro 8,2 drm/i915: make quirks more verbose drm/i915: dump the DMA fetch addr register on pre-gen6 drm/i915/sdvo: Include YRPB as an additional TV output type drm/i915: disallow gem init ioctl on ilk drm/i915: refuse to load on gen6+ without kms drm/i915: extract gt interrupt handler drm/i915: use render gen to switch ring irq functions drm/i915: rip out old HWSTAM missed irq WA for vlv drm/i915: open code gen6+ ring irqs drm/i915: ring irq cleanups drm/i915: add SFUSE_STRAP registers for digital port detection drm/i915: add WM_LINETIME registers drm/i915: add WRPLL clocks drm/i915: add LCPLL control registers drm/i915: add SSC offsets for SBI access drm/i915: add port clock selection support for HSW drm/i915: add S PLL control drm/i915: add PIXCLK_GATE register ... Conflicts: drivers/char/agp/intel-agp.h drivers/char/agp/intel-gtt.c drivers/gpu/drm/i915/i915_debugfs.c
Diffstat (limited to 'drivers/gpu/drm/i915/i915_drv.c')
-rw-r--r--drivers/gpu/drm/i915/i915_drv.c88
1 files changed, 86 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index dfa55e7478fb..c33b0a41a73d 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -84,6 +84,12 @@ MODULE_PARM_DESC(lvds_downclock,
84 "Use panel (LVDS/eDP) downclocking for power savings " 84 "Use panel (LVDS/eDP) downclocking for power savings "
85 "(default: false)"); 85 "(default: false)");
86 86
87int i915_lvds_channel_mode __read_mostly;
88module_param_named(lvds_channel_mode, i915_lvds_channel_mode, int, 0600);
89MODULE_PARM_DESC(lvds_channel_mode,
90 "Specify LVDS channel mode "
91 "(0=probe BIOS [default], 1=single-channel, 2=dual-channel)");
92
87int i915_panel_use_ssc __read_mostly = -1; 93int i915_panel_use_ssc __read_mostly = -1;
88module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600); 94module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600);
89MODULE_PARM_DESC(lvds_use_ssc, 95MODULE_PARM_DESC(lvds_use_ssc,
@@ -93,8 +99,8 @@ MODULE_PARM_DESC(lvds_use_ssc,
93int i915_vbt_sdvo_panel_type __read_mostly = -1; 99int i915_vbt_sdvo_panel_type __read_mostly = -1;
94module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600); 100module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600);
95MODULE_PARM_DESC(vbt_sdvo_panel_type, 101MODULE_PARM_DESC(vbt_sdvo_panel_type,
96 "Override selection of SDVO panel mode in the VBT " 102 "Override/Ignore selection of SDVO panel mode in the VBT "
97 "(default: auto)"); 103 "(-2=ignore, -1=auto [default], index in VBT BIOS table)");
98 104
99static bool i915_try_reset __read_mostly = true; 105static bool i915_try_reset __read_mostly = true;
100module_param_named(reset, i915_try_reset, bool, 0600); 106module_param_named(reset, i915_try_reset, bool, 0600);
@@ -209,6 +215,7 @@ static const struct intel_device_info intel_ironlake_d_info = {
209 .gen = 5, 215 .gen = 5,
210 .need_gfx_hws = 1, .has_hotplug = 1, 216 .need_gfx_hws = 1, .has_hotplug = 1,
211 .has_bsd_ring = 1, 217 .has_bsd_ring = 1,
218 .has_pch_split = 1,
212}; 219};
213 220
214static const struct intel_device_info intel_ironlake_m_info = { 221static const struct intel_device_info intel_ironlake_m_info = {
@@ -216,6 +223,7 @@ static const struct intel_device_info intel_ironlake_m_info = {
216 .need_gfx_hws = 1, .has_hotplug = 1, 223 .need_gfx_hws = 1, .has_hotplug = 1,
217 .has_fbc = 1, 224 .has_fbc = 1,
218 .has_bsd_ring = 1, 225 .has_bsd_ring = 1,
226 .has_pch_split = 1,
219}; 227};
220 228
221static const struct intel_device_info intel_sandybridge_d_info = { 229static const struct intel_device_info intel_sandybridge_d_info = {
@@ -224,6 +232,7 @@ static const struct intel_device_info intel_sandybridge_d_info = {
224 .has_bsd_ring = 1, 232 .has_bsd_ring = 1,
225 .has_blt_ring = 1, 233 .has_blt_ring = 1,
226 .has_llc = 1, 234 .has_llc = 1,
235 .has_pch_split = 1,
227}; 236};
228 237
229static const struct intel_device_info intel_sandybridge_m_info = { 238static const struct intel_device_info intel_sandybridge_m_info = {
@@ -233,6 +242,7 @@ static const struct intel_device_info intel_sandybridge_m_info = {
233 .has_bsd_ring = 1, 242 .has_bsd_ring = 1,
234 .has_blt_ring = 1, 243 .has_blt_ring = 1,
235 .has_llc = 1, 244 .has_llc = 1,
245 .has_pch_split = 1,
236}; 246};
237 247
238static const struct intel_device_info intel_ivybridge_d_info = { 248static const struct intel_device_info intel_ivybridge_d_info = {
@@ -241,6 +251,7 @@ static const struct intel_device_info intel_ivybridge_d_info = {
241 .has_bsd_ring = 1, 251 .has_bsd_ring = 1,
242 .has_blt_ring = 1, 252 .has_blt_ring = 1,
243 .has_llc = 1, 253 .has_llc = 1,
254 .has_pch_split = 1,
244}; 255};
245 256
246static const struct intel_device_info intel_ivybridge_m_info = { 257static const struct intel_device_info intel_ivybridge_m_info = {
@@ -250,6 +261,43 @@ static const struct intel_device_info intel_ivybridge_m_info = {
250 .has_bsd_ring = 1, 261 .has_bsd_ring = 1,
251 .has_blt_ring = 1, 262 .has_blt_ring = 1,
252 .has_llc = 1, 263 .has_llc = 1,
264 .has_pch_split = 1,
265};
266
267static const struct intel_device_info intel_valleyview_m_info = {
268 .gen = 7, .is_mobile = 1,
269 .need_gfx_hws = 1, .has_hotplug = 1,
270 .has_fbc = 0,
271 .has_bsd_ring = 1,
272 .has_blt_ring = 1,
273 .is_valleyview = 1,
274};
275
276static const struct intel_device_info intel_valleyview_d_info = {
277 .gen = 7,
278 .need_gfx_hws = 1, .has_hotplug = 1,
279 .has_fbc = 0,
280 .has_bsd_ring = 1,
281 .has_blt_ring = 1,
282 .is_valleyview = 1,
283};
284
285static const struct intel_device_info intel_haswell_d_info = {
286 .is_haswell = 1, .gen = 7,
287 .need_gfx_hws = 1, .has_hotplug = 1,
288 .has_bsd_ring = 1,
289 .has_blt_ring = 1,
290 .has_llc = 1,
291 .has_pch_split = 1,
292};
293
294static const struct intel_device_info intel_haswell_m_info = {
295 .is_haswell = 1, .gen = 7, .is_mobile = 1,
296 .need_gfx_hws = 1, .has_hotplug = 1,
297 .has_bsd_ring = 1,
298 .has_blt_ring = 1,
299 .has_llc = 1,
300 .has_pch_split = 1,
253}; 301};
254 302
255static const struct pci_device_id pciidlist[] = { /* aka */ 303static const struct pci_device_id pciidlist[] = { /* aka */
@@ -308,6 +356,7 @@ MODULE_DEVICE_TABLE(pci, pciidlist);
308#define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 356#define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
309#define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 357#define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
310#define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00 358#define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
359#define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
311 360
312void intel_detect_pch(struct drm_device *dev) 361void intel_detect_pch(struct drm_device *dev)
313{ 362{
@@ -336,6 +385,9 @@ void intel_detect_pch(struct drm_device *dev)
336 /* PantherPoint is CPT compatible */ 385 /* PantherPoint is CPT compatible */
337 dev_priv->pch_type = PCH_CPT; 386 dev_priv->pch_type = PCH_CPT;
338 DRM_DEBUG_KMS("Found PatherPoint PCH\n"); 387 DRM_DEBUG_KMS("Found PatherPoint PCH\n");
388 } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
389 dev_priv->pch_type = PCH_LPT;
390 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
339 } 391 }
340 } 392 }
341 pci_dev_put(pch); 393 pci_dev_put(pch);
@@ -446,6 +498,31 @@ int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
446 return ret; 498 return ret;
447} 499}
448 500
501void vlv_force_wake_get(struct drm_i915_private *dev_priv)
502{
503 int count;
504
505 count = 0;
506
507 /* Already awake? */
508 if ((I915_READ(0x130094) & 0xa1) == 0xa1)
509 return;
510
511 I915_WRITE_NOTRACE(FORCEWAKE_VLV, 0xffffffff);
512 POSTING_READ(FORCEWAKE_VLV);
513
514 count = 0;
515 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & 1) == 0)
516 udelay(10);
517}
518
519void vlv_force_wake_put(struct drm_i915_private *dev_priv)
520{
521 I915_WRITE_NOTRACE(FORCEWAKE_VLV, 0xffff0000);
522 /* FIXME: confirm VLV behavior with Punit folks */
523 POSTING_READ(FORCEWAKE_VLV);
524}
525
449static int i915_drm_freeze(struct drm_device *dev) 526static int i915_drm_freeze(struct drm_device *dev)
450{ 527{
451 struct drm_i915_private *dev_priv = dev->dev_private; 528 struct drm_i915_private *dev_priv = dev->dev_private;
@@ -993,6 +1070,13 @@ MODULE_AUTHOR(DRIVER_AUTHOR);
993MODULE_DESCRIPTION(DRIVER_DESC); 1070MODULE_DESCRIPTION(DRIVER_DESC);
994MODULE_LICENSE("GPL and additional rights"); 1071MODULE_LICENSE("GPL and additional rights");
995 1072
1073/* We give fast paths for the really cool registers */
1074#define NEEDS_FORCE_WAKE(dev_priv, reg) \
1075 (((dev_priv)->info->gen >= 6) && \
1076 ((reg) < 0x40000) && \
1077 ((reg) != FORCEWAKE)) && \
1078 (!IS_VALLEYVIEW((dev_priv)->dev))
1079
996#define __i915_read(x, y) \ 1080#define __i915_read(x, y) \
997u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \ 1081u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
998 u##x val = 0; \ 1082 u##x val = 0; \