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authorBen Widawsky <ben@bwidawsk.net>2012-11-04 12:21:27 -0500
committerDaniel Vetter <daniel.vetter@ffwll.ch>2012-11-11 17:51:42 -0500
commite76e9aebcdbfebae8f4cd147e3c0f800d36e97f3 (patch)
tree94272c5f3ee021931bfe43136d81076b10a26c77 /drivers/gpu/drm/i915/i915_dma.c
parentb3fcabb15bb83202fb5e4e5b296711b91c4942a3 (diff)
drm/i915: Stop using AGP layer for GEN6+
As a quick hack we make the old intel_gtt structure mutable so we can fool a bunch of the existing code which depends on elements in that data structure. We can/should try to remove this in a subsequent patch. This should preserve the old gtt init behavior which upon writing these patches seems incorrect. The next patch will fix these things. The one exception is VLV which doesn't have the preserved flush control write behavior. Since we want to do that for all GEN6+ stuff, we'll handle that in a later patch. Mainstream VLV support doesn't actually exist yet anyway. v2: Update the comment to remove the "voodoo" Check that the last pte written matches what we readback v3: actually kill cache_level_to_agp_type since most of the flags will disappear in an upcoming patch v4: v3 was actually not what we wanted (Daniel) Make the ggtt bind assertions better and stricter (Chris) Fix some uncaught errors at gtt init (Chris) Some other random stuff that Chris wanted v5: check for i==0 in gen6_ggtt_bind_object to shut up gcc (Ben) Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Reviewed-by [v4]: Chris Wilson <chris@chris-wilson.co.uk> [danvet: Make the cache_level -> agp_flags conversion for pre-gen6 a tad more robust by mapping everything != CACHE_NONE to the cached agp flag - we have a 1:1 uncached mapping, but different modes of cacheable (at least on later generations). Suggested by Chris Wilson.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_dma.c')
-rw-r--r--drivers/gpu/drm/i915/i915_dma.c16
1 files changed, 3 insertions, 13 deletions
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index ff06e3239ada..1eea5be43617 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1496,19 +1496,9 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
1496 goto free_priv; 1496 goto free_priv;
1497 } 1497 }
1498 1498
1499 ret = intel_gmch_probe(dev_priv->bridge_dev, dev->pdev, NULL); 1499 ret = i915_gem_gtt_init(dev);
1500 if (!ret) { 1500 if (ret)
1501 DRM_ERROR("failed to set up gmch\n");
1502 ret = -EIO;
1503 goto put_bridge; 1501 goto put_bridge;
1504 }
1505
1506 dev_priv->mm.gtt = intel_gtt_get();
1507 if (!dev_priv->mm.gtt) {
1508 DRM_ERROR("Failed to initialize GTT\n");
1509 ret = -ENODEV;
1510 goto put_gmch;
1511 }
1512 1502
1513 i915_kick_out_firmware_fb(dev_priv); 1503 i915_kick_out_firmware_fb(dev_priv);
1514 1504
@@ -1683,7 +1673,7 @@ out_mtrrfree:
1683out_rmmap: 1673out_rmmap:
1684 pci_iounmap(dev->pdev, dev_priv->regs); 1674 pci_iounmap(dev->pdev, dev_priv->regs);
1685put_gmch: 1675put_gmch:
1686 intel_gmch_remove(); 1676 i915_gem_gtt_fini(dev);
1687put_bridge: 1677put_bridge:
1688 pci_dev_put(dev_priv->bridge_dev); 1678 pci_dev_put(dev_priv->bridge_dev);
1689free_priv: 1679free_priv: