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authorAlan Cox <alan@linux.intel.com>2012-08-08 09:55:03 -0400
committerDave Airlie <airlied@redhat.com>2012-08-23 19:29:16 -0400
commit37e7b184da18a9cf42e19f3c3cb42cb30874ac22 (patch)
tree1e3136bc5a1f462ce0116343a3bc12cf50e12022 /drivers/gpu/drm/gma500
parent220801bdb53ceeac01d021ac459d112acc7deb0b (diff)
gma500/cdv: sync up and add the displayport code to the build
This is mostly just aligning bits of behaviour Signed-off-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/gma500')
-rw-r--r--drivers/gpu/drm/gma500/Makefile3
-rw-r--r--drivers/gpu/drm/gma500/cdv_intel_display.c6
-rw-r--r--drivers/gpu/drm/gma500/cdv_intel_dp.c480
-rw-r--r--drivers/gpu/drm/gma500/psb_intel_drv.h16
4 files changed, 260 insertions, 245 deletions
diff --git a/drivers/gpu/drm/gma500/Makefile b/drivers/gpu/drm/gma500/Makefile
index abfa2a93f0d0..56a0f2ac82c4 100644
--- a/drivers/gpu/drm/gma500/Makefile
+++ b/drivers/gpu/drm/gma500/Makefile
@@ -30,7 +30,8 @@ gma500_gfx-$(CONFIG_DRM_GMA3600) += cdv_device.o \
30 cdv_intel_crt.o \ 30 cdv_intel_crt.o \
31 cdv_intel_display.o \ 31 cdv_intel_display.o \
32 cdv_intel_hdmi.o \ 32 cdv_intel_hdmi.o \
33 cdv_intel_lvds.o 33 cdv_intel_lvds.o \
34 cdv_intel_dp.o
34 35
35gma500_gfx-$(CONFIG_DRM_GMA600) += oaktrail_device.o \ 36gma500_gfx-$(CONFIG_DRM_GMA600) += oaktrail_device.o \
36 oaktrail_crtc.o \ 37 oaktrail_crtc.o \
diff --git a/drivers/gpu/drm/gma500/cdv_intel_display.c b/drivers/gpu/drm/gma500/cdv_intel_display.c
index 2e0231e909ff..3f1106096ad3 100644
--- a/drivers/gpu/drm/gma500/cdv_intel_display.c
+++ b/drivers/gpu/drm/gma500/cdv_intel_display.c
@@ -171,7 +171,7 @@ static const struct cdv_intel_limit_t cdv_intel_limits[] = {
171#define wait_for(COND, MS) _wait_for(COND, MS, 1) 171#define wait_for(COND, MS) _wait_for(COND, MS, 1)
172 172
173 173
174static int cdv_sb_read(struct drm_device *dev, u32 reg, u32 *val) 174int cdv_sb_read(struct drm_device *dev, u32 reg, u32 *val)
175{ 175{
176 int ret; 176 int ret;
177 177
@@ -198,7 +198,7 @@ static int cdv_sb_read(struct drm_device *dev, u32 reg, u32 *val)
198 return 0; 198 return 0;
199} 199}
200 200
201static int cdv_sb_write(struct drm_device *dev, u32 reg, u32 val) 201int cdv_sb_write(struct drm_device *dev, u32 reg, u32 val)
202{ 202{
203 int ret; 203 int ret;
204 static bool dpio_debug = true; 204 static bool dpio_debug = true;
@@ -240,7 +240,7 @@ static int cdv_sb_write(struct drm_device *dev, u32 reg, u32 val)
240/* Reset the DPIO configuration register. The BIOS does this at every 240/* Reset the DPIO configuration register. The BIOS does this at every
241 * mode set. 241 * mode set.
242 */ 242 */
243static void cdv_sb_reset(struct drm_device *dev) 243void cdv_sb_reset(struct drm_device *dev)
244{ 244{
245 245
246 REG_WRITE(DPIO_CFG, 0); 246 REG_WRITE(DPIO_CFG, 0);
diff --git a/drivers/gpu/drm/gma500/cdv_intel_dp.c b/drivers/gpu/drm/gma500/cdv_intel_dp.c
index c6d545d42923..b29b6026b6ef 100644
--- a/drivers/gpu/drm/gma500/cdv_intel_dp.c
+++ b/drivers/gpu/drm/gma500/cdv_intel_dp.c
@@ -33,7 +33,6 @@
33#include "drm_crtc_helper.h" 33#include "drm_crtc_helper.h"
34#include "psb_drv.h" 34#include "psb_drv.h"
35#include "psb_intel_drv.h" 35#include "psb_intel_drv.h"
36#include "psb_drm.h"
37#include "psb_intel_reg.h" 36#include "psb_intel_reg.h"
38#include "drm_dp_helper.h" 37#include "drm_dp_helper.h"
39 38
@@ -45,7 +44,7 @@
45 44
46#define CDV_FAST_LINK_TRAIN 1 45#define CDV_FAST_LINK_TRAIN 1
47 46
48struct psb_intel_dp { 47struct cdv_intel_dp {
49 uint32_t output_reg; 48 uint32_t output_reg;
50 uint32_t DP; 49 uint32_t DP;
51 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]; 50 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE];
@@ -55,7 +54,7 @@ struct psb_intel_dp {
55 uint8_t link_bw; 54 uint8_t link_bw;
56 uint8_t lane_count; 55 uint8_t lane_count;
57 uint8_t dpcd[4]; 56 uint8_t dpcd[4];
58 struct psb_intel_output *output; 57 struct psb_intel_encoder *encoder;
59 struct i2c_adapter adapter; 58 struct i2c_adapter adapter;
60 struct i2c_algo_dp_aux_data algo; 59 struct i2c_algo_dp_aux_data algo;
61 uint8_t train_set[4]; 60 uint8_t train_set[4];
@@ -94,20 +93,20 @@ static uint32_t dp_vswing_premph_table[] = {
94 * If a CPU or PCH DP output is attached to an eDP panel, this function 93 * If a CPU or PCH DP output is attached to an eDP panel, this function
95 * will return true, and false otherwise. 94 * will return true, and false otherwise.
96 */ 95 */
97static bool is_edp(struct psb_intel_output *output) 96static bool is_edp(struct psb_intel_encoder *encoder)
98{ 97{
99 return output->type == INTEL_OUTPUT_EDP; 98 return encoder->type == INTEL_OUTPUT_EDP;
100} 99}
101 100
102 101
103static void psb_intel_dp_start_link_train(struct psb_intel_output *output); 102static void cdv_intel_dp_start_link_train(struct psb_intel_encoder *encoder);
104static void psb_intel_dp_complete_link_train(struct psb_intel_output *output); 103static void cdv_intel_dp_complete_link_train(struct psb_intel_encoder *encoder);
105static void psb_intel_dp_link_down(struct psb_intel_output *output); 104static void cdv_intel_dp_link_down(struct psb_intel_encoder *encoder);
106 105
107static int 106static int
108psb_intel_dp_max_lane_count(struct psb_intel_output *output) 107cdv_intel_dp_max_lane_count(struct psb_intel_encoder *encoder)
109{ 108{
110 struct psb_intel_dp *intel_dp = output->dev_priv; 109 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
111 int max_lane_count = 4; 110 int max_lane_count = 4;
112 111
113 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { 112 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
@@ -123,9 +122,9 @@ psb_intel_dp_max_lane_count(struct psb_intel_output *output)
123} 122}
124 123
125static int 124static int
126psb_intel_dp_max_link_bw(struct psb_intel_output *output) 125cdv_intel_dp_max_link_bw(struct psb_intel_encoder *encoder)
127{ 126{
128 struct psb_intel_dp *intel_dp = output->dev_priv; 127 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
129 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; 128 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
130 129
131 switch (max_link_bw) { 130 switch (max_link_bw) {
@@ -140,7 +139,7 @@ psb_intel_dp_max_link_bw(struct psb_intel_output *output)
140} 139}
141 140
142static int 141static int
143psb_intel_dp_link_clock(uint8_t link_bw) 142cdv_intel_dp_link_clock(uint8_t link_bw)
144{ 143{
145 if (link_bw == DP_LINK_BW_2_7) 144 if (link_bw == DP_LINK_BW_2_7)
146 return 270000; 145 return 270000;
@@ -149,28 +148,28 @@ psb_intel_dp_link_clock(uint8_t link_bw)
149} 148}
150 149
151static int 150static int
152psb_intel_dp_link_required(int pixel_clock, int bpp) 151cdv_intel_dp_link_required(int pixel_clock, int bpp)
153{ 152{
154 return (pixel_clock * bpp + 7) / 8; 153 return (pixel_clock * bpp + 7) / 8;
155} 154}
156 155
157static int 156static int
158psb_intel_dp_max_data_rate(int max_link_clock, int max_lanes) 157cdv_intel_dp_max_data_rate(int max_link_clock, int max_lanes)
159{ 158{
160 return (max_link_clock * max_lanes * 19) / 20; 159 return (max_link_clock * max_lanes * 19) / 20;
161} 160}
162 161
163static int 162static int
164psb_intel_dp_mode_valid(struct drm_connector *connector, 163cdv_intel_dp_mode_valid(struct drm_connector *connector,
165 struct drm_display_mode *mode) 164 struct drm_display_mode *mode)
166{ 165{
167 struct psb_intel_output *output = to_psb_intel_output(connector); 166 struct psb_intel_encoder *encoder = psb_intel_attached_encoder(connector);
168 struct drm_device *dev = connector->dev; 167 struct drm_device *dev = connector->dev;
169 struct drm_psb_private *dev_priv = dev->dev_private; 168 struct drm_psb_private *dev_priv = dev->dev_private;
170 int max_link_clock = psb_intel_dp_link_clock(psb_intel_dp_max_link_bw(output)); 169 int max_link_clock = cdv_intel_dp_link_clock(cdv_intel_dp_max_link_bw(encoder));
171 int max_lanes = psb_intel_dp_max_lane_count(output); 170 int max_lanes = cdv_intel_dp_max_lane_count(encoder);
172 171
173 if (is_edp(output) && dev_priv->panel_fixed_mode) { 172 if (is_edp(encoder) && dev_priv->panel_fixed_mode) {
174 if (mode->hdisplay > dev_priv->panel_fixed_mode->hdisplay) 173 if (mode->hdisplay > dev_priv->panel_fixed_mode->hdisplay)
175 return MODE_PANEL; 174 return MODE_PANEL;
176 175
@@ -180,9 +179,9 @@ psb_intel_dp_mode_valid(struct drm_connector *connector,
180 179
181 /* only refuse the mode on non eDP since we have seen some weird eDP panels 180 /* only refuse the mode on non eDP since we have seen some weird eDP panels
182 which are outside spec tolerances but somehow work by magic */ 181 which are outside spec tolerances but somehow work by magic */
183 if (!is_edp(output) && 182 if (!is_edp(encoder) &&
184 (psb_intel_dp_link_required(mode->clock, 24) 183 (cdv_intel_dp_link_required(mode->clock, 24)
185 > psb_intel_dp_max_data_rate(max_link_clock, max_lanes))) 184 > cdv_intel_dp_max_data_rate(max_link_clock, max_lanes)))
186 return MODE_CLOCK_HIGH; 185 return MODE_CLOCK_HIGH;
187 186
188 if (mode->clock < 10000) 187 if (mode->clock < 10000)
@@ -215,13 +214,13 @@ unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
215} 214}
216 215
217static int 216static int
218psb_intel_dp_aux_ch(struct psb_intel_output *output, 217cdv_intel_dp_aux_ch(struct psb_intel_encoder *encoder,
219 uint8_t *send, int send_bytes, 218 uint8_t *send, int send_bytes,
220 uint8_t *recv, int recv_size) 219 uint8_t *recv, int recv_size)
221{ 220{
222 struct psb_intel_dp *intel_dp = output->dev_priv; 221 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
223 uint32_t output_reg = intel_dp->output_reg; 222 uint32_t output_reg = intel_dp->output_reg;
224 struct drm_device *dev = output->base.dev; 223 struct drm_device *dev = encoder->base.dev;
225 uint32_t ch_ctl = output_reg + 0x10; 224 uint32_t ch_ctl = output_reg + 0x10;
226 uint32_t ch_data = ch_ctl + 4; 225 uint32_t ch_data = ch_ctl + 4;
227 int i; 226 int i;
@@ -315,7 +314,7 @@ psb_intel_dp_aux_ch(struct psb_intel_output *output,
315 314
316/* Write data to the aux channel in native mode */ 315/* Write data to the aux channel in native mode */
317static int 316static int
318psb_intel_dp_aux_native_write(struct psb_intel_output *output, 317cdv_intel_dp_aux_native_write(struct psb_intel_encoder *encoder,
319 uint16_t address, uint8_t *send, int send_bytes) 318 uint16_t address, uint8_t *send, int send_bytes)
320{ 319{
321 int ret; 320 int ret;
@@ -332,7 +331,7 @@ psb_intel_dp_aux_native_write(struct psb_intel_output *output,
332 memcpy(&msg[4], send, send_bytes); 331 memcpy(&msg[4], send, send_bytes);
333 msg_bytes = send_bytes + 4; 332 msg_bytes = send_bytes + 4;
334 for (;;) { 333 for (;;) {
335 ret = psb_intel_dp_aux_ch(output, msg, msg_bytes, &ack, 1); 334 ret = cdv_intel_dp_aux_ch(encoder, msg, msg_bytes, &ack, 1);
336 if (ret < 0) 335 if (ret < 0)
337 return ret; 336 return ret;
338 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) 337 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
@@ -347,15 +346,15 @@ psb_intel_dp_aux_native_write(struct psb_intel_output *output,
347 346
348/* Write a single byte to the aux channel in native mode */ 347/* Write a single byte to the aux channel in native mode */
349static int 348static int
350psb_intel_dp_aux_native_write_1(struct psb_intel_output *output, 349cdv_intel_dp_aux_native_write_1(struct psb_intel_encoder *encoder,
351 uint16_t address, uint8_t byte) 350 uint16_t address, uint8_t byte)
352{ 351{
353 return psb_intel_dp_aux_native_write(output, address, &byte, 1); 352 return cdv_intel_dp_aux_native_write(encoder, address, &byte, 1);
354} 353}
355 354
356/* read bytes from a native aux channel */ 355/* read bytes from a native aux channel */
357static int 356static int
358psb_intel_dp_aux_native_read(struct psb_intel_output *output, 357cdv_intel_dp_aux_native_read(struct psb_intel_encoder *encoder,
359 uint16_t address, uint8_t *recv, int recv_bytes) 358 uint16_t address, uint8_t *recv, int recv_bytes)
360{ 359{
361 uint8_t msg[4]; 360 uint8_t msg[4];
@@ -374,7 +373,7 @@ psb_intel_dp_aux_native_read(struct psb_intel_output *output,
374 reply_bytes = recv_bytes + 1; 373 reply_bytes = recv_bytes + 1;
375 374
376 for (;;) { 375 for (;;) {
377 ret = psb_intel_dp_aux_ch(output, msg, msg_bytes, 376 ret = cdv_intel_dp_aux_ch(encoder, msg, msg_bytes,
378 reply, reply_bytes); 377 reply, reply_bytes);
379 if (ret == 0) 378 if (ret == 0)
380 return -EPROTO; 379 return -EPROTO;
@@ -393,14 +392,14 @@ psb_intel_dp_aux_native_read(struct psb_intel_output *output,
393} 392}
394 393
395static int 394static int
396psb_intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, 395cdv_intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
397 uint8_t write_byte, uint8_t *read_byte) 396 uint8_t write_byte, uint8_t *read_byte)
398{ 397{
399 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data; 398 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
400 struct psb_intel_dp *intel_dp = container_of(adapter, 399 struct cdv_intel_dp *intel_dp = container_of(adapter,
401 struct psb_intel_dp, 400 struct cdv_intel_dp,
402 adapter); 401 adapter);
403 struct psb_intel_output *output = intel_dp->output; 402 struct psb_intel_encoder *encoder = intel_dp->encoder;
404 uint16_t address = algo_data->address; 403 uint16_t address = algo_data->address;
405 uint8_t msg[5]; 404 uint8_t msg[5];
406 uint8_t reply[2]; 405 uint8_t reply[2];
@@ -440,7 +439,7 @@ psb_intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
440 } 439 }
441 440
442 for (retry = 0; retry < 5; retry++) { 441 for (retry = 0; retry < 5; retry++) {
443 ret = psb_intel_dp_aux_ch(output, 442 ret = cdv_intel_dp_aux_ch(encoder,
444 msg, msg_bytes, 443 msg, msg_bytes,
445 reply, reply_bytes); 444 reply, reply_bytes);
446 if (ret < 0) { 445 if (ret < 0) {
@@ -490,13 +489,13 @@ psb_intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
490} 489}
491 490
492static int 491static int
493psb_intel_dp_i2c_init(struct psb_intel_output *output, const char *name) 492cdv_intel_dp_i2c_init(struct psb_intel_connector *connector, struct psb_intel_encoder *encoder, const char *name)
494{ 493{
495 struct psb_intel_dp *intel_dp = output->dev_priv; 494 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
496 DRM_DEBUG_KMS("i2c_init %s\n", name); 495 DRM_DEBUG_KMS("i2c_init %s\n", name);
497 intel_dp->algo.running = false; 496 intel_dp->algo.running = false;
498 intel_dp->algo.address = 0; 497 intel_dp->algo.address = 0;
499 intel_dp->algo.aux_ch = psb_intel_dp_i2c_aux_ch; 498 intel_dp->algo.aux_ch = cdv_intel_dp_i2c_aux_ch;
500 499
501 memset(&intel_dp->adapter, '\0', sizeof (intel_dp->adapter)); 500 memset(&intel_dp->adapter, '\0', sizeof (intel_dp->adapter));
502 intel_dp->adapter.owner = THIS_MODULE; 501 intel_dp->adapter.owner = THIS_MODULE;
@@ -504,32 +503,32 @@ psb_intel_dp_i2c_init(struct psb_intel_output *output, const char *name)
504 strncpy (intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1); 503 strncpy (intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
505 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0'; 504 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
506 intel_dp->adapter.algo_data = &intel_dp->algo; 505 intel_dp->adapter.algo_data = &intel_dp->algo;
507 intel_dp->adapter.dev.parent = &output->base.kdev; 506 intel_dp->adapter.dev.parent = &connector->base.kdev;
508 507
509 return i2c_dp_aux_add_bus(&intel_dp->adapter); 508 return i2c_dp_aux_add_bus(&intel_dp->adapter);
510} 509}
511 510
512static bool 511static bool
513psb_intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode, 512cdv_intel_dp_mode_fixup(struct drm_encoder *encoder, const struct drm_display_mode *mode,
514 struct drm_display_mode *adjusted_mode) 513 struct drm_display_mode *adjusted_mode)
515{ 514{
516 struct psb_intel_output *output = enc_to_psb_intel_output(encoder); 515 struct psb_intel_encoder *intel_encoder = to_psb_intel_encoder(encoder);
517 struct psb_intel_dp *intel_dp = output->dev_priv; 516 struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;
518 int lane_count, clock; 517 int lane_count, clock;
519 int max_lane_count = psb_intel_dp_max_lane_count(output); 518 int max_lane_count = cdv_intel_dp_max_lane_count(intel_encoder);
520 int max_clock = psb_intel_dp_max_link_bw(output) == DP_LINK_BW_2_7 ? 1 : 0; 519 int max_clock = cdv_intel_dp_max_link_bw(intel_encoder) == DP_LINK_BW_2_7 ? 1 : 0;
521 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 }; 520 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
522 521
523 522
524 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) { 523 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
525 for (clock = max_clock; clock >= 0; clock--) { 524 for (clock = max_clock; clock >= 0; clock--) {
526 int link_avail = psb_intel_dp_max_data_rate(psb_intel_dp_link_clock(bws[clock]), lane_count); 525 int link_avail = cdv_intel_dp_max_data_rate(cdv_intel_dp_link_clock(bws[clock]), lane_count);
527 526
528 if (psb_intel_dp_link_required(mode->clock, 24) 527 if (cdv_intel_dp_link_required(mode->clock, 24)
529 <= link_avail) { 528 <= link_avail) {
530 intel_dp->link_bw = bws[clock]; 529 intel_dp->link_bw = bws[clock];
531 intel_dp->lane_count = lane_count; 530 intel_dp->lane_count = lane_count;
532 adjusted_mode->clock = psb_intel_dp_link_clock(intel_dp->link_bw); 531 adjusted_mode->clock = cdv_intel_dp_link_clock(intel_dp->link_bw);
533 DRM_DEBUG_KMS("Display port link bw %02x lane " 532 DRM_DEBUG_KMS("Display port link bw %02x lane "
534 "count %d clock %d\n", 533 "count %d clock %d\n",
535 intel_dp->link_bw, intel_dp->lane_count, 534 intel_dp->link_bw, intel_dp->lane_count,
@@ -542,7 +541,7 @@ psb_intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mo
542 return false; 541 return false;
543} 542}
544 543
545struct psb_intel_dp_m_n { 544struct cdv_intel_dp_m_n {
546 uint32_t tu; 545 uint32_t tu;
547 uint32_t gmch_m; 546 uint32_t gmch_m;
548 uint32_t gmch_n; 547 uint32_t gmch_n;
@@ -567,11 +566,11 @@ psb_intel_reduce_ratio(uint32_t *num, uint32_t *den)
567} 566}
568 567
569static void 568static void
570psb_intel_dp_compute_m_n(int bpp, 569cdv_intel_dp_compute_m_n(int bpp,
571 int nlanes, 570 int nlanes,
572 int pixel_clock, 571 int pixel_clock,
573 int link_clock, 572 int link_clock,
574 struct psb_intel_dp_m_n *m_n) 573 struct cdv_intel_dp_m_n *m_n)
575{ 574{
576 m_n->tu = 64; 575 m_n->tu = 64;
577 m_n->gmch_m = (pixel_clock * bpp + 7) >> 3; 576 m_n->gmch_m = (pixel_clock * bpp + 7) >> 3;
@@ -583,7 +582,7 @@ psb_intel_dp_compute_m_n(int bpp,
583} 582}
584 583
585void 584void
586psb_intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, 585cdv_intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
587 struct drm_display_mode *adjusted_mode) 586 struct drm_display_mode *adjusted_mode)
588{ 587{
589 struct drm_device *dev = crtc->dev; 588 struct drm_device *dev = crtc->dev;
@@ -591,25 +590,25 @@ psb_intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
591 struct drm_encoder *encoder; 590 struct drm_encoder *encoder;
592 struct psb_intel_crtc *intel_crtc = to_psb_intel_crtc(crtc); 591 struct psb_intel_crtc *intel_crtc = to_psb_intel_crtc(crtc);
593 int lane_count = 4, bpp = 24; 592 int lane_count = 4, bpp = 24;
594 struct psb_intel_dp_m_n m_n; 593 struct cdv_intel_dp_m_n m_n;
595 int pipe = intel_crtc->pipe; 594 int pipe = intel_crtc->pipe;
596 595
597 /* 596 /*
598 * Find the lane count in the intel_encoder private 597 * Find the lane count in the intel_encoder private
599 */ 598 */
600 list_for_each_entry(encoder, &mode_config->encoder_list, head) { 599 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
601 struct psb_intel_output *intel_output; 600 struct psb_intel_encoder *intel_encoder;
602 struct psb_intel_dp *intel_dp; 601 struct cdv_intel_dp *intel_dp;
603 602
604 if (encoder->crtc != crtc) 603 if (encoder->crtc != crtc)
605 continue; 604 continue;
606 605
607 intel_output = enc_to_psb_intel_output(encoder); 606 intel_encoder = to_psb_intel_encoder(encoder);
608 intel_dp = intel_output->dev_priv; 607 intel_dp = intel_encoder->dev_priv;
609 if (intel_output->type == INTEL_OUTPUT_DISPLAYPORT) { 608 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
610 lane_count = intel_dp->lane_count; 609 lane_count = intel_dp->lane_count;
611 break; 610 break;
612 } else if (is_edp(intel_output)) { 611 } else if (is_edp(intel_encoder)) {
613 lane_count = intel_dp->lane_count; 612 lane_count = intel_dp->lane_count;
614 break; 613 break;
615 } 614 }
@@ -620,7 +619,7 @@ psb_intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
620 * the number of bytes_per_pixel post-LUT, which we always 619 * the number of bytes_per_pixel post-LUT, which we always
621 * set up for 8-bits of R/G/B, or 3 bytes total. 620 * set up for 8-bits of R/G/B, or 3 bytes total.
622 */ 621 */
623 psb_intel_dp_compute_m_n(bpp, lane_count, 622 cdv_intel_dp_compute_m_n(bpp, lane_count,
624 mode->clock, adjusted_mode->clock, &m_n); 623 mode->clock, adjusted_mode->clock, &m_n);
625 624
626 { 625 {
@@ -634,13 +633,13 @@ psb_intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
634} 633}
635 634
636static void 635static void
637psb_intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, 636cdv_intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
638 struct drm_display_mode *adjusted_mode) 637 struct drm_display_mode *adjusted_mode)
639{ 638{
640 struct psb_intel_output *intel_output = enc_to_psb_intel_output(encoder); 639 struct psb_intel_encoder *intel_encoder = to_psb_intel_encoder(encoder);
641 struct drm_crtc *crtc = encoder->crtc; 640 struct drm_crtc *crtc = encoder->crtc;
642 struct psb_intel_crtc *intel_crtc = to_psb_intel_crtc(crtc); 641 struct psb_intel_crtc *intel_crtc = to_psb_intel_crtc(crtc);
643 struct psb_intel_dp *intel_dp = intel_output->dev_priv; 642 struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;
644 643
645 644
646 intel_dp->DP = DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; 645 intel_dp->DP = DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
@@ -689,9 +688,9 @@ psb_intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode
689 688
690 689
691/* If the sink supports it, try to set the power state appropriately */ 690/* If the sink supports it, try to set the power state appropriately */
692static void psb_intel_dp_sink_dpms(struct psb_intel_output *output, int mode) 691static void cdv_intel_dp_sink_dpms(struct psb_intel_encoder *encoder, int mode)
693{ 692{
694 struct psb_intel_dp *intel_dp = output->dev_priv; 693 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
695 int ret, i; 694 int ret, i;
696 695
697 /* Should have a valid DPCD by this point */ 696 /* Should have a valid DPCD by this point */
@@ -699,7 +698,7 @@ static void psb_intel_dp_sink_dpms(struct psb_intel_output *output, int mode)
699 return; 698 return;
700 699
701 if (mode != DRM_MODE_DPMS_ON) { 700 if (mode != DRM_MODE_DPMS_ON) {
702 ret = psb_intel_dp_aux_native_write_1(output, DP_SET_POWER, 701 ret = cdv_intel_dp_aux_native_write_1(encoder, DP_SET_POWER,
703 DP_SET_POWER_D3); 702 DP_SET_POWER_D3);
704 if (ret != 1) 703 if (ret != 1)
705 DRM_DEBUG_DRIVER("failed to write sink power state\n"); 704 DRM_DEBUG_DRIVER("failed to write sink power state\n");
@@ -709,7 +708,7 @@ static void psb_intel_dp_sink_dpms(struct psb_intel_output *output, int mode)
709 * time to wake up. 708 * time to wake up.
710 */ 709 */
711 for (i = 0; i < 3; i++) { 710 for (i = 0; i < 3; i++) {
712 ret = psb_intel_dp_aux_native_write_1(output, 711 ret = cdv_intel_dp_aux_native_write_1(encoder,
713 DP_SET_POWER, 712 DP_SET_POWER,
714 DP_SET_POWER_D0); 713 DP_SET_POWER_D0);
715 if (ret == 1) 714 if (ret == 1)
@@ -719,42 +718,39 @@ static void psb_intel_dp_sink_dpms(struct psb_intel_output *output, int mode)
719 } 718 }
720} 719}
721 720
722static void psb_intel_dp_prepare(struct drm_encoder *encoder) 721static void cdv_intel_dp_prepare(struct drm_encoder *encoder)
723{ 722{
724 struct psb_intel_output *output = enc_to_psb_intel_output(encoder); 723 struct psb_intel_encoder *intel_encoder = to_psb_intel_encoder(encoder);
725 724
726 /* Wake up the sink first */ 725 /* Wake up the sink first */
727 psb_intel_dp_sink_dpms(output, DRM_MODE_DPMS_ON); 726 cdv_intel_dp_sink_dpms(intel_encoder, DRM_MODE_DPMS_ON);
728 727 cdv_intel_dp_link_down(intel_encoder);
729 psb_intel_dp_link_down(output);
730} 728}
731 729
732static void psb_intel_dp_commit(struct drm_encoder *encoder) 730static void cdv_intel_dp_commit(struct drm_encoder *encoder)
733{ 731{
734 struct psb_intel_output *output = enc_to_psb_intel_output(encoder); 732 struct psb_intel_encoder *intel_encoder = to_psb_intel_encoder(encoder);
735
736 psb_intel_dp_start_link_train(output);
737
738 psb_intel_dp_complete_link_train(output);
739 733
734 cdv_intel_dp_start_link_train(intel_encoder);
735 cdv_intel_dp_complete_link_train(intel_encoder);
740} 736}
741 737
742static void 738static void
743psb_intel_dp_dpms(struct drm_encoder *encoder, int mode) 739cdv_intel_dp_dpms(struct drm_encoder *encoder, int mode)
744{ 740{
745 struct psb_intel_output *intel_output = enc_to_psb_intel_output(encoder); 741 struct psb_intel_encoder *intel_encoder = to_psb_intel_encoder(encoder);
746 struct psb_intel_dp *intel_dp = intel_output->dev_priv; 742 struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;
747 struct drm_device *dev = encoder->dev; 743 struct drm_device *dev = encoder->dev;
748 uint32_t dp_reg = REG_READ(intel_dp->output_reg); 744 uint32_t dp_reg = REG_READ(intel_dp->output_reg);
749 745
750 if (mode != DRM_MODE_DPMS_ON) { 746 if (mode != DRM_MODE_DPMS_ON) {
751 psb_intel_dp_sink_dpms(intel_output, mode); 747 cdv_intel_dp_sink_dpms(intel_encoder, mode);
752 psb_intel_dp_link_down(intel_output); 748 cdv_intel_dp_link_down(intel_encoder);
753 } else { 749 } else {
754 psb_intel_dp_sink_dpms(intel_output, mode); 750 cdv_intel_dp_sink_dpms(intel_encoder, mode);
755 if (!(dp_reg & DP_PORT_EN)) { 751 if (!(dp_reg & DP_PORT_EN)) {
756 psb_intel_dp_start_link_train(intel_output); 752 cdv_intel_dp_start_link_train(intel_encoder);
757 psb_intel_dp_complete_link_train(intel_output); 753 cdv_intel_dp_complete_link_train(intel_encoder);
758 } 754 }
759 } 755 }
760} 756}
@@ -764,7 +760,7 @@ psb_intel_dp_dpms(struct drm_encoder *encoder, int mode)
764 * cases where the sink may still be asleep. 760 * cases where the sink may still be asleep.
765 */ 761 */
766static bool 762static bool
767psb_intel_dp_aux_native_read_retry(struct psb_intel_output *output, uint16_t address, 763cdv_intel_dp_aux_native_read_retry(struct psb_intel_encoder *encoder, uint16_t address,
768 uint8_t *recv, int recv_bytes) 764 uint8_t *recv, int recv_bytes)
769{ 765{
770 int ret, i; 766 int ret, i;
@@ -774,7 +770,7 @@ psb_intel_dp_aux_native_read_retry(struct psb_intel_output *output, uint16_t add
774 * but we're also supposed to retry 3 times per the spec. 770 * but we're also supposed to retry 3 times per the spec.
775 */ 771 */
776 for (i = 0; i < 3; i++) { 772 for (i = 0; i < 3; i++) {
777 ret = psb_intel_dp_aux_native_read(output, address, recv, 773 ret = cdv_intel_dp_aux_native_read(encoder, address, recv,
778 recv_bytes); 774 recv_bytes);
779 if (ret == recv_bytes) 775 if (ret == recv_bytes)
780 return true; 776 return true;
@@ -789,44 +785,44 @@ psb_intel_dp_aux_native_read_retry(struct psb_intel_output *output, uint16_t add
789 * link status information 785 * link status information
790 */ 786 */
791static bool 787static bool
792psb_intel_dp_get_link_status(struct psb_intel_output *output) 788cdv_intel_dp_get_link_status(struct psb_intel_encoder *encoder)
793{ 789{
794 struct psb_intel_dp *intel_dp = output->dev_priv; 790 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
795 return psb_intel_dp_aux_native_read_retry(output, 791 return cdv_intel_dp_aux_native_read_retry(encoder,
796 DP_LANE0_1_STATUS, 792 DP_LANE0_1_STATUS,
797 intel_dp->link_status, 793 intel_dp->link_status,
798 DP_LINK_STATUS_SIZE); 794 DP_LINK_STATUS_SIZE);
799} 795}
800 796
801static uint8_t 797static uint8_t
802psb_intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE], 798cdv_intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
803 int r) 799 int r)
804{ 800{
805 return link_status[r - DP_LANE0_1_STATUS]; 801 return link_status[r - DP_LANE0_1_STATUS];
806} 802}
807 803
808static uint8_t 804static uint8_t
809psb_intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE], 805cdv_intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE],
810 int lane) 806 int lane)
811{ 807{
812 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); 808 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
813 int s = ((lane & 1) ? 809 int s = ((lane & 1) ?
814 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT : 810 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
815 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT); 811 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
816 uint8_t l = psb_intel_dp_link_status(link_status, i); 812 uint8_t l = cdv_intel_dp_link_status(link_status, i);
817 813
818 return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT; 814 return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
819} 815}
820 816
821static uint8_t 817static uint8_t
822psb_intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE], 818cdv_intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE],
823 int lane) 819 int lane)
824{ 820{
825 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); 821 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
826 int s = ((lane & 1) ? 822 int s = ((lane & 1) ?
827 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT : 823 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
828 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT); 824 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
829 uint8_t l = psb_intel_dp_link_status(link_status, i); 825 uint8_t l = cdv_intel_dp_link_status(link_status, i);
830 826
831 return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT; 827 return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
832} 828}
@@ -847,7 +843,7 @@ static char *link_train_names[] = {
847#define CDV_DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_1200 843#define CDV_DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_1200
848/* 844/*
849static uint8_t 845static uint8_t
850psb_intel_dp_pre_emphasis_max(uint8_t voltage_swing) 846cdv_intel_dp_pre_emphasis_max(uint8_t voltage_swing)
851{ 847{
852 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 848 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
853 case DP_TRAIN_VOLTAGE_SWING_400: 849 case DP_TRAIN_VOLTAGE_SWING_400:
@@ -863,16 +859,16 @@ psb_intel_dp_pre_emphasis_max(uint8_t voltage_swing)
863} 859}
864*/ 860*/
865static void 861static void
866psb_intel_get_adjust_train(struct psb_intel_output *output) 862cdv_intel_get_adjust_train(struct psb_intel_encoder *encoder)
867{ 863{
868 struct psb_intel_dp *intel_dp = output->dev_priv; 864 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
869 uint8_t v = 0; 865 uint8_t v = 0;
870 uint8_t p = 0; 866 uint8_t p = 0;
871 int lane; 867 int lane;
872 868
873 for (lane = 0; lane < intel_dp->lane_count; lane++) { 869 for (lane = 0; lane < intel_dp->lane_count; lane++) {
874 uint8_t this_v = psb_intel_get_adjust_request_voltage(intel_dp->link_status, lane); 870 uint8_t this_v = cdv_intel_get_adjust_request_voltage(intel_dp->link_status, lane);
875 uint8_t this_p = psb_intel_get_adjust_request_pre_emphasis(intel_dp->link_status, lane); 871 uint8_t this_p = cdv_intel_get_adjust_request_pre_emphasis(intel_dp->link_status, lane);
876 872
877 if (this_v > v) 873 if (this_v > v)
878 v = this_v; 874 v = this_v;
@@ -892,25 +888,25 @@ psb_intel_get_adjust_train(struct psb_intel_output *output)
892 888
893 889
894static uint8_t 890static uint8_t
895psb_intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE], 891cdv_intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
896 int lane) 892 int lane)
897{ 893{
898 int i = DP_LANE0_1_STATUS + (lane >> 1); 894 int i = DP_LANE0_1_STATUS + (lane >> 1);
899 int s = (lane & 1) * 4; 895 int s = (lane & 1) * 4;
900 uint8_t l = psb_intel_dp_link_status(link_status, i); 896 uint8_t l = cdv_intel_dp_link_status(link_status, i);
901 897
902 return (l >> s) & 0xf; 898 return (l >> s) & 0xf;
903} 899}
904 900
905/* Check for clock recovery is done on all channels */ 901/* Check for clock recovery is done on all channels */
906static bool 902static bool
907psb_intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count) 903cdv_intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
908{ 904{
909 int lane; 905 int lane;
910 uint8_t lane_status; 906 uint8_t lane_status;
911 907
912 for (lane = 0; lane < lane_count; lane++) { 908 for (lane = 0; lane < lane_count; lane++) {
913 lane_status = psb_intel_get_lane_status(link_status, lane); 909 lane_status = cdv_intel_get_lane_status(link_status, lane);
914 if ((lane_status & DP_LANE_CR_DONE) == 0) 910 if ((lane_status & DP_LANE_CR_DONE) == 0)
915 return false; 911 return false;
916 } 912 }
@@ -922,19 +918,19 @@ psb_intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_c
922 DP_LANE_CHANNEL_EQ_DONE|\ 918 DP_LANE_CHANNEL_EQ_DONE|\
923 DP_LANE_SYMBOL_LOCKED) 919 DP_LANE_SYMBOL_LOCKED)
924static bool 920static bool
925psb_intel_channel_eq_ok(struct psb_intel_output *output) 921cdv_intel_channel_eq_ok(struct psb_intel_encoder *encoder)
926{ 922{
927 struct psb_intel_dp *intel_dp = output->dev_priv; 923 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
928 uint8_t lane_align; 924 uint8_t lane_align;
929 uint8_t lane_status; 925 uint8_t lane_status;
930 int lane; 926 int lane;
931 927
932 lane_align = psb_intel_dp_link_status(intel_dp->link_status, 928 lane_align = cdv_intel_dp_link_status(intel_dp->link_status,
933 DP_LANE_ALIGN_STATUS_UPDATED); 929 DP_LANE_ALIGN_STATUS_UPDATED);
934 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0) 930 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
935 return false; 931 return false;
936 for (lane = 0; lane < intel_dp->lane_count; lane++) { 932 for (lane = 0; lane < intel_dp->lane_count; lane++) {
937 lane_status = psb_intel_get_lane_status(intel_dp->link_status, lane); 933 lane_status = cdv_intel_get_lane_status(intel_dp->link_status, lane);
938 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS) 934 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
939 return false; 935 return false;
940 } 936 }
@@ -942,19 +938,19 @@ psb_intel_channel_eq_ok(struct psb_intel_output *output)
942} 938}
943 939
944static bool 940static bool
945psb_intel_dp_set_link_train(struct psb_intel_output *output, 941cdv_intel_dp_set_link_train(struct psb_intel_encoder *encoder,
946 uint32_t dp_reg_value, 942 uint32_t dp_reg_value,
947 uint8_t dp_train_pat) 943 uint8_t dp_train_pat)
948{ 944{
949 945
950 struct drm_device *dev = output->base.dev; 946 struct drm_device *dev = encoder->base.dev;
951 int ret; 947 int ret;
952 struct psb_intel_dp *intel_dp = output->dev_priv; 948 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
953 949
954 REG_WRITE(intel_dp->output_reg, dp_reg_value); 950 REG_WRITE(intel_dp->output_reg, dp_reg_value);
955 REG_READ(intel_dp->output_reg); 951 REG_READ(intel_dp->output_reg);
956 952
957 ret = psb_intel_dp_aux_native_write_1(output, 953 ret = cdv_intel_dp_aux_native_write_1(encoder,
958 DP_TRAINING_PATTERN_SET, 954 DP_TRAINING_PATTERN_SET,
959 dp_train_pat); 955 dp_train_pat);
960 956
@@ -969,14 +965,14 @@ psb_intel_dp_set_link_train(struct psb_intel_output *output,
969 965
970 966
971static bool 967static bool
972psb_intel_dplink_set_level(struct psb_intel_output *output, 968cdv_intel_dplink_set_level(struct psb_intel_encoder *encoder,
973 uint8_t dp_train_pat) 969 uint8_t dp_train_pat)
974{ 970{
975 971
976 int ret; 972 int ret;
977 struct psb_intel_dp *intel_dp = output->dev_priv; 973 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
978 974
979 ret = psb_intel_dp_aux_native_write(output, 975 ret = cdv_intel_dp_aux_native_write(encoder,
980 DP_TRAINING_LANE0_SET, 976 DP_TRAINING_LANE0_SET,
981 intel_dp->train_set, 977 intel_dp->train_set,
982 intel_dp->lane_count); 978 intel_dp->lane_count);
@@ -990,10 +986,10 @@ psb_intel_dplink_set_level(struct psb_intel_output *output,
990} 986}
991 987
992static void 988static void
993psb_intel_dp_set_vswing_premph(struct psb_intel_output *output, uint8_t signal_level) 989cdv_intel_dp_set_vswing_premph(struct psb_intel_encoder *encoder, uint8_t signal_level)
994{ 990{
995 struct drm_device *dev = output->base.dev; 991 struct drm_device *dev = encoder->base.dev;
996 struct psb_intel_dp *intel_dp = output->dev_priv; 992 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
997 struct ddi_regoff *ddi_reg; 993 struct ddi_regoff *ddi_reg;
998 int vswing, premph, index; 994 int vswing, premph, index;
999 995
@@ -1013,53 +1009,53 @@ psb_intel_dp_set_vswing_premph(struct psb_intel_output *output, uint8_t signal_l
1013#endif 1009#endif
1014 DRM_DEBUG_KMS("Test2\n"); 1010 DRM_DEBUG_KMS("Test2\n");
1015 //return ; 1011 //return ;
1016 psb_sb_reset(dev); 1012 cdv_sb_reset(dev);
1017 /* ;Swing voltage programming 1013 /* ;Swing voltage programming
1018 ;gfx_dpio_set_reg(0xc058, 0x0505313A) */ 1014 ;gfx_dpio_set_reg(0xc058, 0x0505313A) */
1019 psb_sb_write(dev, ddi_reg->VSwing5, 0x0505313A); 1015 cdv_sb_write(dev, ddi_reg->VSwing5, 0x0505313A);
1020 1016
1021 /* ;gfx_dpio_set_reg(0x8154, 0x43406055) */ 1017 /* ;gfx_dpio_set_reg(0x8154, 0x43406055) */
1022 psb_sb_write(dev, ddi_reg->VSwing1, 0x43406055); 1018 cdv_sb_write(dev, ddi_reg->VSwing1, 0x43406055);
1023 1019
1024 /* ;gfx_dpio_set_reg(0x8148, 0x55338954) 1020 /* ;gfx_dpio_set_reg(0x8148, 0x55338954)
1025 * The VSwing_PreEmph table is also considered based on the vswing/premp 1021 * The VSwing_PreEmph table is also considered based on the vswing/premp
1026 */ 1022 */
1027 index = (vswing + premph) * 2; 1023 index = (vswing + premph) * 2;
1028 if (premph == 1 && vswing == 1) { 1024 if (premph == 1 && vswing == 1) {
1029 psb_sb_write(dev, ddi_reg->VSwing2, 0x055738954); 1025 cdv_sb_write(dev, ddi_reg->VSwing2, 0x055738954);
1030 } else 1026 } else
1031 psb_sb_write(dev, ddi_reg->VSwing2, dp_vswing_premph_table[index]); 1027 cdv_sb_write(dev, ddi_reg->VSwing2, dp_vswing_premph_table[index]);
1032 1028
1033 /* ;gfx_dpio_set_reg(0x814c, 0x40802040) */ 1029 /* ;gfx_dpio_set_reg(0x814c, 0x40802040) */
1034 if ((vswing + premph) == DP_TRAIN_VOLTAGE_SWING_1200) 1030 if ((vswing + premph) == DP_TRAIN_VOLTAGE_SWING_1200)
1035 psb_sb_write(dev, ddi_reg->VSwing3, 0x70802040); 1031 cdv_sb_write(dev, ddi_reg->VSwing3, 0x70802040);
1036 else 1032 else
1037 psb_sb_write(dev, ddi_reg->VSwing3, 0x40802040); 1033 cdv_sb_write(dev, ddi_reg->VSwing3, 0x40802040);
1038 1034
1039 /* ;gfx_dpio_set_reg(0x8150, 0x2b405555) */ 1035 /* ;gfx_dpio_set_reg(0x8150, 0x2b405555) */
1040 //psb_sb_write(dev, ddi_reg->VSwing4, 0x2b405555); 1036 /* cdv_sb_write(dev, ddi_reg->VSwing4, 0x2b405555); */
1041 1037
1042 /* ;gfx_dpio_set_reg(0x8154, 0xc3406055) */ 1038 /* ;gfx_dpio_set_reg(0x8154, 0xc3406055) */
1043 psb_sb_write(dev, ddi_reg->VSwing1, 0xc3406055); 1039 cdv_sb_write(dev, ddi_reg->VSwing1, 0xc3406055);
1044 1040
1045 /* ;Pre emphasis programming 1041 /* ;Pre emphasis programming
1046 * ;gfx_dpio_set_reg(0xc02c, 0x1f030040) 1042 * ;gfx_dpio_set_reg(0xc02c, 0x1f030040)
1047 */ 1043 */
1048 psb_sb_write(dev, ddi_reg->PreEmph1, 0x1f030040); 1044 cdv_sb_write(dev, ddi_reg->PreEmph1, 0x1f030040);
1049 1045
1050 /* ;gfx_dpio_set_reg(0x8124, 0x00004000) */ 1046 /* ;gfx_dpio_set_reg(0x8124, 0x00004000) */
1051 index = 2 * premph + 1; 1047 index = 2 * premph + 1;
1052 psb_sb_write(dev, ddi_reg->PreEmph2, dp_vswing_premph_table[index]); 1048 cdv_sb_write(dev, ddi_reg->PreEmph2, dp_vswing_premph_table[index]);
1053 return; 1049 return;
1054} 1050}
1055 1051
1056 1052
1057/* Enable corresponding port and start training pattern 1 */ 1053/* Enable corresponding port and start training pattern 1 */
1058static void 1054static void
1059psb_intel_dp_start_link_train(struct psb_intel_output *output) 1055cdv_intel_dp_start_link_train(struct psb_intel_encoder *encoder)
1060{ 1056{
1061 struct drm_device *dev = output->base.dev; 1057 struct drm_device *dev = encoder->base.dev;
1062 struct psb_intel_dp *intel_dp = output->dev_priv; 1058 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
1063 int i; 1059 int i;
1064 uint8_t voltage; 1060 uint8_t voltage;
1065 bool clock_recovery = false; 1061 bool clock_recovery = false;
@@ -1068,10 +1064,10 @@ psb_intel_dp_start_link_train(struct psb_intel_output *output)
1068 uint32_t DP = intel_dp->DP; 1064 uint32_t DP = intel_dp->DP;
1069 1065
1070 DP |= DP_PORT_EN; 1066 DP |= DP_PORT_EN;
1071 DP &= ~DP_LINK_TRAIN_MASK; 1067 DP &= ~DP_LINK_TRAIN_MASK;
1072 1068
1073 reg = DP; 1069 reg = DP;
1074 reg |= DP_LINK_TRAIN_PAT_1; 1070 reg |= DP_LINK_TRAIN_PAT_1;
1075 /* Enable output, wait for it to become active */ 1071 /* Enable output, wait for it to become active */
1076 REG_WRITE(intel_dp->output_reg, reg); 1072 REG_WRITE(intel_dp->output_reg, reg);
1077 REG_READ(intel_dp->output_reg); 1073 REG_READ(intel_dp->output_reg);
@@ -1079,7 +1075,7 @@ psb_intel_dp_start_link_train(struct psb_intel_output *output)
1079 1075
1080 DRM_DEBUG_KMS("Link config\n"); 1076 DRM_DEBUG_KMS("Link config\n");
1081 /* Write the link configuration data */ 1077 /* Write the link configuration data */
1082 psb_intel_dp_aux_native_write(output, DP_LINK_BW_SET, 1078 cdv_intel_dp_aux_native_write(encoder, DP_LINK_BW_SET,
1083 intel_dp->link_configuration, 1079 intel_dp->link_configuration,
1084 2); 1080 2);
1085 1081
@@ -1095,19 +1091,19 @@ psb_intel_dp_start_link_train(struct psb_intel_output *output)
1095 for (;;) { 1091 for (;;) {
1096 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */ 1092 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1097 1093
1098 if (!psb_intel_dp_set_link_train(output, reg, DP_TRAINING_PATTERN_1)) { 1094 if (!cdv_intel_dp_set_link_train(encoder, reg, DP_TRAINING_PATTERN_1)) {
1099 DRM_DEBUG_KMS("Failure in aux-transfer setting pattern 1\n"); 1095 DRM_DEBUG_KMS("Failure in aux-transfer setting pattern 1\n");
1100 } 1096 }
1101 psb_intel_dp_set_vswing_premph(output, intel_dp->train_set[0]); 1097 cdv_intel_dp_set_vswing_premph(encoder, intel_dp->train_set[0]);
1102 /* Set training pattern 1 */ 1098 /* Set training pattern 1 */
1103 1099
1104 psb_intel_dplink_set_level(output, DP_TRAINING_PATTERN_1); 1100 cdv_intel_dplink_set_level(encoder, DP_TRAINING_PATTERN_1);
1105 1101
1106 udelay(200); 1102 udelay(200);
1107 if (!psb_intel_dp_get_link_status(output)) 1103 if (!cdv_intel_dp_get_link_status(encoder))
1108 break; 1104 break;
1109 1105
1110 if (psb_intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) { 1106 if (cdv_intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {
1111 DRM_DEBUG_KMS("PT1 train is done\n"); 1107 DRM_DEBUG_KMS("PT1 train is done\n");
1112 clock_recovery = true; 1108 clock_recovery = true;
1113 break; 1109 break;
@@ -1130,7 +1126,7 @@ psb_intel_dp_start_link_train(struct psb_intel_output *output)
1130 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; 1126 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1131 1127
1132 /* Compute new intel_dp->train_set as requested by target */ 1128 /* Compute new intel_dp->train_set as requested by target */
1133 psb_intel_get_adjust_train(output); 1129 cdv_intel_get_adjust_train(encoder);
1134 1130
1135 } 1131 }
1136 1132
@@ -1142,10 +1138,10 @@ psb_intel_dp_start_link_train(struct psb_intel_output *output)
1142} 1138}
1143 1139
1144static void 1140static void
1145psb_intel_dp_complete_link_train(struct psb_intel_output *output) 1141cdv_intel_dp_complete_link_train(struct psb_intel_encoder *encoder)
1146{ 1142{
1147 struct drm_device *dev = output->base.dev; 1143 struct drm_device *dev = encoder->base.dev;
1148 struct psb_intel_dp *intel_dp = output->dev_priv; 1144 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
1149 bool channel_eq = false; 1145 bool channel_eq = false;
1150 int tries, cr_tries; 1146 int tries, cr_tries;
1151 u32 reg; 1147 u32 reg;
@@ -1161,7 +1157,7 @@ psb_intel_dp_complete_link_train(struct psb_intel_output *output)
1161 1157
1162 for (;;) { 1158 for (;;) {
1163 /* channel eq pattern */ 1159 /* channel eq pattern */
1164 if (!psb_intel_dp_set_link_train(output, reg, 1160 if (!cdv_intel_dp_set_link_train(encoder, reg,
1165 DP_TRAINING_PATTERN_2)) { 1161 DP_TRAINING_PATTERN_2)) {
1166 DRM_DEBUG_KMS("Failure in aux-transfer setting pattern 2\n"); 1162 DRM_DEBUG_KMS("Failure in aux-transfer setting pattern 2\n");
1167 } 1163 }
@@ -1169,26 +1165,26 @@ psb_intel_dp_complete_link_train(struct psb_intel_output *output)
1169 1165
1170 if (cr_tries > 5) { 1166 if (cr_tries > 5) {
1171 DRM_ERROR("failed to train DP, aborting\n"); 1167 DRM_ERROR("failed to train DP, aborting\n");
1172 psb_intel_dp_link_down(output); 1168 cdv_intel_dp_link_down(encoder);
1173 break; 1169 break;
1174 } 1170 }
1175 1171
1176 psb_intel_dp_set_vswing_premph(output, intel_dp->train_set[0]); 1172 cdv_intel_dp_set_vswing_premph(encoder, intel_dp->train_set[0]);
1177 1173
1178 psb_intel_dplink_set_level(output, DP_TRAINING_PATTERN_2); 1174 cdv_intel_dplink_set_level(encoder, DP_TRAINING_PATTERN_2);
1179 1175
1180 udelay(1000); 1176 udelay(1000);
1181 if (!psb_intel_dp_get_link_status(output)) 1177 if (!cdv_intel_dp_get_link_status(encoder))
1182 break; 1178 break;
1183 1179
1184 /* Make sure clock is still ok */ 1180 /* Make sure clock is still ok */
1185 if (!psb_intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) { 1181 if (!cdv_intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {
1186 psb_intel_dp_start_link_train(output); 1182 cdv_intel_dp_start_link_train(encoder);
1187 cr_tries++; 1183 cr_tries++;
1188 continue; 1184 continue;
1189 } 1185 }
1190 1186
1191 if (psb_intel_channel_eq_ok(output)) { 1187 if (cdv_intel_channel_eq_ok(encoder)) {
1192 DRM_DEBUG_KMS("PT2 train is done\n"); 1188 DRM_DEBUG_KMS("PT2 train is done\n");
1193 channel_eq = true; 1189 channel_eq = true;
1194 break; 1190 break;
@@ -1196,15 +1192,15 @@ psb_intel_dp_complete_link_train(struct psb_intel_output *output)
1196 1192
1197 /* Try 5 times, then try clock recovery if that fails */ 1193 /* Try 5 times, then try clock recovery if that fails */
1198 if (tries > 5) { 1194 if (tries > 5) {
1199 psb_intel_dp_link_down(output); 1195 cdv_intel_dp_link_down(encoder);
1200 psb_intel_dp_start_link_train(output); 1196 cdv_intel_dp_start_link_train(encoder);
1201 tries = 0; 1197 tries = 0;
1202 cr_tries++; 1198 cr_tries++;
1203 continue; 1199 continue;
1204 } 1200 }
1205 1201
1206 /* Compute new intel_dp->train_set as requested by target */ 1202 /* Compute new intel_dp->train_set as requested by target */
1207 psb_intel_get_adjust_train(output); 1203 cdv_intel_get_adjust_train(encoder);
1208 ++tries; 1204 ++tries;
1209 1205
1210 } 1206 }
@@ -1213,15 +1209,15 @@ psb_intel_dp_complete_link_train(struct psb_intel_output *output)
1213 1209
1214 REG_WRITE(intel_dp->output_reg, reg); 1210 REG_WRITE(intel_dp->output_reg, reg);
1215 REG_READ(intel_dp->output_reg); 1211 REG_READ(intel_dp->output_reg);
1216 psb_intel_dp_aux_native_write_1(output, 1212 cdv_intel_dp_aux_native_write_1(encoder,
1217 DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE); 1213 DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
1218} 1214}
1219 1215
1220static void 1216static void
1221psb_intel_dp_link_down(struct psb_intel_output *output) 1217cdv_intel_dp_link_down(struct psb_intel_encoder *encoder)
1222{ 1218{
1223 struct drm_device *dev = output->base.dev; 1219 struct drm_device *dev = encoder->base.dev;
1224 struct psb_intel_dp *intel_dp = output->dev_priv; 1220 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
1225 uint32_t DP = intel_dp->DP; 1221 uint32_t DP = intel_dp->DP;
1226 1222
1227 if ((REG_READ(intel_dp->output_reg) & DP_PORT_EN) == 0) 1223 if ((REG_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)
@@ -1243,13 +1239,13 @@ psb_intel_dp_link_down(struct psb_intel_output *output)
1243} 1239}
1244 1240
1245static enum drm_connector_status 1241static enum drm_connector_status
1246cdv_dp_detect(struct psb_intel_output *output) 1242cdv_dp_detect(struct psb_intel_encoder *encoder)
1247{ 1243{
1248 struct psb_intel_dp *intel_dp = output->dev_priv; 1244 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
1249 enum drm_connector_status status; 1245 enum drm_connector_status status;
1250 1246
1251 status = connector_status_disconnected; 1247 status = connector_status_disconnected;
1252 if (psb_intel_dp_aux_native_read(output, 0x000, intel_dp->dpcd, 1248 if (cdv_intel_dp_aux_native_read(encoder, 0x000, intel_dp->dpcd,
1253 sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd)) 1249 sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd))
1254 { 1250 {
1255 if (intel_dp->dpcd[DP_DPCD_REV] != 0) 1251 if (intel_dp->dpcd[DP_DPCD_REV] != 0)
@@ -1269,16 +1265,16 @@ cdv_dp_detect(struct psb_intel_output *output)
1269 * \return false if DP port is disconnected. 1265 * \return false if DP port is disconnected.
1270 */ 1266 */
1271static enum drm_connector_status 1267static enum drm_connector_status
1272psb_intel_dp_detect(struct drm_connector *connector, bool force) 1268cdv_intel_dp_detect(struct drm_connector *connector, bool force)
1273{ 1269{
1274 struct psb_intel_output *output = to_psb_intel_output(connector); 1270 struct psb_intel_encoder *encoder = psb_intel_attached_encoder(connector);
1275 struct psb_intel_dp *intel_dp = output->dev_priv; 1271 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
1276 enum drm_connector_status status; 1272 enum drm_connector_status status;
1277 struct edid *edid = NULL; 1273 struct edid *edid = NULL;
1278 1274
1279 intel_dp->has_audio = false; 1275 intel_dp->has_audio = false;
1280 1276
1281 status = cdv_dp_detect(output); 1277 status = cdv_dp_detect(encoder);
1282 if (status != connector_status_connected) 1278 if (status != connector_status_connected)
1283 return status; 1279 return status;
1284 1280
@@ -1296,20 +1292,18 @@ psb_intel_dp_detect(struct drm_connector *connector, bool force)
1296 return connector_status_connected; 1292 return connector_status_connected;
1297} 1293}
1298 1294
1299static int psb_intel_dp_get_modes(struct drm_connector *connector) 1295static int cdv_intel_dp_get_modes(struct drm_connector *connector)
1300{ 1296{
1301 struct psb_intel_output *intel_output = to_psb_intel_output(connector); 1297 struct psb_intel_encoder *intel_encoder = psb_intel_attached_encoder(connector);
1302 struct psb_intel_dp *intel_dp = intel_output->dev_priv; 1298 struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;
1303 struct edid *edid = NULL; 1299 struct edid *edid = NULL;
1304 int ret = 0; 1300 int ret = 0;
1305 1301
1306 1302
1307 edid = drm_get_edid(&intel_output->base, 1303 edid = drm_get_edid(connector, &intel_dp->adapter);
1308 &intel_dp->adapter);
1309 if (edid) { 1304 if (edid) {
1310 drm_mode_connector_update_edid_property(&intel_output-> 1305 drm_mode_connector_update_edid_property(connector, edid);
1311 base, edid); 1306 ret = drm_add_edid_modes(connector, edid);
1312 ret = drm_add_edid_modes(&intel_output->base, edid);
1313 kfree(edid); 1307 kfree(edid);
1314 } 1308 }
1315 1309
@@ -1317,10 +1311,10 @@ static int psb_intel_dp_get_modes(struct drm_connector *connector)
1317} 1311}
1318 1312
1319static bool 1313static bool
1320psb_intel_dp_detect_audio(struct drm_connector *connector) 1314cdv_intel_dp_detect_audio(struct drm_connector *connector)
1321{ 1315{
1322 struct psb_intel_output *output = to_psb_intel_output(connector); 1316 struct psb_intel_encoder *encoder = psb_intel_attached_encoder(connector);
1323 struct psb_intel_dp *intel_dp = output->dev_priv; 1317 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
1324 struct edid *edid; 1318 struct edid *edid;
1325 bool has_audio = false; 1319 bool has_audio = false;
1326 1320
@@ -1336,13 +1330,13 @@ psb_intel_dp_detect_audio(struct drm_connector *connector)
1336} 1330}
1337 1331
1338static int 1332static int
1339psb_intel_dp_set_property(struct drm_connector *connector, 1333cdv_intel_dp_set_property(struct drm_connector *connector,
1340 struct drm_property *property, 1334 struct drm_property *property,
1341 uint64_t val) 1335 uint64_t val)
1342{ 1336{
1343 struct drm_psb_private *dev_priv = connector->dev->dev_private; 1337 struct drm_psb_private *dev_priv = connector->dev->dev_private;
1344 struct psb_intel_output *output = to_psb_intel_output(connector); 1338 struct psb_intel_encoder *encoder = psb_intel_attached_encoder(connector);
1345 struct psb_intel_dp *intel_dp = output->dev_priv; 1339 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
1346 int ret; 1340 int ret;
1347 1341
1348 ret = drm_connector_property_set_value(connector, property, val); 1342 ret = drm_connector_property_set_value(connector, property, val);
@@ -1359,7 +1353,7 @@ psb_intel_dp_set_property(struct drm_connector *connector,
1359 intel_dp->force_audio = i; 1353 intel_dp->force_audio = i;
1360 1354
1361 if (i == 0) 1355 if (i == 0)
1362 has_audio = psb_intel_dp_detect_audio(connector); 1356 has_audio = cdv_intel_dp_detect_audio(connector);
1363 else 1357 else
1364 has_audio = i > 0; 1358 has_audio = i > 0;
1365 1359
@@ -1381,8 +1375,8 @@ psb_intel_dp_set_property(struct drm_connector *connector,
1381 return -EINVAL; 1375 return -EINVAL;
1382 1376
1383done: 1377done:
1384 if (output->enc.crtc) { 1378 if (encoder->base.crtc) {
1385 struct drm_crtc *crtc = output->enc.crtc; 1379 struct drm_crtc *crtc = encoder->base.crtc;
1386 drm_crtc_helper_set_mode(crtc, &crtc->mode, 1380 drm_crtc_helper_set_mode(crtc, &crtc->mode,
1387 crtc->x, crtc->y, 1381 crtc->x, crtc->y,
1388 crtc->fb); 1382 crtc->fb);
@@ -1392,10 +1386,11 @@ done:
1392} 1386}
1393 1387
1394static void 1388static void
1395psb_intel_dp_destroy (struct drm_connector *connector) 1389cdv_intel_dp_destroy (struct drm_connector *connector)
1396{ 1390{
1397 struct psb_intel_output *output = to_psb_intel_output(connector); 1391 struct psb_intel_encoder *psb_intel_encoder =
1398 struct psb_intel_dp *intel_dp = output->dev_priv; 1392 psb_intel_attached_encoder(connector);
1393 struct cdv_intel_dp *intel_dp = psb_intel_encoder->dev_priv;
1399 1394
1400 i2c_del_adapter(&intel_dp->adapter); 1395 i2c_del_adapter(&intel_dp->adapter);
1401 drm_sysfs_connector_remove(connector); 1396 drm_sysfs_connector_remove(connector);
@@ -1403,86 +1398,83 @@ psb_intel_dp_destroy (struct drm_connector *connector)
1403 kfree(connector); 1398 kfree(connector);
1404} 1399}
1405 1400
1406static void psb_intel_dp_encoder_destroy(struct drm_encoder *encoder) 1401static void cdv_intel_dp_encoder_destroy(struct drm_encoder *encoder)
1407{ 1402{
1408 drm_encoder_cleanup(encoder); 1403 drm_encoder_cleanup(encoder);
1409} 1404}
1410 1405
1411static const struct drm_encoder_helper_funcs psb_intel_dp_helper_funcs = { 1406static const struct drm_encoder_helper_funcs cdv_intel_dp_helper_funcs = {
1412 .dpms = psb_intel_dp_dpms, 1407 .dpms = cdv_intel_dp_dpms,
1413 .mode_fixup = psb_intel_dp_mode_fixup, 1408 .mode_fixup = cdv_intel_dp_mode_fixup,
1414 .prepare = psb_intel_dp_prepare, 1409 .prepare = cdv_intel_dp_prepare,
1415 .mode_set = psb_intel_dp_mode_set, 1410 .mode_set = cdv_intel_dp_mode_set,
1416 .commit = psb_intel_dp_commit, 1411 .commit = cdv_intel_dp_commit,
1417}; 1412};
1418 1413
1419static const struct drm_connector_funcs psb_intel_dp_connector_funcs = { 1414static const struct drm_connector_funcs cdv_intel_dp_connector_funcs = {
1420 .dpms = drm_helper_connector_dpms, 1415 .dpms = drm_helper_connector_dpms,
1421 .detect = psb_intel_dp_detect, 1416 .detect = cdv_intel_dp_detect,
1422 .fill_modes = drm_helper_probe_single_connector_modes, 1417 .fill_modes = drm_helper_probe_single_connector_modes,
1423 .set_property = psb_intel_dp_set_property, 1418 .set_property = cdv_intel_dp_set_property,
1424 .destroy = psb_intel_dp_destroy, 1419 .destroy = cdv_intel_dp_destroy,
1425}; 1420};
1426 1421
1427static const struct drm_connector_helper_funcs psb_intel_dp_connector_helper_funcs = { 1422static const struct drm_connector_helper_funcs cdv_intel_dp_connector_helper_funcs = {
1428 .get_modes = psb_intel_dp_get_modes, 1423 .get_modes = cdv_intel_dp_get_modes,
1429 .mode_valid = psb_intel_dp_mode_valid, 1424 .mode_valid = cdv_intel_dp_mode_valid,
1430 .best_encoder = psb_intel_best_encoder, 1425 .best_encoder = psb_intel_best_encoder,
1431}; 1426};
1432 1427
1433static const struct drm_encoder_funcs psb_intel_dp_enc_funcs = { 1428static const struct drm_encoder_funcs cdv_intel_dp_enc_funcs = {
1434 .destroy = psb_intel_dp_encoder_destroy, 1429 .destroy = cdv_intel_dp_encoder_destroy,
1435}; 1430};
1436 1431
1437 1432
1438static void 1433static void cdv_intel_dp_add_properties(struct drm_connector *connector)
1439psb_intel_dp_add_properties(struct psb_intel_output *output, struct drm_connector *connector)
1440{ 1434{
1441 psb_intel_attach_force_audio_property(connector); 1435 cdv_intel_attach_force_audio_property(connector);
1442 psb_intel_attach_broadcast_rgb_property(connector); 1436 cdv_intel_attach_broadcast_rgb_property(connector);
1443} 1437}
1444 1438
1445void 1439void
1446psb_intel_dp_init(struct drm_device *dev, struct psb_intel_mode_device *mode_dev, int output_reg) 1440cdv_intel_dp_init(struct drm_device *dev, struct psb_intel_mode_device *mode_dev, int output_reg)
1447{ 1441{
1442 struct psb_intel_encoder *psb_intel_encoder;
1443 struct psb_intel_connector *psb_intel_connector;
1448 struct drm_connector *connector; 1444 struct drm_connector *connector;
1449 struct drm_encoder *encoder; 1445 struct drm_encoder *encoder;
1450 struct psb_intel_output *psb_intel_output; 1446 struct cdv_intel_dp *intel_dp;
1451 struct psb_intel_dp *intel_dp;
1452 const char *name = NULL; 1447 const char *name = NULL;
1453 int type;
1454 1448
1455 psb_intel_output = kzalloc(sizeof(struct psb_intel_output) + 1449 psb_intel_encoder = kzalloc(sizeof(struct psb_intel_encoder), GFP_KERNEL);
1456 sizeof(struct psb_intel_dp), GFP_KERNEL); 1450 if (!psb_intel_encoder)
1457 if (!psb_intel_output)
1458 return; 1451 return;
1452 psb_intel_connector = kzalloc(sizeof(struct psb_intel_connector), GFP_KERNEL);
1453 if (!psb_intel_connector)
1454 goto err_connector;
1455 intel_dp = kzalloc(sizeof(struct cdv_intel_dp), GFP_KERNEL);
1456 if (!intel_dp)
1457 goto err_priv;
1458
1459 connector = &psb_intel_connector->base;
1460 encoder = &psb_intel_encoder->base;
1459 1461
1460 intel_dp = (struct psb_intel_dp *)(psb_intel_output + 1); 1462 drm_connector_init(dev, connector, &cdv_intel_dp_connector_funcs, DRM_MODE_CONNECTOR_DisplayPort);
1461 psb_intel_output->mode_dev = mode_dev; 1463 drm_encoder_init(dev, encoder, &cdv_intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS);
1462 connector = &psb_intel_output->base;
1463 encoder = &psb_intel_output->enc;
1464 psb_intel_output->dev_priv=intel_dp;
1465 intel_dp->output = psb_intel_output;
1466 1464
1465 psb_intel_connector_attach_encoder(psb_intel_connector, psb_intel_encoder);
1466 psb_intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
1467
1468 psb_intel_encoder->dev_priv=intel_dp;
1469 intel_dp->encoder = psb_intel_encoder;
1467 intel_dp->output_reg = output_reg; 1470 intel_dp->output_reg = output_reg;
1468 1471
1469 type = DRM_MODE_CONNECTOR_DisplayPort; 1472 drm_encoder_helper_add(encoder, &cdv_intel_dp_helper_funcs);
1470 psb_intel_output->type = INTEL_OUTPUT_DISPLAYPORT; 1473 drm_connector_helper_add(connector, &cdv_intel_dp_connector_helper_funcs);
1471
1472 drm_connector_init(dev, connector, &psb_intel_dp_connector_funcs, type);
1473 drm_connector_helper_add(connector, &psb_intel_dp_connector_helper_funcs);
1474 1474
1475 connector->polled = DRM_CONNECTOR_POLL_HPD; 1475 connector->polled = DRM_CONNECTOR_POLL_HPD;
1476 1476 connector->interlace_allowed = false;
1477 connector->interlace_allowed = 0; 1477 connector->doublescan_allowed = false;
1478 connector->doublescan_allowed = 0;
1479
1480 drm_encoder_init(dev, encoder, &psb_intel_dp_enc_funcs,
1481 DRM_MODE_ENCODER_TMDS);
1482 drm_encoder_helper_add(encoder, &psb_intel_dp_helper_funcs);
1483
1484 drm_mode_connector_attach_encoder(&psb_intel_output->base,
1485 &psb_intel_output->enc);
1486 1478
1487 drm_sysfs_connector_add(connector); 1479 drm_sysfs_connector_add(connector);
1488 1480
@@ -1490,15 +1482,21 @@ psb_intel_dp_init(struct drm_device *dev, struct psb_intel_mode_device *mode_dev
1490 switch (output_reg) { 1482 switch (output_reg) {
1491 case DP_B: 1483 case DP_B:
1492 name = "DPDDC-B"; 1484 name = "DPDDC-B";
1493 psb_intel_output->ddi_select = (DP_MASK | DDI0_SELECT); 1485 psb_intel_encoder->ddi_select = (DP_MASK | DDI0_SELECT);
1494 break; 1486 break;
1495 case DP_C: 1487 case DP_C:
1496 name = "DPDDC-C"; 1488 name = "DPDDC-C";
1497 psb_intel_output->ddi_select = (DP_MASK | DDI1_SELECT); 1489 psb_intel_encoder->ddi_select = (DP_MASK | DDI1_SELECT);
1498 break; 1490 break;
1499 } 1491 }
1500 1492
1501 psb_intel_dp_i2c_init(psb_intel_output, name); 1493 cdv_intel_dp_i2c_init(psb_intel_connector, psb_intel_encoder, name);
1502 psb_intel_dp_add_properties(psb_intel_output, connector); 1494 /* FIXME:fail check */
1495 cdv_intel_dp_add_properties(connector);
1496 return;
1503 1497
1498err_priv:
1499 kfree(psb_intel_connector);
1500err_connector:
1501 kfree(psb_intel_encoder);
1504} 1502}
diff --git a/drivers/gpu/drm/gma500/psb_intel_drv.h b/drivers/gpu/drm/gma500/psb_intel_drv.h
index c574c0199103..c53e592604c8 100644
--- a/drivers/gpu/drm/gma500/psb_intel_drv.h
+++ b/drivers/gpu/drm/gma500/psb_intel_drv.h
@@ -288,4 +288,20 @@ extern void gma_intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
288extern void gma_intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit); 288extern void gma_intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
289extern void gma_intel_teardown_gmbus(struct drm_device *dev); 289extern void gma_intel_teardown_gmbus(struct drm_device *dev);
290 290
291/* DP support */
292extern void cdv_intel_dp_init(struct drm_device *dev, struct psb_intel_mode_device *mode_dev, int output_reg);
293extern void psb_intel_dp_set_m_n(struct drm_crtc *crtc,
294 struct drm_display_mode *mode,
295 struct drm_display_mode *adjusted_mode);
296
297extern void psb_intel_attach_force_audio_property(struct drm_connector *connector);
298extern void psb_intel_attach_broadcast_rgb_property(struct drm_connector *connector);
299
300extern int cdv_sb_read(struct drm_device *dev, u32 reg, u32 *val);
301extern int cdv_sb_write(struct drm_device *dev, u32 reg, u32 val);
302extern void cdv_sb_reset(struct drm_device *dev);
303
304extern void cdv_intel_attach_force_audio_property(struct drm_connector *connector);
305extern void cdv_intel_attach_broadcast_rgb_property(struct drm_connector *connector);
306
291#endif /* __INTEL_DRV_H__ */ 307#endif /* __INTEL_DRV_H__ */
generated by cgit v1.2.2 (git 2.25.0) at 2026-04-04 20:45:35 -0400