diff options
author | Rahul Sharma <rahul.sharma@samsung.com> | 2013-06-19 08:51:08 -0400 |
---|---|---|
committer | Inki Dae <daeinki@gmail.com> | 2013-06-28 08:13:57 -0400 |
commit | def5e095719dbc808c856dd5c64749b867b3984a (patch) | |
tree | a20ff1e2efddc1ba9071f112d3e908dd1899b112 /drivers/gpu/drm/exynos | |
parent | cc57caf0cfe74e536910f587a369af4a8550a4ee (diff) |
drm/exynos: add support for exynos5420 mixer
Add support for exynos5420 mixer IP in the drm mixer driver.
Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Acked-by: Seung-Woo Kim <sw0312.kim@samsung.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
Diffstat (limited to 'drivers/gpu/drm/exynos')
-rw-r--r-- | drivers/gpu/drm/exynos/exynos_mixer.c | 49 | ||||
-rw-r--r-- | drivers/gpu/drm/exynos/regs-mixer.h | 7 |
2 files changed, 44 insertions, 12 deletions
diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c b/drivers/gpu/drm/exynos/exynos_mixer.c index 62255011c9d6..b1280b43931c 100644 --- a/drivers/gpu/drm/exynos/exynos_mixer.c +++ b/drivers/gpu/drm/exynos/exynos_mixer.c | |||
@@ -78,6 +78,7 @@ struct mixer_resources { | |||
78 | enum mixer_version_id { | 78 | enum mixer_version_id { |
79 | MXR_VER_0_0_0_16, | 79 | MXR_VER_0_0_0_16, |
80 | MXR_VER_16_0_33_0, | 80 | MXR_VER_16_0_33_0, |
81 | MXR_VER_128_0_0_184, | ||
81 | }; | 82 | }; |
82 | 83 | ||
83 | struct mixer_context { | 84 | struct mixer_context { |
@@ -283,17 +284,19 @@ static void mixer_cfg_scan(struct mixer_context *ctx, unsigned int height) | |||
283 | val = (ctx->interlace ? MXR_CFG_SCAN_INTERLACE : | 284 | val = (ctx->interlace ? MXR_CFG_SCAN_INTERLACE : |
284 | MXR_CFG_SCAN_PROGRASSIVE); | 285 | MXR_CFG_SCAN_PROGRASSIVE); |
285 | 286 | ||
286 | /* choosing between porper HD and SD mode */ | 287 | if (ctx->mxr_ver != MXR_VER_128_0_0_184) { |
287 | if (height <= 480) | 288 | /* choosing between proper HD and SD mode */ |
288 | val |= MXR_CFG_SCAN_NTSC | MXR_CFG_SCAN_SD; | 289 | if (height <= 480) |
289 | else if (height <= 576) | 290 | val |= MXR_CFG_SCAN_NTSC | MXR_CFG_SCAN_SD; |
290 | val |= MXR_CFG_SCAN_PAL | MXR_CFG_SCAN_SD; | 291 | else if (height <= 576) |
291 | else if (height <= 720) | 292 | val |= MXR_CFG_SCAN_PAL | MXR_CFG_SCAN_SD; |
292 | val |= MXR_CFG_SCAN_HD_720 | MXR_CFG_SCAN_HD; | 293 | else if (height <= 720) |
293 | else if (height <= 1080) | 294 | val |= MXR_CFG_SCAN_HD_720 | MXR_CFG_SCAN_HD; |
294 | val |= MXR_CFG_SCAN_HD_1080 | MXR_CFG_SCAN_HD; | 295 | else if (height <= 1080) |
295 | else | 296 | val |= MXR_CFG_SCAN_HD_1080 | MXR_CFG_SCAN_HD; |
296 | val |= MXR_CFG_SCAN_HD_720 | MXR_CFG_SCAN_HD; | 297 | else |
298 | val |= MXR_CFG_SCAN_HD_720 | MXR_CFG_SCAN_HD; | ||
299 | } | ||
297 | 300 | ||
298 | mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_SCAN_MASK); | 301 | mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_SCAN_MASK); |
299 | } | 302 | } |
@@ -557,6 +560,14 @@ static void mixer_graph_buffer(struct mixer_context *ctx, int win) | |||
557 | /* setup geometry */ | 560 | /* setup geometry */ |
558 | mixer_reg_write(res, MXR_GRAPHIC_SPAN(win), win_data->fb_width); | 561 | mixer_reg_write(res, MXR_GRAPHIC_SPAN(win), win_data->fb_width); |
559 | 562 | ||
563 | /* setup display size */ | ||
564 | if (ctx->mxr_ver == MXR_VER_128_0_0_184 && | ||
565 | win == MIXER_DEFAULT_WIN) { | ||
566 | val = MXR_MXR_RES_HEIGHT(win_data->fb_height); | ||
567 | val |= MXR_MXR_RES_WIDTH(win_data->fb_width); | ||
568 | mixer_reg_write(res, MXR_RESOLUTION, val); | ||
569 | } | ||
570 | |||
560 | val = MXR_GRP_WH_WIDTH(win_data->crtc_width); | 571 | val = MXR_GRP_WH_WIDTH(win_data->crtc_width); |
561 | val |= MXR_GRP_WH_HEIGHT(win_data->crtc_height); | 572 | val |= MXR_GRP_WH_HEIGHT(win_data->crtc_height); |
562 | val |= MXR_GRP_WH_H_SCALE(x_ratio); | 573 | val |= MXR_GRP_WH_H_SCALE(x_ratio); |
@@ -581,7 +592,8 @@ static void mixer_graph_buffer(struct mixer_context *ctx, int win) | |||
581 | mixer_cfg_layer(ctx, win, true); | 592 | mixer_cfg_layer(ctx, win, true); |
582 | 593 | ||
583 | /* layer update mandatory for mixer 16.0.33.0 */ | 594 | /* layer update mandatory for mixer 16.0.33.0 */ |
584 | if (ctx->mxr_ver == MXR_VER_16_0_33_0) | 595 | if (ctx->mxr_ver == MXR_VER_16_0_33_0 || |
596 | ctx->mxr_ver == MXR_VER_128_0_0_184) | ||
585 | mixer_layer_update(ctx); | 597 | mixer_layer_update(ctx); |
586 | 598 | ||
587 | mixer_run(ctx); | 599 | mixer_run(ctx); |
@@ -816,6 +828,7 @@ static void mixer_win_disable(void *ctx, int win) | |||
816 | 828 | ||
817 | static int mixer_check_mode(void *ctx, struct drm_display_mode *mode) | 829 | static int mixer_check_mode(void *ctx, struct drm_display_mode *mode) |
818 | { | 830 | { |
831 | struct mixer_context *mixer_ctx = ctx; | ||
819 | u32 w, h; | 832 | u32 w, h; |
820 | 833 | ||
821 | w = mode->hdisplay; | 834 | w = mode->hdisplay; |
@@ -825,6 +838,10 @@ static int mixer_check_mode(void *ctx, struct drm_display_mode *mode) | |||
825 | mode->hdisplay, mode->vdisplay, mode->vrefresh, | 838 | mode->hdisplay, mode->vdisplay, mode->vrefresh, |
826 | (mode->flags & DRM_MODE_FLAG_INTERLACE) ? 1 : 0); | 839 | (mode->flags & DRM_MODE_FLAG_INTERLACE) ? 1 : 0); |
827 | 840 | ||
841 | if (mixer_ctx->mxr_ver == MXR_VER_0_0_0_16 || | ||
842 | mixer_ctx->mxr_ver == MXR_VER_128_0_0_184) | ||
843 | return 0; | ||
844 | |||
828 | if ((w >= 464 && w <= 720 && h >= 261 && h <= 576) || | 845 | if ((w >= 464 && w <= 720 && h >= 261 && h <= 576) || |
829 | (w >= 1024 && w <= 1280 && h >= 576 && h <= 720) || | 846 | (w >= 1024 && w <= 1280 && h >= 576 && h <= 720) || |
830 | (w >= 1664 && w <= 1920 && h >= 936 && h <= 1080)) | 847 | (w >= 1664 && w <= 1920 && h >= 936 && h <= 1080)) |
@@ -1115,6 +1132,11 @@ static int vp_resources_init(struct exynos_drm_hdmi_context *ctx, | |||
1115 | return 0; | 1132 | return 0; |
1116 | } | 1133 | } |
1117 | 1134 | ||
1135 | static struct mixer_drv_data exynos5420_mxr_drv_data = { | ||
1136 | .version = MXR_VER_128_0_0_184, | ||
1137 | .is_vp_enabled = 0, | ||
1138 | }; | ||
1139 | |||
1118 | static struct mixer_drv_data exynos5250_mxr_drv_data = { | 1140 | static struct mixer_drv_data exynos5250_mxr_drv_data = { |
1119 | .version = MXR_VER_16_0_33_0, | 1141 | .version = MXR_VER_16_0_33_0, |
1120 | .is_vp_enabled = 0, | 1142 | .is_vp_enabled = 0, |
@@ -1145,6 +1167,9 @@ static struct of_device_id mixer_match_types[] = { | |||
1145 | .compatible = "samsung,exynos5250-mixer", | 1167 | .compatible = "samsung,exynos5250-mixer", |
1146 | .data = &exynos5250_mxr_drv_data, | 1168 | .data = &exynos5250_mxr_drv_data, |
1147 | }, { | 1169 | }, { |
1170 | .compatible = "samsung,exynos5420-mixer", | ||
1171 | .data = &exynos5420_mxr_drv_data, | ||
1172 | }, { | ||
1148 | /* end node */ | 1173 | /* end node */ |
1149 | } | 1174 | } |
1150 | }; | 1175 | }; |
diff --git a/drivers/gpu/drm/exynos/regs-mixer.h b/drivers/gpu/drm/exynos/regs-mixer.h index 5d8dbc0301e6..4537026bc385 100644 --- a/drivers/gpu/drm/exynos/regs-mixer.h +++ b/drivers/gpu/drm/exynos/regs-mixer.h | |||
@@ -44,6 +44,9 @@ | |||
44 | #define MXR_CM_COEFF_Y 0x0080 | 44 | #define MXR_CM_COEFF_Y 0x0080 |
45 | #define MXR_CM_COEFF_CB 0x0084 | 45 | #define MXR_CM_COEFF_CB 0x0084 |
46 | #define MXR_CM_COEFF_CR 0x0088 | 46 | #define MXR_CM_COEFF_CR 0x0088 |
47 | #define MXR_MO 0x0304 | ||
48 | #define MXR_RESOLUTION 0x0310 | ||
49 | |||
47 | #define MXR_GRAPHIC0_BASE_S 0x2024 | 50 | #define MXR_GRAPHIC0_BASE_S 0x2024 |
48 | #define MXR_GRAPHIC1_BASE_S 0x2044 | 51 | #define MXR_GRAPHIC1_BASE_S 0x2044 |
49 | 52 | ||
@@ -119,6 +122,10 @@ | |||
119 | #define MXR_GRP_WH_WIDTH(x) MXR_MASK_VAL(x, 26, 16) | 122 | #define MXR_GRP_WH_WIDTH(x) MXR_MASK_VAL(x, 26, 16) |
120 | #define MXR_GRP_WH_HEIGHT(x) MXR_MASK_VAL(x, 10, 0) | 123 | #define MXR_GRP_WH_HEIGHT(x) MXR_MASK_VAL(x, 10, 0) |
121 | 124 | ||
125 | /* bits for MXR_RESOLUTION */ | ||
126 | #define MXR_MXR_RES_HEIGHT(x) MXR_MASK_VAL(x, 26, 16) | ||
127 | #define MXR_MXR_RES_WIDTH(x) MXR_MASK_VAL(x, 10, 0) | ||
128 | |||
122 | /* bits for MXR_GRAPHICn_SXY */ | 129 | /* bits for MXR_GRAPHICn_SXY */ |
123 | #define MXR_GRP_SXY_SX(x) MXR_MASK_VAL(x, 26, 16) | 130 | #define MXR_GRP_SXY_SX(x) MXR_MASK_VAL(x, 26, 16) |
124 | #define MXR_GRP_SXY_SY(x) MXR_MASK_VAL(x, 10, 0) | 131 | #define MXR_GRP_SXY_SY(x) MXR_MASK_VAL(x, 10, 0) |