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authorLeela Krishna Amudala <l.krishna@samsung.com>2013-03-07 23:28:52 -0500
committerInki Dae <inki.dae@samsung.com>2013-03-20 06:09:10 -0400
commit0f10cf1463c6fc02a9e85bf098ef3c215d94b1e3 (patch)
tree57e5fbcc0b0242a556996be7ae6108d8906fa15b /drivers/gpu/drm/exynos
parent9800935a215ddf278da4860f59b4d29d2f429152 (diff)
drm/exynos: fimd: calculate the correct address offset
Calculate the correct address offset values for alpha and color key control registers based on exynos4 and exynos5 user manuals. Also remove VIDOSD_C_SIZE_W0 macro and fix comments about registers for size and alpha. Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com> Acked-by: Joonyoung Shim <jy0922.shim@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
Diffstat (limited to 'drivers/gpu/drm/exynos')
-rw-r--r--drivers/gpu/drm/exynos/exynos_drm_fimd.c17
1 files changed, 9 insertions, 8 deletions
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
index 549cb7db9c9f..98cc14725ba9 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
@@ -38,11 +38,12 @@
38/* position control register for hardware window 0, 2 ~ 4.*/ 38/* position control register for hardware window 0, 2 ~ 4.*/
39#define VIDOSD_A(win) (VIDOSD_BASE + 0x00 + (win) * 16) 39#define VIDOSD_A(win) (VIDOSD_BASE + 0x00 + (win) * 16)
40#define VIDOSD_B(win) (VIDOSD_BASE + 0x04 + (win) * 16) 40#define VIDOSD_B(win) (VIDOSD_BASE + 0x04 + (win) * 16)
41/* size control register for hardware window 0. */ 41/*
42#define VIDOSD_C_SIZE_W0 (VIDOSD_BASE + 0x08) 42 * size control register for hardware windows 0 and alpha control register
43/* alpha control register for hardware window 1 ~ 4. */ 43 * for hardware windows 1 ~ 4
44#define VIDOSD_C(win) (VIDOSD_BASE + 0x18 + (win) * 16) 44 */
45/* size control register for hardware window 1 ~ 4. */ 45#define VIDOSD_C(win) (VIDOSD_BASE + 0x08 + (win) * 16)
46/* size control register for hardware windows 1 ~ 2. */
46#define VIDOSD_D(win) (VIDOSD_BASE + 0x0C + (win) * 16) 47#define VIDOSD_D(win) (VIDOSD_BASE + 0x0C + (win) * 16)
47 48
48#define VIDWx_BUF_START(win, buf) (VIDW_BUF_START(buf) + (win) * 8) 49#define VIDWx_BUF_START(win, buf) (VIDW_BUF_START(buf) + (win) * 8)
@@ -50,9 +51,9 @@
50#define VIDWx_BUF_SIZE(win, buf) (VIDW_BUF_SIZE(buf) + (win) * 4) 51#define VIDWx_BUF_SIZE(win, buf) (VIDW_BUF_SIZE(buf) + (win) * 4)
51 52
52/* color key control register for hardware window 1 ~ 4. */ 53/* color key control register for hardware window 1 ~ 4. */
53#define WKEYCON0_BASE(x) ((WKEYCON0 + 0x140) + (x * 8)) 54#define WKEYCON0_BASE(x) ((WKEYCON0 + 0x140) + ((x - 1) * 8))
54/* color key value register for hardware window 1 ~ 4. */ 55/* color key value register for hardware window 1 ~ 4. */
55#define WKEYCON1_BASE(x) ((WKEYCON1 + 0x140) + (x * 8)) 56#define WKEYCON1_BASE(x) ((WKEYCON1 + 0x140) + ((x - 1) * 8))
56 57
57/* FIMD has totally five hardware windows. */ 58/* FIMD has totally five hardware windows. */
58#define WINDOWS_NR 5 59#define WINDOWS_NR 5
@@ -581,7 +582,7 @@ static void fimd_win_commit(struct device *dev, int zpos)
581 if (win != 3 && win != 4) { 582 if (win != 3 && win != 4) {
582 u32 offset = VIDOSD_D(win); 583 u32 offset = VIDOSD_D(win);
583 if (win == 0) 584 if (win == 0)
584 offset = VIDOSD_C_SIZE_W0; 585 offset = VIDOSD_C(win);
585 val = win_data->ovl_width * win_data->ovl_height; 586 val = win_data->ovl_width * win_data->ovl_height;
586 writel(val, ctx->regs + offset); 587 writel(val, ctx->regs + offset);
587 588