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authorGustavo Padovan <gustavo.padovan@collabora.co.uk>2014-11-03 15:13:27 -0500
committerInki Dae <daeinki@gmail.com>2015-01-25 07:28:02 -0500
commit8837deeab462a30d5a760fa1ae7c29242d985700 (patch)
tree501c06a949c46235f6f70752b5b93127f379e2a9 /drivers/gpu/drm/exynos/exynos_drm_plane.c
parent1e3b423d0b79dfa25e5f09f558da264d4050eca8 (diff)
drm/exynos: remove struct exynos_drm_overlay
struct exynos_drm_overlay has no practical advantage nor serves as important piece of the exynos API design. The only place it was used was inside the struct exynos_plane which was just causing a extra access overhead. Users had to access the overlay first and just then get the plane information it contains. This patch merges struct exynos_drm_overlay into struct exynos_plane. It also renames struct exynos_plane to struct exynos_drm_plane. The rational is to cut one step to access plane information. Signed-off-by: Gustavo Padovan <gustavo.padovan@collabora.co.uk> Signed-off-by: Inki Dae <inki.dae@samsung.com>
Diffstat (limited to 'drivers/gpu/drm/exynos/exynos_drm_plane.c')
-rw-r--r--drivers/gpu/drm/exynos/exynos_drm_plane.c85
1 files changed, 37 insertions, 48 deletions
diff --git a/drivers/gpu/drm/exynos/exynos_drm_plane.c b/drivers/gpu/drm/exynos/exynos_drm_plane.c
index 7d768612e567..843f74175094 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_plane.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_plane.c
@@ -18,14 +18,6 @@
18#include "exynos_drm_gem.h" 18#include "exynos_drm_gem.h"
19#include "exynos_drm_plane.h" 19#include "exynos_drm_plane.h"
20 20
21#define to_exynos_plane(x) container_of(x, struct exynos_plane, base)
22
23struct exynos_plane {
24 struct drm_plane base;
25 struct exynos_drm_overlay overlay;
26 bool enabled;
27};
28
29static const uint32_t formats[] = { 21static const uint32_t formats[] = {
30 DRM_FORMAT_XRGB8888, 22 DRM_FORMAT_XRGB8888,
31 DRM_FORMAT_ARGB8888, 23 DRM_FORMAT_ARGB8888,
@@ -75,9 +67,8 @@ int exynos_plane_mode_set(struct drm_plane *plane, struct drm_crtc *crtc,
75 uint32_t src_x, uint32_t src_y, 67 uint32_t src_x, uint32_t src_y,
76 uint32_t src_w, uint32_t src_h) 68 uint32_t src_w, uint32_t src_h)
77{ 69{
78 struct exynos_plane *exynos_plane = to_exynos_plane(plane); 70 struct exynos_drm_plane *exynos_plane = to_exynos_plane(plane);
79 struct exynos_drm_manager *manager = to_exynos_crtc(crtc)->manager; 71 struct exynos_drm_manager *manager = to_exynos_crtc(crtc)->manager;
80 struct exynos_drm_overlay *overlay = &exynos_plane->overlay;
81 unsigned int actual_w; 72 unsigned int actual_w;
82 unsigned int actual_h; 73 unsigned int actual_h;
83 int nr; 74 int nr;
@@ -92,10 +83,10 @@ int exynos_plane_mode_set(struct drm_plane *plane, struct drm_crtc *crtc,
92 return -EFAULT; 83 return -EFAULT;
93 } 84 }
94 85
95 overlay->dma_addr[i] = buffer->dma_addr; 86 exynos_plane->dma_addr[i] = buffer->dma_addr;
96 87
97 DRM_DEBUG_KMS("buffer: %d, dma_addr = 0x%lx\n", 88 DRM_DEBUG_KMS("buffer: %d, dma_addr = 0x%lx\n",
98 i, (unsigned long)overlay->dma_addr[i]); 89 i, (unsigned long)exynos_plane->dma_addr[i]);
99 } 90 }
100 91
101 actual_w = exynos_plane_get_size(crtc_x, crtc_w, crtc->mode.hdisplay); 92 actual_w = exynos_plane_get_size(crtc_x, crtc_w, crtc->mode.hdisplay);
@@ -114,54 +105,52 @@ int exynos_plane_mode_set(struct drm_plane *plane, struct drm_crtc *crtc,
114 } 105 }
115 106
116 /* set drm framebuffer data. */ 107 /* set drm framebuffer data. */
117 overlay->fb_x = src_x; 108 exynos_plane->fb_x = src_x;
118 overlay->fb_y = src_y; 109 exynos_plane->fb_y = src_y;
119 overlay->fb_width = fb->width; 110 exynos_plane->fb_width = fb->width;
120 overlay->fb_height = fb->height; 111 exynos_plane->fb_height = fb->height;
121 overlay->src_width = src_w; 112 exynos_plane->src_width = src_w;
122 overlay->src_height = src_h; 113 exynos_plane->src_height = src_h;
123 overlay->bpp = fb->bits_per_pixel; 114 exynos_plane->bpp = fb->bits_per_pixel;
124 overlay->pitch = fb->pitches[0]; 115 exynos_plane->pitch = fb->pitches[0];
125 overlay->pixel_format = fb->pixel_format; 116 exynos_plane->pixel_format = fb->pixel_format;
126 117
127 /* set overlay range to be displayed. */ 118 /* set plane range to be displayed. */
128 overlay->crtc_x = crtc_x; 119 exynos_plane->crtc_x = crtc_x;
129 overlay->crtc_y = crtc_y; 120 exynos_plane->crtc_y = crtc_y;
130 overlay->crtc_width = actual_w; 121 exynos_plane->crtc_width = actual_w;
131 overlay->crtc_height = actual_h; 122 exynos_plane->crtc_height = actual_h;
132 123
133 /* set drm mode data. */ 124 /* set drm mode data. */
134 overlay->mode_width = crtc->mode.hdisplay; 125 exynos_plane->mode_width = crtc->mode.hdisplay;
135 overlay->mode_height = crtc->mode.vdisplay; 126 exynos_plane->mode_height = crtc->mode.vdisplay;
136 overlay->refresh = crtc->mode.vrefresh; 127 exynos_plane->refresh = crtc->mode.vrefresh;
137 overlay->scan_flag = crtc->mode.flags; 128 exynos_plane->scan_flag = crtc->mode.flags;
138 129
139 DRM_DEBUG_KMS("overlay : offset_x/y(%d,%d), width/height(%d,%d)", 130 DRM_DEBUG_KMS("plane : offset_x/y(%d,%d), width/height(%d,%d)",
140 overlay->crtc_x, overlay->crtc_y, 131 exynos_plane->crtc_x, exynos_plane->crtc_y,
141 overlay->crtc_width, overlay->crtc_height); 132 exynos_plane->crtc_width, exynos_plane->crtc_height);
142 133
143 plane->crtc = crtc; 134 plane->crtc = crtc;
144 135
145 if (manager->ops->win_mode_set) 136 if (manager->ops->win_mode_set)
146 manager->ops->win_mode_set(manager, overlay); 137 manager->ops->win_mode_set(manager, exynos_plane);
147 138
148 return 0; 139 return 0;
149} 140}
150 141
151void exynos_plane_commit(struct drm_plane *plane) 142void exynos_plane_commit(struct drm_plane *plane)
152{ 143{
153 struct exynos_plane *exynos_plane = to_exynos_plane(plane); 144 struct exynos_drm_plane *exynos_plane = to_exynos_plane(plane);
154 struct exynos_drm_overlay *overlay = &exynos_plane->overlay;
155 struct exynos_drm_manager *manager = to_exynos_crtc(plane->crtc)->manager; 145 struct exynos_drm_manager *manager = to_exynos_crtc(plane->crtc)->manager;
156 146
157 if (manager->ops->win_commit) 147 if (manager->ops->win_commit)
158 manager->ops->win_commit(manager, overlay->zpos); 148 manager->ops->win_commit(manager, exynos_plane->zpos);
159} 149}
160 150
161void exynos_plane_dpms(struct drm_plane *plane, int mode) 151void exynos_plane_dpms(struct drm_plane *plane, int mode)
162{ 152{
163 struct exynos_plane *exynos_plane = to_exynos_plane(plane); 153 struct exynos_drm_plane *exynos_plane = to_exynos_plane(plane);
164 struct exynos_drm_overlay *overlay = &exynos_plane->overlay;
165 struct exynos_drm_manager *manager; 154 struct exynos_drm_manager *manager;
166 155
167 if (mode == DRM_MODE_DPMS_ON) { 156 if (mode == DRM_MODE_DPMS_ON) {
@@ -170,7 +159,7 @@ void exynos_plane_dpms(struct drm_plane *plane, int mode)
170 159
171 manager = to_exynos_crtc(plane->crtc)->manager; 160 manager = to_exynos_crtc(plane->crtc)->manager;
172 if (manager->ops->win_enable) 161 if (manager->ops->win_enable)
173 manager->ops->win_enable(manager, overlay->zpos); 162 manager->ops->win_enable(manager, exynos_plane->zpos);
174 163
175 exynos_plane->enabled = true; 164 exynos_plane->enabled = true;
176 } else { 165 } else {
@@ -179,7 +168,7 @@ void exynos_plane_dpms(struct drm_plane *plane, int mode)
179 168
180 manager = to_exynos_crtc(plane->crtc)->manager; 169 manager = to_exynos_crtc(plane->crtc)->manager;
181 if (manager->ops->win_disable) 170 if (manager->ops->win_disable)
182 manager->ops->win_disable(manager, overlay->zpos); 171 manager->ops->win_disable(manager, exynos_plane->zpos);
183 172
184 exynos_plane->enabled = false; 173 exynos_plane->enabled = false;
185 } 174 }
@@ -215,7 +204,7 @@ static int exynos_disable_plane(struct drm_plane *plane)
215 204
216static void exynos_plane_destroy(struct drm_plane *plane) 205static void exynos_plane_destroy(struct drm_plane *plane)
217{ 206{
218 struct exynos_plane *exynos_plane = to_exynos_plane(plane); 207 struct exynos_drm_plane *exynos_plane = to_exynos_plane(plane);
219 208
220 exynos_disable_plane(plane); 209 exynos_disable_plane(plane);
221 drm_plane_cleanup(plane); 210 drm_plane_cleanup(plane);
@@ -227,11 +216,11 @@ static int exynos_plane_set_property(struct drm_plane *plane,
227 uint64_t val) 216 uint64_t val)
228{ 217{
229 struct drm_device *dev = plane->dev; 218 struct drm_device *dev = plane->dev;
230 struct exynos_plane *exynos_plane = to_exynos_plane(plane); 219 struct exynos_drm_plane *exynos_plane = to_exynos_plane(plane);
231 struct exynos_drm_private *dev_priv = dev->dev_private; 220 struct exynos_drm_private *dev_priv = dev->dev_private;
232 221
233 if (property == dev_priv->plane_zpos_property) { 222 if (property == dev_priv->plane_zpos_property) {
234 exynos_plane->overlay.zpos = val; 223 exynos_plane->zpos = val;
235 return 0; 224 return 0;
236 } 225 }
237 226
@@ -268,10 +257,10 @@ struct drm_plane *exynos_plane_init(struct drm_device *dev,
268 unsigned long possible_crtcs, 257 unsigned long possible_crtcs,
269 enum drm_plane_type type) 258 enum drm_plane_type type)
270{ 259{
271 struct exynos_plane *exynos_plane; 260 struct exynos_drm_plane *exynos_plane;
272 int err; 261 int err;
273 262
274 exynos_plane = kzalloc(sizeof(struct exynos_plane), GFP_KERNEL); 263 exynos_plane = kzalloc(sizeof(struct exynos_drm_plane), GFP_KERNEL);
275 if (!exynos_plane) 264 if (!exynos_plane)
276 return ERR_PTR(-ENOMEM); 265 return ERR_PTR(-ENOMEM);
277 266
@@ -285,7 +274,7 @@ struct drm_plane *exynos_plane_init(struct drm_device *dev,
285 } 274 }
286 275
287 if (type == DRM_PLANE_TYPE_PRIMARY) 276 if (type == DRM_PLANE_TYPE_PRIMARY)
288 exynos_plane->overlay.zpos = DEFAULT_ZPOS; 277 exynos_plane->zpos = DEFAULT_ZPOS;
289 else 278 else
290 exynos_plane_attach_zpos_property(&exynos_plane->base); 279 exynos_plane_attach_zpos_property(&exynos_plane->base);
291 280