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authorAndrzej Hajda <a.hajda@samsung.com>2014-03-20 04:09:00 -0400
committerInki Dae <daeinki@gmail.com>2014-03-23 11:36:41 -0400
commit1d531062cdc5fcb5e417886bb16f8228b6b1131d (patch)
tree1379546b0a599a54383fb9a56858541bc40bac26 /drivers/gpu/drm/exynos/exynos_drm_fimd.c
parent621c5d66633242ad2d1f824dfb7bae84753b3b3d (diff)
drm/exynos: fimd: remove unused variable
The patch removes unused vidcon0 field from fimd_context structure. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
Diffstat (limited to 'drivers/gpu/drm/exynos/exynos_drm_fimd.c')
-rw-r--r--drivers/gpu/drm/exynos/exynos_drm_fimd.c20
1 files changed, 6 insertions, 14 deletions
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
index 15d6b37c687d..40fd6ccfcd6f 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
@@ -114,7 +114,6 @@ struct fimd_context {
114 struct fimd_win_data win_data[WINDOWS_NR]; 114 struct fimd_win_data win_data[WINDOWS_NR];
115 unsigned int default_win; 115 unsigned int default_win;
116 unsigned long irq_flags; 116 unsigned long irq_flags;
117 u32 vidcon0;
118 u32 vidcon1; 117 u32 vidcon1;
119 bool suspended; 118 bool suspended;
120 int pipe; 119 int pipe;
@@ -266,26 +265,19 @@ static void fimd_commit(struct exynos_drm_manager *mgr)
266 VIDTCON2_HOZVAL_E(mode->hdisplay - 1); 265 VIDTCON2_HOZVAL_E(mode->hdisplay - 1);
267 writel(val, ctx->regs + driver_data->timing_base + VIDTCON2); 266 writel(val, ctx->regs + driver_data->timing_base + VIDTCON2);
268 267
269 /* setup clock source, clock divider, enable dma. */ 268 /*
270 val = ctx->vidcon0; 269 * fields of register with prefix '_F' would be updated
271 val &= ~(VIDCON0_CLKVAL_F_MASK | VIDCON0_CLKDIR); 270 * at vsync(same as dma start)
271 */
272 val = VIDCON0_ENVID | VIDCON0_ENVID_F;
272 273
273 if (ctx->driver_data->has_clksel) { 274 if (ctx->driver_data->has_clksel)
274 val &= ~VIDCON0_CLKSEL_MASK;
275 val |= VIDCON0_CLKSEL_LCD; 275 val |= VIDCON0_CLKSEL_LCD;
276 }
277 276
278 clkdiv = fimd_calc_clkdiv(ctx, mode); 277 clkdiv = fimd_calc_clkdiv(ctx, mode);
279 if (clkdiv > 1) 278 if (clkdiv > 1)
280 val |= VIDCON0_CLKVAL_F(clkdiv - 1) | VIDCON0_CLKDIR; 279 val |= VIDCON0_CLKVAL_F(clkdiv - 1) | VIDCON0_CLKDIR;
281 else
282 val &= ~VIDCON0_CLKDIR; /* 1:1 clock */
283 280
284 /*
285 * fields of register with prefix '_F' would be updated
286 * at vsync(same as dma start)
287 */
288 val |= VIDCON0_ENVID | VIDCON0_ENVID_F;
289 writel(val, ctx->regs + VIDCON0); 281 writel(val, ctx->regs + VIDCON0);
290} 282}
291 283