drm/exynos/fimc: fix source buffer registers

FIMC in default mode of operation uses only one input buffer,
but the driver used also second buffer, as a result only the
first frame was processed correctly. The patch fixes it.

Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Reviewed-by: Joonyoung Shim <jy0922.shim@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>

1 files changed, 8 insertions, 8 deletions

diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimc.c b/drivers/gpu/drm/exynos/exynos_drm_fimc.c
index c2648a0717be..68d38eb6774d 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fimc.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fimc.c
@@ -715,24 +715,24 @@ static int fimc_src_set_addr(struct device *dev,
         case IPP_BUF_ENQUEUE:
                 config = &property->config[EXYNOS_DRM_OPS_SRC];
                 fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_Y],
-                        EXYNOS_CIIYSA(buf_id));
+                        EXYNOS_CIIYSA0);
 
                 if (config->fmt == DRM_FORMAT_YVU420) {
                         fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_CR],
-                                EXYNOS_CIICBSA(buf_id));
+                                EXYNOS_CIICBSA0);
                         fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_CB],
-                                EXYNOS_CIICRSA(buf_id));
+                                EXYNOS_CIICRSA0);
                 } else {
                         fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_CB],
-                                EXYNOS_CIICBSA(buf_id));
+                                EXYNOS_CIICBSA0);
                         fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_CR],
-                                EXYNOS_CIICRSA(buf_id));
+                                EXYNOS_CIICRSA0);
                 }
                 break;
         case IPP_BUF_DEQUEUE:
-                fimc_write(ctx, 0x0, EXYNOS_CIIYSA(buf_id));
-                fimc_write(ctx, 0x0, EXYNOS_CIICBSA(buf_id));
-                fimc_write(ctx, 0x0, EXYNOS_CIICRSA(buf_id));
+                fimc_write(ctx, 0x0, EXYNOS_CIIYSA0);
+                fimc_write(ctx, 0x0, EXYNOS_CIICBSA0);
+                fimc_write(ctx, 0x0, EXYNOS_CIICRSA0);
                 break;
         default:
                 /* bypass */