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authorDave Airlie <airlied@redhat.com>2014-05-18 21:15:08 -0400
committerDave Airlie <airlied@redhat.com>2014-05-18 21:15:08 -0400
commit263432b021cd252570001c10404367e948ac10f0 (patch)
treec8ac4662ece75eab1554de8d180e430f55b18d97 /drivers/gpu/drm/ast
parente5daa1ddc1b01587cba2915390e52c0dd0190e1e (diff)
parent83c6620bae3f14adb2430fdcc367980fe3b7bee2 (diff)
Merge branch 'ast-updates' of ssh://people.freedesktop.org/~/linux into drm-next
Pull in latest updates to AST driver. * 'ast-updates' of ssh://people.freedesktop.org/~/linux: drm/ast: initial DP501 support (v0.2) drm/ast: rename the mindwm/moutdwm and deinline them drm/ast: resync the dram post code with upstream drm/ast: add AST 2400 support. drm/ast: add widescreen + rb modes from X.org driver (v2)
Diffstat (limited to 'drivers/gpu/drm/ast')
-rw-r--r--drivers/gpu/drm/ast/Makefile4
-rw-r--r--drivers/gpu/drm/ast/ast_dp501.c410
-rw-r--r--drivers/gpu/drm/ast/ast_drv.h24
-rw-r--r--drivers/gpu/drm/ast/ast_main.c90
-rw-r--r--drivers/gpu/drm/ast/ast_mode.c105
-rw-r--r--drivers/gpu/drm/ast/ast_post.c898
-rw-r--r--drivers/gpu/drm/ast/ast_tables.h67
7 files changed, 1046 insertions, 552 deletions
diff --git a/drivers/gpu/drm/ast/Makefile b/drivers/gpu/drm/ast/Makefile
index 8df4f284ee24..171aa0622b66 100644
--- a/drivers/gpu/drm/ast/Makefile
+++ b/drivers/gpu/drm/ast/Makefile
@@ -4,6 +4,6 @@
4 4
5ccflags-y := -Iinclude/drm 5ccflags-y := -Iinclude/drm
6 6
7ast-y := ast_drv.o ast_main.o ast_mode.o ast_fb.o ast_ttm.o ast_post.o 7ast-y := ast_drv.o ast_main.o ast_mode.o ast_fb.o ast_ttm.o ast_post.o ast_dp501.o
8 8
9obj-$(CONFIG_DRM_AST) := ast.o \ No newline at end of file 9obj-$(CONFIG_DRM_AST) := ast.o
diff --git a/drivers/gpu/drm/ast/ast_dp501.c b/drivers/gpu/drm/ast/ast_dp501.c
new file mode 100644
index 000000000000..5da4b62285fa
--- /dev/null
+++ b/drivers/gpu/drm/ast/ast_dp501.c
@@ -0,0 +1,410 @@
1
2#include <linux/firmware.h>
3#include <drm/drmP.h>
4#include "ast_drv.h"
5MODULE_FIRMWARE("ast_dp501_fw.bin");
6
7int ast_load_dp501_microcode(struct drm_device *dev)
8{
9 struct ast_private *ast = dev->dev_private;
10 static char *fw_name = "ast_dp501_fw.bin";
11 int err;
12 err = request_firmware(&ast->dp501_fw, fw_name, dev->dev);
13 if (err)
14 return err;
15
16 return 0;
17}
18
19static void send_ack(struct ast_private *ast)
20{
21 u8 sendack;
22 sendack = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0xff);
23 sendack |= 0x80;
24 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0x00, sendack);
25}
26
27static void send_nack(struct ast_private *ast)
28{
29 u8 sendack;
30 sendack = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0xff);
31 sendack &= ~0x80;
32 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0x00, sendack);
33}
34
35static bool wait_ack(struct ast_private *ast)
36{
37 u8 waitack;
38 u32 retry = 0;
39 do {
40 waitack = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd2, 0xff);
41 waitack &= 0x80;
42 udelay(100);
43 } while ((!waitack) && (retry++ < 1000));
44
45 if (retry < 1000)
46 return true;
47 else
48 return false;
49}
50
51static bool wait_nack(struct ast_private *ast)
52{
53 u8 waitack;
54 u32 retry = 0;
55 do {
56 waitack = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd2, 0xff);
57 waitack &= 0x80;
58 udelay(100);
59 } while ((waitack) && (retry++ < 1000));
60
61 if (retry < 1000)
62 return true;
63 else
64 return false;
65}
66
67static void set_cmd_trigger(struct ast_private *ast)
68{
69 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, ~0x40, 0x40);
70}
71
72static void clear_cmd_trigger(struct ast_private *ast)
73{
74 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, ~0x40, 0x00);
75}
76
77#if 0
78static bool wait_fw_ready(struct ast_private *ast)
79{
80 u8 waitready;
81 u32 retry = 0;
82 do {
83 waitready = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd2, 0xff);
84 waitready &= 0x40;
85 udelay(100);
86 } while ((!waitready) && (retry++ < 1000));
87
88 if (retry < 1000)
89 return true;
90 else
91 return false;
92}
93#endif
94
95static bool ast_write_cmd(struct drm_device *dev, u8 data)
96{
97 struct ast_private *ast = dev->dev_private;
98 int retry = 0;
99 if (wait_nack(ast)) {
100 send_nack(ast);
101 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9a, 0x00, data);
102 send_ack(ast);
103 set_cmd_trigger(ast);
104 do {
105 if (wait_ack(ast)) {
106 clear_cmd_trigger(ast);
107 send_nack(ast);
108 return true;
109 }
110 } while (retry++ < 100);
111 }
112 clear_cmd_trigger(ast);
113 send_nack(ast);
114 return false;
115}
116
117static bool ast_write_data(struct drm_device *dev, u8 data)
118{
119 struct ast_private *ast = dev->dev_private;
120
121 if (wait_nack(ast)) {
122 send_nack(ast);
123 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9a, 0x00, data);
124 send_ack(ast);
125 if (wait_ack(ast)) {
126 send_nack(ast);
127 return true;
128 }
129 }
130 send_nack(ast);
131 return false;
132}
133
134#if 0
135static bool ast_read_data(struct drm_device *dev, u8 *data)
136{
137 struct ast_private *ast = dev->dev_private;
138 u8 tmp;
139
140 *data = 0;
141
142 if (wait_ack(ast) == false)
143 return false;
144 tmp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd3, 0xff);
145 *data = tmp;
146 if (wait_nack(ast) == false) {
147 send_nack(ast);
148 return false;
149 }
150 send_nack(ast);
151 return true;
152}
153
154static void clear_cmd(struct ast_private *ast)
155{
156 send_nack(ast);
157 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9a, 0x00, 0x00);
158}
159#endif
160
161void ast_set_dp501_video_output(struct drm_device *dev, u8 mode)
162{
163 ast_write_cmd(dev, 0x40);
164 ast_write_data(dev, mode);
165
166 msleep(10);
167}
168
169static u32 get_fw_base(struct ast_private *ast)
170{
171 return ast_mindwm(ast, 0x1e6e2104) & 0x7fffffff;
172}
173
174bool ast_backup_fw(struct drm_device *dev, u8 *addr, u32 size)
175{
176 struct ast_private *ast = dev->dev_private;
177 u32 i, data;
178 u32 boot_address;
179
180 data = ast_mindwm(ast, 0x1e6e2100) & 0x01;
181 if (data) {
182 boot_address = get_fw_base(ast);
183 for (i = 0; i < size; i += 4)
184 *(u32 *)(addr + i) = ast_mindwm(ast, boot_address + i);
185 return true;
186 }
187 return false;
188}
189
190bool ast_launch_m68k(struct drm_device *dev)
191{
192 struct ast_private *ast = dev->dev_private;
193 u32 i, data, len = 0;
194 u32 boot_address;
195 u8 *fw_addr = NULL;
196 u8 jreg;
197
198 data = ast_mindwm(ast, 0x1e6e2100) & 0x01;
199 if (!data) {
200
201 if (ast->dp501_fw_addr) {
202 fw_addr = ast->dp501_fw_addr;
203 len = 32*1024;
204 } else if (ast->dp501_fw) {
205 fw_addr = (u8 *)ast->dp501_fw->data;
206 len = ast->dp501_fw->size;
207 }
208 /* Get BootAddress */
209 ast_moutdwm(ast, 0x1e6e2000, 0x1688a8a8);
210 data = ast_mindwm(ast, 0x1e6e0004);
211 switch (data & 0x03) {
212 case 0:
213 boot_address = 0x44000000;
214 break;
215 default:
216 case 1:
217 boot_address = 0x48000000;
218 break;
219 case 2:
220 boot_address = 0x50000000;
221 break;
222 case 3:
223 boot_address = 0x60000000;
224 break;
225 }
226 boot_address -= 0x200000; /* -2MB */
227
228 /* copy image to buffer */
229 for (i = 0; i < len; i += 4) {
230 data = *(u32 *)(fw_addr + i);
231 ast_moutdwm(ast, boot_address + i, data);
232 }
233
234 /* Init SCU */
235 ast_moutdwm(ast, 0x1e6e2000, 0x1688a8a8);
236
237 /* Launch FW */
238 ast_moutdwm(ast, 0x1e6e2104, 0x80000000 + boot_address);
239 ast_moutdwm(ast, 0x1e6e2100, 1);
240
241 /* Update Scratch */
242 data = ast_mindwm(ast, 0x1e6e2040) & 0xfffff1ff; /* D[11:9] = 100b: UEFI handling */
243 data |= 0x800;
244 ast_moutdwm(ast, 0x1e6e2040, data);
245
246 jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x99, 0xfc); /* D[1:0]: Reserved Video Buffer */
247 jreg |= 0x02;
248 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x99, jreg);
249 }
250 return true;
251}
252
253u8 ast_get_dp501_max_clk(struct drm_device *dev)
254{
255 struct ast_private *ast = dev->dev_private;
256 u32 boot_address, offset, data;
257 u8 linkcap[4], linkrate, linklanes, maxclk = 0xff;
258
259 boot_address = get_fw_base(ast);
260
261 /* validate FW version */
262 offset = 0xf000;
263 data = ast_mindwm(ast, boot_address + offset);
264 if ((data & 0xf0) != 0x10) /* version: 1x */
265 return maxclk;
266
267 /* Read Link Capability */
268 offset = 0xf014;
269 *(u32 *)linkcap = ast_mindwm(ast, boot_address + offset);
270 if (linkcap[2] == 0) {
271 linkrate = linkcap[0];
272 linklanes = linkcap[1];
273 data = (linkrate == 0x0a) ? (90 * linklanes) : (54 * linklanes);
274 if (data > 0xff)
275 data = 0xff;
276 maxclk = (u8)data;
277 }
278 return maxclk;
279}
280
281bool ast_dp501_read_edid(struct drm_device *dev, u8 *ediddata)
282{
283 struct ast_private *ast = dev->dev_private;
284 u32 i, boot_address, offset, data;
285
286 boot_address = get_fw_base(ast);
287
288 /* validate FW version */
289 offset = 0xf000;
290 data = ast_mindwm(ast, boot_address + offset);
291 if ((data & 0xf0) != 0x10)
292 return false;
293
294 /* validate PnP Monitor */
295 offset = 0xf010;
296 data = ast_mindwm(ast, boot_address + offset);
297 if (!(data & 0x01))
298 return false;
299
300 /* Read EDID */
301 offset = 0xf020;
302 for (i = 0; i < 128; i += 4) {
303 data = ast_mindwm(ast, boot_address + offset + i);
304 *(u32 *)(ediddata + i) = data;
305 }
306
307 return true;
308}
309
310static bool ast_init_dvo(struct drm_device *dev)
311{
312 struct ast_private *ast = dev->dev_private;
313 u8 jreg;
314 u32 data;
315 ast_write32(ast, 0xf004, 0x1e6e0000);
316 ast_write32(ast, 0xf000, 0x1);
317 ast_write32(ast, 0x12000, 0x1688a8a8);
318
319 jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
320 if (!(jreg & 0x80)) {
321 /* Init SCU DVO Settings */
322 data = ast_read32(ast, 0x12008);
323 /* delay phase */
324 data &= 0xfffff8ff;
325 data |= 0x00000500;
326 ast_write32(ast, 0x12008, data);
327
328 if (ast->chip == AST2300) {
329 data = ast_read32(ast, 0x12084);
330 /* multi-pins for DVO single-edge */
331 data |= 0xfffe0000;
332 ast_write32(ast, 0x12084, data);
333
334 data = ast_read32(ast, 0x12088);
335 /* multi-pins for DVO single-edge */
336 data |= 0x000fffff;
337 ast_write32(ast, 0x12088, data);
338
339 data = ast_read32(ast, 0x12090);
340 /* multi-pins for DVO single-edge */
341 data &= 0xffffffcf;
342 data |= 0x00000020;
343 ast_write32(ast, 0x12090, data);
344 } else { /* AST2400 */
345 data = ast_read32(ast, 0x12088);
346 /* multi-pins for DVO single-edge */
347 data |= 0x30000000;
348 ast_write32(ast, 0x12088, data);
349
350 data = ast_read32(ast, 0x1208c);
351 /* multi-pins for DVO single-edge */
352 data |= 0x000000cf;
353 ast_write32(ast, 0x1208c, data);
354
355 data = ast_read32(ast, 0x120a4);
356 /* multi-pins for DVO single-edge */
357 data |= 0xffff0000;
358 ast_write32(ast, 0x120a4, data);
359
360 data = ast_read32(ast, 0x120a8);
361 /* multi-pins for DVO single-edge */
362 data |= 0x0000000f;
363 ast_write32(ast, 0x120a8, data);
364
365 data = ast_read32(ast, 0x12094);
366 /* multi-pins for DVO single-edge */
367 data |= 0x00000002;
368 ast_write32(ast, 0x12094, data);
369 }
370 }
371
372 /* Force to DVO */
373 data = ast_read32(ast, 0x1202c);
374 data &= 0xfffbffff;
375 ast_write32(ast, 0x1202c, data);
376
377 /* Init VGA DVO Settings */
378 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xcf, 0x80);
379 return true;
380}
381
382void ast_init_3rdtx(struct drm_device *dev)
383{
384 struct ast_private *ast = dev->dev_private;
385 u8 jreg;
386 u32 data;
387 if (ast->chip == AST2300 || ast->chip == AST2400) {
388 jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff);
389 switch (jreg & 0x0e) {
390 case 0x04:
391 ast_init_dvo(dev);
392 break;
393 case 0x08:
394 ast_launch_m68k(dev);
395 break;
396 case 0x0c:
397 ast_init_dvo(dev);
398 break;
399 default:
400 if (ast->tx_chip_type == AST_TX_SIL164)
401 ast_init_dvo(dev);
402 else {
403 ast_write32(ast, 0x12000, 0x1688a8a8);
404 data = ast_read32(ast, 0x1202c);
405 data &= 0xfffcffff;
406 ast_write32(ast, 0, data);
407 }
408 }
409 }
410}
diff --git a/drivers/gpu/drm/ast/ast_drv.h b/drivers/gpu/drm/ast/ast_drv.h
index 9833a1b1acc1..5d6a87573c33 100644
--- a/drivers/gpu/drm/ast/ast_drv.h
+++ b/drivers/gpu/drm/ast/ast_drv.h
@@ -61,9 +61,17 @@ enum ast_chip {
61 AST2200, 61 AST2200,
62 AST2150, 62 AST2150,
63 AST2300, 63 AST2300,
64 AST2400,
64 AST1180, 65 AST1180,
65}; 66};
66 67
68enum ast_tx_chip {
69 AST_TX_NONE,
70 AST_TX_SIL164,
71 AST_TX_ITE66121,
72 AST_TX_DP501,
73};
74
67#define AST_DRAM_512Mx16 0 75#define AST_DRAM_512Mx16 0
68#define AST_DRAM_1Gx16 1 76#define AST_DRAM_1Gx16 1
69#define AST_DRAM_512Mx32 2 77#define AST_DRAM_512Mx32 2
@@ -102,6 +110,12 @@ struct ast_private {
102 * we have. */ 110 * we have. */
103 struct ttm_bo_kmap_obj cache_kmap; 111 struct ttm_bo_kmap_obj cache_kmap;
104 int next_cursor; 112 int next_cursor;
113 bool support_wide_screen;
114
115 enum ast_tx_chip tx_chip_type;
116 u8 dp501_maxclk;
117 u8 *dp501_fw_addr;
118 const struct firmware *dp501_fw; /* dp501 fw */
105}; 119};
106 120
107int ast_driver_load(struct drm_device *dev, unsigned long flags); 121int ast_driver_load(struct drm_device *dev, unsigned long flags);
@@ -368,4 +382,14 @@ int ast_mmap(struct file *filp, struct vm_area_struct *vma);
368 382
369/* ast post */ 383/* ast post */
370void ast_post_gpu(struct drm_device *dev); 384void ast_post_gpu(struct drm_device *dev);
385u32 ast_mindwm(struct ast_private *ast, u32 r);
386void ast_moutdwm(struct ast_private *ast, u32 r, u32 v);
387/* ast dp501 */
388int ast_load_dp501_microcode(struct drm_device *dev);
389void ast_set_dp501_video_output(struct drm_device *dev, u8 mode);
390bool ast_launch_m68k(struct drm_device *dev);
391bool ast_backup_fw(struct drm_device *dev, u8 *addr, u32 size);
392bool ast_dp501_read_edid(struct drm_device *dev, u8 *ediddata);
393u8 ast_get_dp501_max_clk(struct drm_device *dev);
394void ast_init_3rdtx(struct drm_device *dev);
371#endif 395#endif
diff --git a/drivers/gpu/drm/ast/ast_main.c b/drivers/gpu/drm/ast/ast_main.c
index 01bf9e730acf..a2cc6be97983 100644
--- a/drivers/gpu/drm/ast/ast_main.c
+++ b/drivers/gpu/drm/ast/ast_main.c
@@ -66,12 +66,16 @@ uint8_t ast_get_index_reg_mask(struct ast_private *ast,
66static int ast_detect_chip(struct drm_device *dev) 66static int ast_detect_chip(struct drm_device *dev)
67{ 67{
68 struct ast_private *ast = dev->dev_private; 68 struct ast_private *ast = dev->dev_private;
69 uint32_t data, jreg;
69 70
70 if (dev->pdev->device == PCI_CHIP_AST1180) { 71 if (dev->pdev->device == PCI_CHIP_AST1180) {
71 ast->chip = AST1100; 72 ast->chip = AST1100;
72 DRM_INFO("AST 1180 detected\n"); 73 DRM_INFO("AST 1180 detected\n");
73 } else { 74 } else {
74 if (dev->pdev->revision >= 0x20) { 75 if (dev->pdev->revision >= 0x30) {
76 ast->chip = AST2400;
77 DRM_INFO("AST 2400 detected\n");
78 } else if (dev->pdev->revision >= 0x20) {
75 ast->chip = AST2300; 79 ast->chip = AST2300;
76 DRM_INFO("AST 2300 detected\n"); 80 DRM_INFO("AST 2300 detected\n");
77 } else if (dev->pdev->revision >= 0x10) { 81 } else if (dev->pdev->revision >= 0x10) {
@@ -104,6 +108,59 @@ static int ast_detect_chip(struct drm_device *dev)
104 DRM_INFO("AST 2000 detected\n"); 108 DRM_INFO("AST 2000 detected\n");
105 } 109 }
106 } 110 }
111
112 switch (ast->chip) {
113 case AST1180:
114 ast->support_wide_screen = true;
115 break;
116 case AST2000:
117 ast->support_wide_screen = false;
118 break;
119 default:
120 jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
121 if (!(jreg & 0x80))
122 ast->support_wide_screen = true;
123 else if (jreg & 0x01)
124 ast->support_wide_screen = true;
125 else {
126 ast->support_wide_screen = false;
127 ast_write32(ast, 0xf004, 0x1e6e0000);
128 ast_write32(ast, 0xf000, 0x1);
129 data = ast_read32(ast, 0x1207c);
130 data &= 0x300;
131 if (ast->chip == AST2300 && data == 0x0) /* ast1300 */
132 ast->support_wide_screen = true;
133 if (ast->chip == AST2400 && data == 0x100) /* ast1400 */
134 ast->support_wide_screen = true;
135 }
136 break;
137 }
138
139 ast->tx_chip_type = AST_TX_NONE;
140 jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xff);
141 if (jreg & 0x80)
142 ast->tx_chip_type = AST_TX_SIL164;
143 if ((ast->chip == AST2300) || (ast->chip == AST2400)) {
144 jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff);
145 switch (jreg) {
146 case 0x04:
147 ast->tx_chip_type = AST_TX_SIL164;
148 break;
149 case 0x08:
150 ast->dp501_fw_addr = kzalloc(32*1024, GFP_KERNEL);
151 if (ast->dp501_fw_addr) {
152 /* backup firmware */
153 if (ast_backup_fw(dev, ast->dp501_fw_addr, 32*1024)) {
154 kfree(ast->dp501_fw_addr);
155 ast->dp501_fw_addr = NULL;
156 }
157 }
158 /* fallthrough */
159 case 0x0c:
160 ast->tx_chip_type = AST_TX_DP501;
161 }
162 }
163
107 return 0; 164 return 0;
108} 165}
109 166
@@ -129,7 +186,7 @@ static int ast_get_dram_info(struct drm_device *dev)
129 else 186 else
130 ast->dram_bus_width = 32; 187 ast->dram_bus_width = 32;
131 188
132 if (ast->chip == AST2300) { 189 if (ast->chip == AST2300 || ast->chip == AST2400) {
133 switch (data & 0x03) { 190 switch (data & 0x03) {
134 case 0: 191 case 0:
135 ast->dram_type = AST_DRAM_512Mx16; 192 ast->dram_type = AST_DRAM_512Mx16;
@@ -257,17 +314,32 @@ static u32 ast_get_vram_info(struct drm_device *dev)
257{ 314{
258 struct ast_private *ast = dev->dev_private; 315 struct ast_private *ast = dev->dev_private;
259 u8 jreg; 316 u8 jreg;
260 317 u32 vram_size;
261 ast_open_key(ast); 318 ast_open_key(ast);
262 319
320 vram_size = AST_VIDMEM_DEFAULT_SIZE;
263 jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xaa, 0xff); 321 jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xaa, 0xff);
264 switch (jreg & 3) { 322 switch (jreg & 3) {
265 case 0: return AST_VIDMEM_SIZE_8M; 323 case 0: vram_size = AST_VIDMEM_SIZE_8M; break;
266 case 1: return AST_VIDMEM_SIZE_16M; 324 case 1: vram_size = AST_VIDMEM_SIZE_16M; break;
267 case 2: return AST_VIDMEM_SIZE_32M; 325 case 2: vram_size = AST_VIDMEM_SIZE_32M; break;
268 case 3: return AST_VIDMEM_SIZE_64M; 326 case 3: vram_size = AST_VIDMEM_SIZE_64M; break;
269 } 327 }
270 return AST_VIDMEM_DEFAULT_SIZE; 328
329 jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x99, 0xff);
330 switch (jreg & 0x03) {
331 case 1:
332 vram_size -= 0x100000;
333 break;
334 case 2:
335 vram_size -= 0x200000;
336 break;
337 case 3:
338 vram_size -= 0x400000;
339 break;
340 }
341
342 return vram_size;
271} 343}
272 344
273int ast_driver_load(struct drm_device *dev, unsigned long flags) 345int ast_driver_load(struct drm_device *dev, unsigned long flags)
@@ -316,6 +388,7 @@ int ast_driver_load(struct drm_device *dev, unsigned long flags)
316 if (ast->chip == AST2100 || 388 if (ast->chip == AST2100 ||
317 ast->chip == AST2200 || 389 ast->chip == AST2200 ||
318 ast->chip == AST2300 || 390 ast->chip == AST2300 ||
391 ast->chip == AST2400 ||
319 ast->chip == AST1180) { 392 ast->chip == AST1180) {
320 dev->mode_config.max_width = 1920; 393 dev->mode_config.max_width = 1920;
321 dev->mode_config.max_height = 2048; 394 dev->mode_config.max_height = 2048;
@@ -343,6 +416,7 @@ int ast_driver_unload(struct drm_device *dev)
343{ 416{
344 struct ast_private *ast = dev->dev_private; 417 struct ast_private *ast = dev->dev_private;
345 418
419 kfree(ast->dp501_fw_addr);
346 ast_mode_fini(dev); 420 ast_mode_fini(dev);
347 ast_fbdev_fini(dev); 421 ast_fbdev_fini(dev);
348 drm_mode_config_cleanup(dev); 422 drm_mode_config_cleanup(dev);
diff --git a/drivers/gpu/drm/ast/ast_mode.c b/drivers/gpu/drm/ast/ast_mode.c
index e599d64a2620..114aee941d46 100644
--- a/drivers/gpu/drm/ast/ast_mode.c
+++ b/drivers/gpu/drm/ast/ast_mode.c
@@ -115,11 +115,17 @@ static bool ast_get_vbios_mode_info(struct drm_crtc *crtc, struct drm_display_mo
115 else 115 else
116 vbios_mode->enh_table = &res_1280x1024[refresh_rate_index]; 116 vbios_mode->enh_table = &res_1280x1024[refresh_rate_index];
117 break; 117 break;
118 case 1360:
119 vbios_mode->enh_table = &res_1360x768[refresh_rate_index];
120 break;
118 case 1440: 121 case 1440:
119 vbios_mode->enh_table = &res_1440x900[refresh_rate_index]; 122 vbios_mode->enh_table = &res_1440x900[refresh_rate_index];
120 break; 123 break;
121 case 1600: 124 case 1600:
122 vbios_mode->enh_table = &res_1600x1200[refresh_rate_index]; 125 if (crtc->mode.crtc_vdisplay == 900)
126 vbios_mode->enh_table = &res_1600x900[refresh_rate_index];
127 else
128 vbios_mode->enh_table = &res_1600x1200[refresh_rate_index];
123 break; 129 break;
124 case 1680: 130 case 1680:
125 vbios_mode->enh_table = &res_1680x1050[refresh_rate_index]; 131 vbios_mode->enh_table = &res_1680x1050[refresh_rate_index];
@@ -175,14 +181,17 @@ static bool ast_get_vbios_mode_info(struct drm_crtc *crtc, struct drm_display_mo
175 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8d, refresh_rate_index & 0xff); 181 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8d, refresh_rate_index & 0xff);
176 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8e, mode_id & 0xff); 182 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8e, mode_id & 0xff);
177 183
178 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0xa8); 184 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0x00);
179 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x92, crtc->primary->fb->bits_per_pixel); 185 if (vbios_mode->enh_table->flags & NewModeInfo) {
180 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x93, adjusted_mode->clock / 1000); 186 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0xa8);
181 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x94, adjusted_mode->crtc_hdisplay); 187 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x92, crtc->primary->fb->bits_per_pixel);
182 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x95, adjusted_mode->crtc_hdisplay >> 8); 188 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x93, adjusted_mode->clock / 1000);
189 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x94, adjusted_mode->crtc_hdisplay);
190 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x95, adjusted_mode->crtc_hdisplay >> 8);
183 191
184 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x96, adjusted_mode->crtc_vdisplay); 192 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x96, adjusted_mode->crtc_vdisplay);
185 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x97, adjusted_mode->crtc_vdisplay >> 8); 193 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x97, adjusted_mode->crtc_vdisplay >> 8);
194 }
186 } 195 }
187 196
188 return true; 197 return true;
@@ -389,7 +398,7 @@ static void ast_set_ext_reg(struct drm_crtc *crtc, struct drm_display_mode *mode
389 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa8, 0xfd, jregA8); 398 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa8, 0xfd, jregA8);
390 399
391 /* Set Threshold */ 400 /* Set Threshold */
392 if (ast->chip == AST2300) { 401 if (ast->chip == AST2300 || ast->chip == AST2400) {
393 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x78); 402 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x78);
394 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x60); 403 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x60);
395 } else if (ast->chip == AST2100 || 404 } else if (ast->chip == AST2100 ||
@@ -451,9 +460,13 @@ static void ast_crtc_dpms(struct drm_crtc *crtc, int mode)
451 case DRM_MODE_DPMS_STANDBY: 460 case DRM_MODE_DPMS_STANDBY:
452 case DRM_MODE_DPMS_SUSPEND: 461 case DRM_MODE_DPMS_SUSPEND:
453 ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x1, 0xdf, 0); 462 ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x1, 0xdf, 0);
463 if (ast->tx_chip_type == AST_TX_DP501)
464 ast_set_dp501_video_output(crtc->dev, 1);
454 ast_crtc_load_lut(crtc); 465 ast_crtc_load_lut(crtc);
455 break; 466 break;
456 case DRM_MODE_DPMS_OFF: 467 case DRM_MODE_DPMS_OFF:
468 if (ast->tx_chip_type == AST_TX_DP501)
469 ast_set_dp501_video_output(crtc->dev, 0);
457 ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x1, 0xdf, 0x20); 470 ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x1, 0xdf, 0x20);
458 break; 471 break;
459 } 472 }
@@ -729,10 +742,24 @@ static int ast_encoder_init(struct drm_device *dev)
729static int ast_get_modes(struct drm_connector *connector) 742static int ast_get_modes(struct drm_connector *connector)
730{ 743{
731 struct ast_connector *ast_connector = to_ast_connector(connector); 744 struct ast_connector *ast_connector = to_ast_connector(connector);
745 struct ast_private *ast = connector->dev->dev_private;
732 struct edid *edid; 746 struct edid *edid;
733 int ret; 747 int ret;
734 748 bool flags = false;
735 edid = drm_get_edid(connector, &ast_connector->i2c->adapter); 749 if (ast->tx_chip_type == AST_TX_DP501) {
750 ast->dp501_maxclk = 0xff;
751 edid = kmalloc(128, GFP_KERNEL);
752 if (!edid)
753 return -ENOMEM;
754
755 flags = ast_dp501_read_edid(connector->dev, (u8 *)edid);
756 if (flags)
757 ast->dp501_maxclk = ast_get_dp501_max_clk(connector->dev);
758 else
759 kfree(edid);
760 }
761 if (!flags)
762 edid = drm_get_edid(connector, &ast_connector->i2c->adapter);
736 if (edid) { 763 if (edid) {
737 drm_mode_connector_update_edid_property(&ast_connector->base, edid); 764 drm_mode_connector_update_edid_property(&ast_connector->base, edid);
738 ret = drm_add_edid_modes(connector, edid); 765 ret = drm_add_edid_modes(connector, edid);
@@ -743,6 +770,61 @@ static int ast_get_modes(struct drm_connector *connector)
743 return 0; 770 return 0;
744} 771}
745 772
773static int ast_mode_valid(struct drm_connector *connector,
774 struct drm_display_mode *mode)
775{
776 struct ast_private *ast = connector->dev->dev_private;
777 int flags = MODE_NOMODE;
778 uint32_t jtemp;
779
780 if (ast->support_wide_screen) {
781 if ((mode->hdisplay == 1680) && (mode->vdisplay == 1050))
782 return MODE_OK;
783 if ((mode->hdisplay == 1280) && (mode->vdisplay == 800))
784 return MODE_OK;
785 if ((mode->hdisplay == 1440) && (mode->vdisplay == 900))
786 return MODE_OK;
787 if ((mode->hdisplay == 1360) && (mode->vdisplay == 768))
788 return MODE_OK;
789 if ((mode->hdisplay == 1600) && (mode->vdisplay == 900))
790 return MODE_OK;
791
792 if ((ast->chip == AST2100) || (ast->chip == AST2200) || (ast->chip == AST2300) || (ast->chip == AST2400) || (ast->chip == AST1180)) {
793 if ((mode->hdisplay == 1920) && (mode->vdisplay == 1080))
794 return MODE_OK;
795
796 if ((mode->hdisplay == 1920) && (mode->vdisplay == 1200)) {
797 jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff);
798 if (jtemp & 0x01)
799 return MODE_NOMODE;
800 else
801 return MODE_OK;
802 }
803 }
804 }
805 switch (mode->hdisplay) {
806 case 640:
807 if (mode->vdisplay == 480) flags = MODE_OK;
808 break;
809 case 800:
810 if (mode->vdisplay == 600) flags = MODE_OK;
811 break;
812 case 1024:
813 if (mode->vdisplay == 768) flags = MODE_OK;
814 break;
815 case 1280:
816 if (mode->vdisplay == 1024) flags = MODE_OK;
817 break;
818 case 1600:
819 if (mode->vdisplay == 1200) flags = MODE_OK;
820 break;
821 default:
822 return flags;
823 }
824
825 return flags;
826}
827
746static void ast_connector_destroy(struct drm_connector *connector) 828static void ast_connector_destroy(struct drm_connector *connector)
747{ 829{
748 struct ast_connector *ast_connector = to_ast_connector(connector); 830 struct ast_connector *ast_connector = to_ast_connector(connector);
@@ -759,6 +841,7 @@ ast_connector_detect(struct drm_connector *connector, bool force)
759} 841}
760 842
761static const struct drm_connector_helper_funcs ast_connector_helper_funcs = { 843static const struct drm_connector_helper_funcs ast_connector_helper_funcs = {
844 .mode_valid = ast_mode_valid,
762 .get_modes = ast_get_modes, 845 .get_modes = ast_get_modes,
763 .best_encoder = ast_best_single_encoder, 846 .best_encoder = ast_best_single_encoder,
764}; 847};
diff --git a/drivers/gpu/drm/ast/ast_post.c b/drivers/gpu/drm/ast/ast_post.c
index 635f6ffc27c2..4e5ea3898e72 100644
--- a/drivers/gpu/drm/ast/ast_post.c
+++ b/drivers/gpu/drm/ast/ast_post.c
@@ -78,7 +78,7 @@ ast_set_def_ext_reg(struct drm_device *dev)
78 for (i = 0x81; i <= 0x8f; i++) 78 for (i = 0x81; i <= 0x8f; i++)
79 ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, 0x00); 79 ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, 0x00);
80 80
81 if (ast->chip == AST2300) { 81 if (ast->chip == AST2300 || ast->chip == AST2400) {
82 if (dev->pdev->revision >= 0x20) 82 if (dev->pdev->revision >= 0x20)
83 ext_reg_info = extreginfo_ast2300; 83 ext_reg_info = extreginfo_ast2300;
84 else 84 else
@@ -102,23 +102,32 @@ ast_set_def_ext_reg(struct drm_device *dev)
102 102
103 /* Enable RAMDAC for A1 */ 103 /* Enable RAMDAC for A1 */
104 reg = 0x04; 104 reg = 0x04;
105 if (ast->chip == AST2300) 105 if (ast->chip == AST2300 || ast->chip == AST2400)
106 reg |= 0x20; 106 reg |= 0x20;
107 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0xff, reg); 107 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0xff, reg);
108} 108}
109 109
110static inline u32 mindwm(struct ast_private *ast, u32 r) 110u32 ast_mindwm(struct ast_private *ast, u32 r)
111{ 111{
112 uint32_t data;
113
112 ast_write32(ast, 0xf004, r & 0xffff0000); 114 ast_write32(ast, 0xf004, r & 0xffff0000);
113 ast_write32(ast, 0xf000, 0x1); 115 ast_write32(ast, 0xf000, 0x1);
114 116
117 do {
118 data = ast_read32(ast, 0xf004) & 0xffff0000;
119 } while (data != (r & 0xffff0000));
115 return ast_read32(ast, 0x10000 + (r & 0x0000ffff)); 120 return ast_read32(ast, 0x10000 + (r & 0x0000ffff));
116} 121}
117 122
118static inline void moutdwm(struct ast_private *ast, u32 r, u32 v) 123void ast_moutdwm(struct ast_private *ast, u32 r, u32 v)
119{ 124{
125 uint32_t data;
120 ast_write32(ast, 0xf004, r & 0xffff0000); 126 ast_write32(ast, 0xf004, r & 0xffff0000);
121 ast_write32(ast, 0xf000, 0x1); 127 ast_write32(ast, 0xf000, 0x1);
128 do {
129 data = ast_read32(ast, 0xf004) & 0xffff0000;
130 } while (data != (r & 0xffff0000));
122 ast_write32(ast, 0x10000 + (r & 0x0000ffff), v); 131 ast_write32(ast, 0x10000 + (r & 0x0000ffff), v);
123} 132}
124 133
@@ -154,28 +163,28 @@ static u32 mmctestburst2_ast2150(struct ast_private *ast, u32 datagen)
154{ 163{
155 u32 data, timeout; 164 u32 data, timeout;
156 165
157 moutdwm(ast, 0x1e6e0070, 0x00000000); 166 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
158 moutdwm(ast, 0x1e6e0070, 0x00000001 | (datagen << 3)); 167 ast_moutdwm(ast, 0x1e6e0070, 0x00000001 | (datagen << 3));
159 timeout = 0; 168 timeout = 0;
160 do { 169 do {
161 data = mindwm(ast, 0x1e6e0070) & 0x40; 170 data = ast_mindwm(ast, 0x1e6e0070) & 0x40;
162 if (++timeout > TIMEOUT_AST2150) { 171 if (++timeout > TIMEOUT_AST2150) {
163 moutdwm(ast, 0x1e6e0070, 0x00000000); 172 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
164 return 0xffffffff; 173 return 0xffffffff;
165 } 174 }
166 } while (!data); 175 } while (!data);
167 moutdwm(ast, 0x1e6e0070, 0x00000000); 176 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
168 moutdwm(ast, 0x1e6e0070, 0x00000003 | (datagen << 3)); 177 ast_moutdwm(ast, 0x1e6e0070, 0x00000003 | (datagen << 3));
169 timeout = 0; 178 timeout = 0;
170 do { 179 do {
171 data = mindwm(ast, 0x1e6e0070) & 0x40; 180 data = ast_mindwm(ast, 0x1e6e0070) & 0x40;
172 if (++timeout > TIMEOUT_AST2150) { 181 if (++timeout > TIMEOUT_AST2150) {
173 moutdwm(ast, 0x1e6e0070, 0x00000000); 182 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
174 return 0xffffffff; 183 return 0xffffffff;
175 } 184 }
176 } while (!data); 185 } while (!data);
177 data = (mindwm(ast, 0x1e6e0070) & 0x80) >> 7; 186 data = (ast_mindwm(ast, 0x1e6e0070) & 0x80) >> 7;
178 moutdwm(ast, 0x1e6e0070, 0x00000000); 187 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
179 return data; 188 return data;
180} 189}
181 190
@@ -184,18 +193,18 @@ static u32 mmctestsingle2_ast2150(struct ast_private *ast, u32 datagen)
184{ 193{
185 u32 data, timeout; 194 u32 data, timeout;
186 195
187 moutdwm(ast, 0x1e6e0070, 0x00000000); 196 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
188 moutdwm(ast, 0x1e6e0070, 0x00000005 | (datagen << 3)); 197 ast_moutdwm(ast, 0x1e6e0070, 0x00000005 | (datagen << 3));
189 timeout = 0; 198 timeout = 0;
190 do { 199 do {
191 data = mindwm(ast, 0x1e6e0070) & 0x40; 200 data = ast_mindwm(ast, 0x1e6e0070) & 0x40;
192 if (++timeout > TIMEOUT_AST2150) { 201 if (++timeout > TIMEOUT_AST2150) {
193 moutdwm(ast, 0x1e6e0070, 0x00000000); 202 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
194 return 0xffffffff; 203 return 0xffffffff;
195 } 204 }
196 } while (!data); 205 } while (!data);
197 data = (mindwm(ast, 0x1e6e0070) & 0x80) >> 7; 206 data = (ast_mindwm(ast, 0x1e6e0070) & 0x80) >> 7;
198 moutdwm(ast, 0x1e6e0070, 0x00000000); 207 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
199 return data; 208 return data;
200} 209}
201#endif 210#endif
@@ -215,7 +224,7 @@ static int cbrscan_ast2150(struct ast_private *ast, int busw)
215 u32 patcnt, loop; 224 u32 patcnt, loop;
216 225
217 for (patcnt = 0; patcnt < CBR_PATNUM_AST2150; patcnt++) { 226 for (patcnt = 0; patcnt < CBR_PATNUM_AST2150; patcnt++) {
218 moutdwm(ast, 0x1e6e007c, pattern_AST2150[patcnt]); 227 ast_moutdwm(ast, 0x1e6e007c, pattern_AST2150[patcnt]);
219 for (loop = 0; loop < CBR_PASSNUM_AST2150; loop++) { 228 for (loop = 0; loop < CBR_PASSNUM_AST2150; loop++) {
220 if (cbrtest_ast2150(ast)) 229 if (cbrtest_ast2150(ast))
221 break; 230 break;
@@ -237,7 +246,7 @@ cbr_start:
237 passcnt = 0; 246 passcnt = 0;
238 247
239 for (dlli = 0; dlli < 100; dlli++) { 248 for (dlli = 0; dlli < 100; dlli++) {
240 moutdwm(ast, 0x1e6e0068, dlli | (dlli << 8) | (dlli << 16) | (dlli << 24)); 249 ast_moutdwm(ast, 0x1e6e0068, dlli | (dlli << 8) | (dlli << 16) | (dlli << 24));
241 data = cbrscan_ast2150(ast, busw); 250 data = cbrscan_ast2150(ast, busw);
242 if (data != 0) { 251 if (data != 0) {
243 if (data & 0x1) { 252 if (data & 0x1) {
@@ -254,7 +263,7 @@ cbr_start:
254 goto cbr_start; 263 goto cbr_start;
255 264
256 dlli = dll_min[0] + (((dll_max[0] - dll_min[0]) * 7) >> 4); 265 dlli = dll_min[0] + (((dll_max[0] - dll_min[0]) * 7) >> 4);
257 moutdwm(ast, 0x1e6e0068, dlli | (dlli << 8) | (dlli << 16) | (dlli << 24)); 266 ast_moutdwm(ast, 0x1e6e0068, dlli | (dlli << 8) | (dlli << 16) | (dlli << 24));
258} 267}
259 268
260 269
@@ -365,10 +374,12 @@ void ast_post_gpu(struct drm_device *dev)
365 ast_open_key(ast); 374 ast_open_key(ast);
366 ast_set_def_ext_reg(dev); 375 ast_set_def_ext_reg(dev);
367 376
368 if (ast->chip == AST2300) 377 if (ast->chip == AST2300 || ast->chip == AST2400)
369 ast_init_dram_2300(dev); 378 ast_init_dram_2300(dev);
370 else 379 else
371 ast_init_dram_reg(dev); 380 ast_init_dram_reg(dev);
381
382 ast_init_3rdtx(dev);
372} 383}
373 384
374/* AST 2300 DRAM settings */ 385/* AST 2300 DRAM settings */
@@ -403,6 +414,7 @@ struct ast2300_dram_param {
403/* 414/*
404 * DQSI DLL CBR Setting 415 * DQSI DLL CBR Setting
405 */ 416 */
417#define CBR_SIZE0 ((1 << 10) - 1)
406#define CBR_SIZE1 ((4 << 10) - 1) 418#define CBR_SIZE1 ((4 << 10) - 1)
407#define CBR_SIZE2 ((64 << 10) - 1) 419#define CBR_SIZE2 ((64 << 10) - 1)
408#define CBR_PASSNUM 5 420#define CBR_PASSNUM 5
@@ -423,88 +435,84 @@ static const u32 pattern[8] = {
423 0x7C61D253 435 0x7C61D253
424}; 436};
425 437
426#if 0 /* unused in DDX, included for completeness */
427static int mmc_test_burst(struct ast_private *ast, u32 datagen) 438static int mmc_test_burst(struct ast_private *ast, u32 datagen)
428{ 439{
429 u32 data, timeout; 440 u32 data, timeout;
430 441
431 moutdwm(ast, 0x1e6e0070, 0x00000000); 442 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
432 moutdwm(ast, 0x1e6e0070, 0x000000c1 | (datagen << 3)); 443 ast_moutdwm(ast, 0x1e6e0070, 0x000000c1 | (datagen << 3));
433 timeout = 0; 444 timeout = 0;
434 do { 445 do {
435 data = mindwm(ast, 0x1e6e0070) & 0x3000; 446 data = ast_mindwm(ast, 0x1e6e0070) & 0x3000;
436 if (data & 0x2000) { 447 if (data & 0x2000) {
437 return 0; 448 return 0;
438 } 449 }
439 if (++timeout > TIMEOUT) { 450 if (++timeout > TIMEOUT) {
440 moutdwm(ast, 0x1e6e0070, 0x00000000); 451 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
441 return 0; 452 return 0;
442 } 453 }
443 } while (!data); 454 } while (!data);
444 moutdwm(ast, 0x1e6e0070, 0x00000000); 455 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
445 return 1; 456 return 1;
446} 457}
447#endif
448 458
449static int mmc_test_burst2(struct ast_private *ast, u32 datagen) 459static int mmc_test_burst2(struct ast_private *ast, u32 datagen)
450{ 460{
451 u32 data, timeout; 461 u32 data, timeout;
452 462
453 moutdwm(ast, 0x1e6e0070, 0x00000000); 463 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
454 moutdwm(ast, 0x1e6e0070, 0x00000041 | (datagen << 3)); 464 ast_moutdwm(ast, 0x1e6e0070, 0x00000041 | (datagen << 3));
455 timeout = 0; 465 timeout = 0;
456 do { 466 do {
457 data = mindwm(ast, 0x1e6e0070) & 0x1000; 467 data = ast_mindwm(ast, 0x1e6e0070) & 0x1000;
458 if (++timeout > TIMEOUT) { 468 if (++timeout > TIMEOUT) {
459 moutdwm(ast, 0x1e6e0070, 0x0); 469 ast_moutdwm(ast, 0x1e6e0070, 0x0);
460 return -1; 470 return -1;
461 } 471 }
462 } while (!data); 472 } while (!data);
463 data = mindwm(ast, 0x1e6e0078); 473 data = ast_mindwm(ast, 0x1e6e0078);
464 data = (data | (data >> 16)) & 0xffff; 474 data = (data | (data >> 16)) & 0xffff;
465 moutdwm(ast, 0x1e6e0070, 0x0); 475 ast_moutdwm(ast, 0x1e6e0070, 0x0);
466 return data; 476 return data;
467} 477}
468 478
469#if 0 /* Unused in DDX here for completeness */
470static int mmc_test_single(struct ast_private *ast, u32 datagen) 479static int mmc_test_single(struct ast_private *ast, u32 datagen)
471{ 480{
472 u32 data, timeout; 481 u32 data, timeout;
473 482
474 moutdwm(ast, 0x1e6e0070, 0x00000000); 483 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
475 moutdwm(ast, 0x1e6e0070, 0x000000c5 | (datagen << 3)); 484 ast_moutdwm(ast, 0x1e6e0070, 0x000000c5 | (datagen << 3));
476 timeout = 0; 485 timeout = 0;
477 do { 486 do {
478 data = mindwm(ast, 0x1e6e0070) & 0x3000; 487 data = ast_mindwm(ast, 0x1e6e0070) & 0x3000;
479 if (data & 0x2000) 488 if (data & 0x2000)
480 return 0; 489 return 0;
481 if (++timeout > TIMEOUT) { 490 if (++timeout > TIMEOUT) {
482 moutdwm(ast, 0x1e6e0070, 0x0); 491 ast_moutdwm(ast, 0x1e6e0070, 0x0);
483 return 0; 492 return 0;
484 } 493 }
485 } while (!data); 494 } while (!data);
486 moutdwm(ast, 0x1e6e0070, 0x0); 495 ast_moutdwm(ast, 0x1e6e0070, 0x0);
487 return 1; 496 return 1;
488} 497}
489#endif
490 498
491static int mmc_test_single2(struct ast_private *ast, u32 datagen) 499static int mmc_test_single2(struct ast_private *ast, u32 datagen)
492{ 500{
493 u32 data, timeout; 501 u32 data, timeout;
494 502
495 moutdwm(ast, 0x1e6e0070, 0x00000000); 503 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
496 moutdwm(ast, 0x1e6e0070, 0x00000005 | (datagen << 3)); 504 ast_moutdwm(ast, 0x1e6e0070, 0x00000005 | (datagen << 3));
497 timeout = 0; 505 timeout = 0;
498 do { 506 do {
499 data = mindwm(ast, 0x1e6e0070) & 0x1000; 507 data = ast_mindwm(ast, 0x1e6e0070) & 0x1000;
500 if (++timeout > TIMEOUT) { 508 if (++timeout > TIMEOUT) {
501 moutdwm(ast, 0x1e6e0070, 0x0); 509 ast_moutdwm(ast, 0x1e6e0070, 0x0);
502 return -1; 510 return -1;
503 } 511 }
504 } while (!data); 512 } while (!data);
505 data = mindwm(ast, 0x1e6e0078); 513 data = ast_mindwm(ast, 0x1e6e0078);
506 data = (data | (data >> 16)) & 0xffff; 514 data = (data | (data >> 16)) & 0xffff;
507 moutdwm(ast, 0x1e6e0070, 0x0); 515 ast_moutdwm(ast, 0x1e6e0070, 0x0);
508 return data; 516 return data;
509} 517}
510 518
@@ -533,7 +541,7 @@ static int cbr_scan(struct ast_private *ast)
533 541
534 data2 = 3; 542 data2 = 3;
535 for (patcnt = 0; patcnt < CBR_PATNUM; patcnt++) { 543 for (patcnt = 0; patcnt < CBR_PATNUM; patcnt++) {
536 moutdwm(ast, 0x1e6e007c, pattern[patcnt]); 544 ast_moutdwm(ast, 0x1e6e007c, pattern[patcnt]);
537 for (loop = 0; loop < CBR_PASSNUM2; loop++) { 545 for (loop = 0; loop < CBR_PASSNUM2; loop++) {
538 if ((data = cbr_test(ast)) != 0) { 546 if ((data = cbr_test(ast)) != 0) {
539 data2 &= data; 547 data2 &= data;
@@ -568,7 +576,7 @@ static u32 cbr_scan2(struct ast_private *ast)
568 576
569 data2 = 0xffff; 577 data2 = 0xffff;
570 for (patcnt = 0; patcnt < CBR_PATNUM; patcnt++) { 578 for (patcnt = 0; patcnt < CBR_PATNUM; patcnt++) {
571 moutdwm(ast, 0x1e6e007c, pattern[patcnt]); 579 ast_moutdwm(ast, 0x1e6e007c, pattern[patcnt]);
572 for (loop = 0; loop < CBR_PASSNUM2; loop++) { 580 for (loop = 0; loop < CBR_PASSNUM2; loop++) {
573 if ((data = cbr_test2(ast)) != 0) { 581 if ((data = cbr_test2(ast)) != 0) {
574 data2 &= data; 582 data2 &= data;
@@ -583,106 +591,35 @@ static u32 cbr_scan2(struct ast_private *ast)
583 return data2; 591 return data2;
584} 592}
585 593
586#if 0 /* unused in DDX - added for completeness */ 594static u32 cbr_test3(struct ast_private *ast)
587static void finetuneDQI(struct ast_private *ast, struct ast2300_dram_param *param)
588{ 595{
589 u32 gold_sadj[2], dllmin[16], dllmax[16], dlli, data, cnt, mask, passcnt; 596 if (!mmc_test_burst(ast, 0))
590 597 return 0;
591 gold_sadj[0] = (mindwm(ast, 0x1E6E0024) >> 16) & 0xffff; 598 if (!mmc_test_single(ast, 0))
592 gold_sadj[1] = gold_sadj[0] >> 8; 599 return 0;
593 gold_sadj[0] = gold_sadj[0] & 0xff; 600 return 1;
594 gold_sadj[0] = (gold_sadj[0] + gold_sadj[1]) >> 1; 601}
595 gold_sadj[1] = gold_sadj[0];
596
597 for (cnt = 0; cnt < 16; cnt++) {
598 dllmin[cnt] = 0xff;
599 dllmax[cnt] = 0x0;
600 }
601 passcnt = 0;
602 for (dlli = 0; dlli < 76; dlli++) {
603 moutdwm(ast, 0x1E6E0068, 0x00001400 | (dlli << 16) | (dlli << 24));
604 /* Wait DQSI latch phase calibration */
605 moutdwm(ast, 0x1E6E0074, 0x00000010);
606 moutdwm(ast, 0x1E6E0070, 0x00000003);
607 do {
608 data = mindwm(ast, 0x1E6E0070);
609 } while (!(data & 0x00001000));
610 moutdwm(ast, 0x1E6E0070, 0x00000000);
611 602
612 moutdwm(ast, 0x1E6E0074, CBR_SIZE1); 603static u32 cbr_scan3(struct ast_private *ast)
613 data = cbr_scan2(ast); 604{
614 if (data != 0) { 605 u32 patcnt, loop;
615 mask = 0x00010001;
616 for (cnt = 0; cnt < 16; cnt++) {
617 if (data & mask) {
618 if (dllmin[cnt] > dlli) {
619 dllmin[cnt] = dlli;
620 }
621 if (dllmax[cnt] < dlli) {
622 dllmax[cnt] = dlli;
623 }
624 }
625 mask <<= 1;
626 }
627 passcnt++;
628 } else if (passcnt >= CBR_THRESHOLD) {
629 break;
630 }
631 }
632 data = 0;
633 for (cnt = 0; cnt < 8; cnt++) {
634 data >>= 3;
635 if ((dllmax[cnt] > dllmin[cnt]) && ((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD)) {
636 dlli = (dllmin[cnt] + dllmax[cnt]) >> 1;
637 if (gold_sadj[0] >= dlli) {
638 dlli = (gold_sadj[0] - dlli) >> 1;
639 if (dlli > 3) {
640 dlli = 3;
641 }
642 } else {
643 dlli = (dlli - gold_sadj[0]) >> 1;
644 if (dlli > 4) {
645 dlli = 4;
646 }
647 dlli = (8 - dlli) & 0x7;
648 }
649 data |= dlli << 21;
650 }
651 }
652 moutdwm(ast, 0x1E6E0080, data);
653 606
654 data = 0; 607 for (patcnt = 0; patcnt < CBR_PATNUM; patcnt++) {
655 for (cnt = 8; cnt < 16; cnt++) { 608 ast_moutdwm(ast, 0x1e6e007c, pattern[patcnt]);
656 data >>= 3; 609 for (loop = 0; loop < 2; loop++) {
657 if ((dllmax[cnt] > dllmin[cnt]) && ((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD)) { 610 if (cbr_test3(ast))
658 dlli = (dllmin[cnt] + dllmax[cnt]) >> 1; 611 break;
659 if (gold_sadj[1] >= dlli) {
660 dlli = (gold_sadj[1] - dlli) >> 1;
661 if (dlli > 3) {
662 dlli = 3;
663 } else {
664 dlli = (dlli - 1) & 0x7;
665 }
666 } else {
667 dlli = (dlli - gold_sadj[1]) >> 1;
668 dlli += 1;
669 if (dlli > 4) {
670 dlli = 4;
671 }
672 dlli = (8 - dlli) & 0x7;
673 }
674 data |= dlli << 21;
675 } 612 }
613 if (loop == 2)
614 return 0;
676 } 615 }
677 moutdwm(ast, 0x1E6E0084, data); 616 return 1;
678 617}
679} /* finetuneDQI */
680#endif
681 618
682static void finetuneDQI_L(struct ast_private *ast, struct ast2300_dram_param *param) 619static bool finetuneDQI_L(struct ast_private *ast, struct ast2300_dram_param *param)
683{ 620{
684 u32 gold_sadj[2], dllmin[16], dllmax[16], dlli, data, cnt, mask, passcnt; 621 u32 gold_sadj[2], dllmin[16], dllmax[16], dlli, data, cnt, mask, passcnt, retry = 0;
685 622 bool status = false;
686FINETUNE_START: 623FINETUNE_START:
687 for (cnt = 0; cnt < 16; cnt++) { 624 for (cnt = 0; cnt < 16; cnt++) {
688 dllmin[cnt] = 0xff; 625 dllmin[cnt] = 0xff;
@@ -690,16 +627,8 @@ FINETUNE_START:
690 } 627 }
691 passcnt = 0; 628 passcnt = 0;
692 for (dlli = 0; dlli < 76; dlli++) { 629 for (dlli = 0; dlli < 76; dlli++) {
693 moutdwm(ast, 0x1E6E0068, 0x00001400 | (dlli << 16) | (dlli << 24)); 630 ast_moutdwm(ast, 0x1E6E0068, 0x00001400 | (dlli << 16) | (dlli << 24));
694 /* Wait DQSI latch phase calibration */ 631 ast_moutdwm(ast, 0x1E6E0074, CBR_SIZE1);
695 moutdwm(ast, 0x1E6E0074, 0x00000010);
696 moutdwm(ast, 0x1E6E0070, 0x00000003);
697 do {
698 data = mindwm(ast, 0x1E6E0070);
699 } while (!(data & 0x00001000));
700 moutdwm(ast, 0x1E6E0070, 0x00000000);
701
702 moutdwm(ast, 0x1E6E0074, CBR_SIZE1);
703 data = cbr_scan2(ast); 632 data = cbr_scan2(ast);
704 if (data != 0) { 633 if (data != 0) {
705 mask = 0x00010001; 634 mask = 0x00010001;
@@ -727,9 +656,13 @@ FINETUNE_START:
727 passcnt++; 656 passcnt++;
728 } 657 }
729 } 658 }
659 if (retry++ > 10)
660 goto FINETUNE_DONE;
730 if (passcnt != 16) { 661 if (passcnt != 16) {
731 goto FINETUNE_START; 662 goto FINETUNE_START;
732 } 663 }
664 status = true;
665FINETUNE_DONE:
733 gold_sadj[0] = gold_sadj[0] >> 4; 666 gold_sadj[0] = gold_sadj[0] >> 4;
734 gold_sadj[1] = gold_sadj[0]; 667 gold_sadj[1] = gold_sadj[0];
735 668
@@ -753,7 +686,7 @@ FINETUNE_START:
753 data |= dlli << 21; 686 data |= dlli << 21;
754 } 687 }
755 } 688 }
756 moutdwm(ast, 0x1E6E0080, data); 689 ast_moutdwm(ast, 0x1E6E0080, data);
757 690
758 data = 0; 691 data = 0;
759 for (cnt = 8; cnt < 16; cnt++) { 692 for (cnt = 8; cnt < 16; cnt++) {
@@ -778,162 +711,116 @@ FINETUNE_START:
778 data |= dlli << 21; 711 data |= dlli << 21;
779 } 712 }
780 } 713 }
781 moutdwm(ast, 0x1E6E0084, data); 714 ast_moutdwm(ast, 0x1E6E0084, data);
782 715 return status;
783} /* finetuneDQI_L */ 716} /* finetuneDQI_L */
784 717
785static void finetuneDQI_L2(struct ast_private *ast, struct ast2300_dram_param *param) 718static void finetuneDQSI(struct ast_private *ast)
786{ 719{
787 u32 gold_sadj[2], dllmin[16], dllmax[16], dlli, data, cnt, mask, passcnt, data2; 720 u32 dlli, dqsip, dqidly;
721 u32 reg_mcr18, reg_mcr0c, passcnt[2], diff;
722 u32 g_dqidly, g_dqsip, g_margin, g_side;
723 u16 pass[32][2][2];
724 char tag[2][76];
725
726 /* Disable DQI CBR */
727 reg_mcr0c = ast_mindwm(ast, 0x1E6E000C);
728 reg_mcr18 = ast_mindwm(ast, 0x1E6E0018);
729 reg_mcr18 &= 0x0000ffff;
730 ast_moutdwm(ast, 0x1E6E0018, reg_mcr18);
788 731
789 for (cnt = 0; cnt < 16; cnt++) {
790 dllmin[cnt] = 0xff;
791 dllmax[cnt] = 0x0;
792 }
793 passcnt = 0;
794 for (dlli = 0; dlli < 76; dlli++) { 732 for (dlli = 0; dlli < 76; dlli++) {
795 moutdwm(ast, 0x1E6E0068, 0x00001400 | (dlli << 16) | (dlli << 24)); 733 tag[0][dlli] = 0x0;
796 /* Wait DQSI latch phase calibration */ 734 tag[1][dlli] = 0x0;
797 moutdwm(ast, 0x1E6E0074, 0x00000010);
798 moutdwm(ast, 0x1E6E0070, 0x00000003);
799 do {
800 data = mindwm(ast, 0x1E6E0070);
801 } while (!(data & 0x00001000));
802 moutdwm(ast, 0x1E6E0070, 0x00000000);
803
804 moutdwm(ast, 0x1E6E0074, CBR_SIZE2);
805 data = cbr_scan2(ast);
806 if (data != 0) {
807 mask = 0x00010001;
808 for (cnt = 0; cnt < 16; cnt++) {
809 if (data & mask) {
810 if (dllmin[cnt] > dlli) {
811 dllmin[cnt] = dlli;
812 }
813 if (dllmax[cnt] < dlli) {
814 dllmax[cnt] = dlli;
815 }
816 }
817 mask <<= 1;
818 }
819 passcnt++;
820 } else if (passcnt >= CBR_THRESHOLD2) {
821 break;
822 }
823 } 735 }
824 gold_sadj[0] = 0x0; 736 for (dqidly = 0; dqidly < 32; dqidly++) {
825 gold_sadj[1] = 0xFF; 737 pass[dqidly][0][0] = 0xff;
826 for (cnt = 0; cnt < 8; cnt++) { 738 pass[dqidly][0][1] = 0x0;
827 if ((dllmax[cnt] > dllmin[cnt]) && ((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD2)) { 739 pass[dqidly][1][0] = 0xff;
828 if (gold_sadj[0] < dllmin[cnt]) { 740 pass[dqidly][1][1] = 0x0;
829 gold_sadj[0] = dllmin[cnt];
830 }
831 if (gold_sadj[1] > dllmax[cnt]) {
832 gold_sadj[1] = dllmax[cnt];
833 }
834 }
835 } 741 }
836 gold_sadj[0] = (gold_sadj[1] + gold_sadj[0]) >> 1; 742 for (dqidly = 0; dqidly < 32; dqidly++) {
837 gold_sadj[1] = mindwm(ast, 0x1E6E0080); 743 passcnt[0] = passcnt[1] = 0;
838 744 for (dqsip = 0; dqsip < 2; dqsip++) {
839 data = 0; 745 ast_moutdwm(ast, 0x1E6E000C, 0);
840 for (cnt = 0; cnt < 8; cnt++) { 746 ast_moutdwm(ast, 0x1E6E0018, reg_mcr18 | (dqidly << 16) | (dqsip << 23));
841 data >>= 3; 747 ast_moutdwm(ast, 0x1E6E000C, reg_mcr0c);
842 data2 = gold_sadj[1] & 0x7; 748 for (dlli = 0; dlli < 76; dlli++) {
843 gold_sadj[1] >>= 3; 749 ast_moutdwm(ast, 0x1E6E0068, 0x00001300 | (dlli << 16) | (dlli << 24));
844 if ((dllmax[cnt] > dllmin[cnt]) && ((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD2)) { 750 ast_moutdwm(ast, 0x1E6E0070, 0);
845 dlli = (dllmin[cnt] + dllmax[cnt]) >> 1; 751 ast_moutdwm(ast, 0x1E6E0074, CBR_SIZE0);
846 if (gold_sadj[0] >= dlli) { 752 if (cbr_scan3(ast)) {
847 dlli = (gold_sadj[0] - dlli) >> 1; 753 if (dlli == 0)
848 if (dlli > 0) { 754 break;
849 dlli = 1; 755 passcnt[dqsip]++;
850 } 756 tag[dqsip][dlli] = 'P';
851 if (data2 != 3) { 757 if (dlli < pass[dqidly][dqsip][0])
852 data2 = (data2 + dlli) & 0x7; 758 pass[dqidly][dqsip][0] = (u16) dlli;
853 } 759 if (dlli > pass[dqidly][dqsip][1])
854 } else { 760 pass[dqidly][dqsip][1] = (u16) dlli;
855 dlli = (dlli - gold_sadj[0]) >> 1; 761 } else if (passcnt[dqsip] >= 5)
856 if (dlli > 0) { 762 break;
857 dlli = 1; 763 else {
858 } 764 pass[dqidly][dqsip][0] = 0xff;
859 if (data2 != 4) { 765 pass[dqidly][dqsip][1] = 0x0;
860 data2 = (data2 - dlli) & 0x7;
861 } 766 }
862 } 767 }
863 } 768 }
864 data |= data2 << 21; 769 if (passcnt[0] == 0 && passcnt[1] == 0)
865 } 770 dqidly++;
866 moutdwm(ast, 0x1E6E0080, data);
867
868 gold_sadj[0] = 0x0;
869 gold_sadj[1] = 0xFF;
870 for (cnt = 8; cnt < 16; cnt++) {
871 if ((dllmax[cnt] > dllmin[cnt]) && ((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD2)) {
872 if (gold_sadj[0] < dllmin[cnt]) {
873 gold_sadj[0] = dllmin[cnt];
874 }
875 if (gold_sadj[1] > dllmax[cnt]) {
876 gold_sadj[1] = dllmax[cnt];
877 }
878 }
879 } 771 }
880 gold_sadj[0] = (gold_sadj[1] + gold_sadj[0]) >> 1; 772 /* Search margin */
881 gold_sadj[1] = mindwm(ast, 0x1E6E0084); 773 g_dqidly = g_dqsip = g_margin = g_side = 0;
882 774
883 data = 0; 775 for (dqidly = 0; dqidly < 32; dqidly++) {
884 for (cnt = 8; cnt < 16; cnt++) { 776 for (dqsip = 0; dqsip < 2; dqsip++) {
885 data >>= 3; 777 if (pass[dqidly][dqsip][0] > pass[dqidly][dqsip][1])
886 data2 = gold_sadj[1] & 0x7; 778 continue;
887 gold_sadj[1] >>= 3; 779 diff = pass[dqidly][dqsip][1] - pass[dqidly][dqsip][0];
888 if ((dllmax[cnt] > dllmin[cnt]) && ((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD2)) { 780 if ((diff+2) < g_margin)
889 dlli = (dllmin[cnt] + dllmax[cnt]) >> 1; 781 continue;
890 if (gold_sadj[0] >= dlli) { 782 passcnt[0] = passcnt[1] = 0;
891 dlli = (gold_sadj[0] - dlli) >> 1; 783 for (dlli = pass[dqidly][dqsip][0]; dlli > 0 && tag[dqsip][dlli] != 0; dlli--, passcnt[0]++);
892 if (dlli > 0) { 784 for (dlli = pass[dqidly][dqsip][1]; dlli < 76 && tag[dqsip][dlli] != 0; dlli++, passcnt[1]++);
893 dlli = 1; 785 if (passcnt[0] > passcnt[1])
894 } 786 passcnt[0] = passcnt[1];
895 if (data2 != 3) { 787 passcnt[1] = 0;
896 data2 = (data2 + dlli) & 0x7; 788 if (passcnt[0] > g_side)
897 } 789 passcnt[1] = passcnt[0] - g_side;
898 } else { 790 if (diff > (g_margin+1) && (passcnt[1] > 0 || passcnt[0] > 8)) {
899 dlli = (dlli - gold_sadj[0]) >> 1; 791 g_margin = diff;
900 if (dlli > 0) { 792 g_dqidly = dqidly;
901 dlli = 1; 793 g_dqsip = dqsip;
902 } 794 g_side = passcnt[0];
903 if (data2 != 4) { 795 } else if (passcnt[1] > 1 && g_side < 8) {
904 data2 = (data2 - dlli) & 0x7; 796 if (diff > g_margin)
905 } 797 g_margin = diff;
798 g_dqidly = dqidly;
799 g_dqsip = dqsip;
800 g_side = passcnt[0];
906 } 801 }
907 } 802 }
908 data |= data2 << 21;
909 } 803 }
910 moutdwm(ast, 0x1E6E0084, data); 804 reg_mcr18 = reg_mcr18 | (g_dqidly << 16) | (g_dqsip << 23);
911 805 ast_moutdwm(ast, 0x1E6E0018, reg_mcr18);
912} /* finetuneDQI_L2 */
913 806
914static void cbr_dll2(struct ast_private *ast, struct ast2300_dram_param *param) 807}
808static bool cbr_dll2(struct ast_private *ast, struct ast2300_dram_param *param)
915{ 809{
916 u32 dllmin[2], dllmax[2], dlli, data, data2, passcnt; 810 u32 dllmin[2], dllmax[2], dlli, data, passcnt, retry = 0;
811 bool status = false;
917 812
918 813 finetuneDQSI(ast);
919 finetuneDQI_L(ast, param); 814 if (finetuneDQI_L(ast, param) == false)
920 finetuneDQI_L2(ast, param); 815 return status;
921 816
922CBR_START2: 817CBR_START2:
923 dllmin[0] = dllmin[1] = 0xff; 818 dllmin[0] = dllmin[1] = 0xff;
924 dllmax[0] = dllmax[1] = 0x0; 819 dllmax[0] = dllmax[1] = 0x0;
925 passcnt = 0; 820 passcnt = 0;
926 for (dlli = 0; dlli < 76; dlli++) { 821 for (dlli = 0; dlli < 76; dlli++) {
927 moutdwm(ast, 0x1E6E0068, 0x00001300 | (dlli << 16) | (dlli << 24)); 822 ast_moutdwm(ast, 0x1E6E0068, 0x00001300 | (dlli << 16) | (dlli << 24));
928 /* Wait DQSI latch phase calibration */ 823 ast_moutdwm(ast, 0x1E6E0074, CBR_SIZE2);
929 moutdwm(ast, 0x1E6E0074, 0x00000010);
930 moutdwm(ast, 0x1E6E0070, 0x00000003);
931 do {
932 data = mindwm(ast, 0x1E6E0070);
933 } while (!(data & 0x00001000));
934 moutdwm(ast, 0x1E6E0070, 0x00000000);
935
936 moutdwm(ast, 0x1E6E0074, CBR_SIZE2);
937 data = cbr_scan(ast); 824 data = cbr_scan(ast);
938 if (data != 0) { 825 if (data != 0) {
939 if (data & 0x1) { 826 if (data & 0x1) {
@@ -957,44 +844,31 @@ CBR_START2:
957 break; 844 break;
958 } 845 }
959 } 846 }
847 if (retry++ > 10)
848 goto CBR_DONE2;
960 if (dllmax[0] == 0 || (dllmax[0]-dllmin[0]) < CBR_THRESHOLD) { 849 if (dllmax[0] == 0 || (dllmax[0]-dllmin[0]) < CBR_THRESHOLD) {
961 goto CBR_START2; 850 goto CBR_START2;
962 } 851 }
963 if (dllmax[1] == 0 || (dllmax[1]-dllmin[1]) < CBR_THRESHOLD) { 852 if (dllmax[1] == 0 || (dllmax[1]-dllmin[1]) < CBR_THRESHOLD) {
964 goto CBR_START2; 853 goto CBR_START2;
965 } 854 }
855 status = true;
856CBR_DONE2:
966 dlli = (dllmin[1] + dllmax[1]) >> 1; 857 dlli = (dllmin[1] + dllmax[1]) >> 1;
967 dlli <<= 8; 858 dlli <<= 8;
968 dlli += (dllmin[0] + dllmax[0]) >> 1; 859 dlli += (dllmin[0] + dllmax[0]) >> 1;
969 moutdwm(ast, 0x1E6E0068, (mindwm(ast, 0x1E6E0068) & 0xFFFF) | (dlli << 16)); 860 ast_moutdwm(ast, 0x1E6E0068, ast_mindwm(ast, 0x1E720058) | (dlli << 16));
970 861 return status;
971 data = (mindwm(ast, 0x1E6E0080) >> 24) & 0x1F;
972 data2 = (mindwm(ast, 0x1E6E0018) & 0xff80ffff) | (data << 16);
973 moutdwm(ast, 0x1E6E0018, data2);
974 moutdwm(ast, 0x1E6E0024, 0x8001 | (data << 1) | (param->dll2_finetune_step << 8));
975
976 /* Wait DQSI latch phase calibration */
977 moutdwm(ast, 0x1E6E0074, 0x00000010);
978 moutdwm(ast, 0x1E6E0070, 0x00000003);
979 do {
980 data = mindwm(ast, 0x1E6E0070);
981 } while (!(data & 0x00001000));
982 moutdwm(ast, 0x1E6E0070, 0x00000000);
983 moutdwm(ast, 0x1E6E0070, 0x00000003);
984 do {
985 data = mindwm(ast, 0x1E6E0070);
986 } while (!(data & 0x00001000));
987 moutdwm(ast, 0x1E6E0070, 0x00000000);
988} /* CBRDLL2 */ 862} /* CBRDLL2 */
989 863
990static void get_ddr3_info(struct ast_private *ast, struct ast2300_dram_param *param) 864static void get_ddr3_info(struct ast_private *ast, struct ast2300_dram_param *param)
991{ 865{
992 u32 trap, trap_AC2, trap_MRS; 866 u32 trap, trap_AC2, trap_MRS;
993 867
994 moutdwm(ast, 0x1E6E2000, 0x1688A8A8); 868 ast_moutdwm(ast, 0x1E6E2000, 0x1688A8A8);
995 869
996 /* Ger trap info */ 870 /* Ger trap info */
997 trap = (mindwm(ast, 0x1E6E2070) >> 25) & 0x3; 871 trap = (ast_mindwm(ast, 0x1E6E2070) >> 25) & 0x3;
998 trap_AC2 = 0x00020000 + (trap << 16); 872 trap_AC2 = 0x00020000 + (trap << 16);
999 trap_AC2 |= 0x00300000 + ((trap & 0x2) << 19); 873 trap_AC2 |= 0x00300000 + ((trap & 0x2) << 19);
1000 trap_MRS = 0x00000010 + (trap << 4); 874 trap_MRS = 0x00000010 + (trap << 4);
@@ -1008,22 +882,35 @@ static void get_ddr3_info(struct ast_private *ast, struct ast2300_dram_param *pa
1008 882
1009 switch (param->dram_freq) { 883 switch (param->dram_freq) {
1010 case 336: 884 case 336:
1011 moutdwm(ast, 0x1E6E2020, 0x0190); 885 ast_moutdwm(ast, 0x1E6E2020, 0x0190);
1012 param->wodt = 0; 886 param->wodt = 0;
1013 param->reg_AC1 = 0x22202725; 887 param->reg_AC1 = 0x22202725;
1014 param->reg_AC2 = 0xAA007613 | trap_AC2; 888 param->reg_AC2 = 0xAA007613 | trap_AC2;
1015 param->reg_DQSIC = 0x000000BA; 889 param->reg_DQSIC = 0x000000BA;
1016 param->reg_MRS = 0x04001400 | trap_MRS; 890 param->reg_MRS = 0x04001400 | trap_MRS;
1017 param->reg_EMRS = 0x00000000; 891 param->reg_EMRS = 0x00000000;
1018 param->reg_IOZ = 0x00000034; 892 param->reg_IOZ = 0x00000023;
1019 param->reg_DQIDLY = 0x00000074; 893 param->reg_DQIDLY = 0x00000074;
1020 param->reg_FREQ = 0x00004DC0; 894 param->reg_FREQ = 0x00004DC0;
1021 param->madj_max = 96; 895 param->madj_max = 96;
1022 param->dll2_finetune_step = 3; 896 param->dll2_finetune_step = 3;
897 switch (param->dram_chipid) {
898 default:
899 case AST_DRAM_512Mx16:
900 case AST_DRAM_1Gx16:
901 param->reg_AC2 = 0xAA007613 | trap_AC2;
902 break;
903 case AST_DRAM_2Gx16:
904 param->reg_AC2 = 0xAA00761C | trap_AC2;
905 break;
906 case AST_DRAM_4Gx16:
907 param->reg_AC2 = 0xAA007636 | trap_AC2;
908 break;
909 }
1023 break; 910 break;
1024 default: 911 default:
1025 case 396: 912 case 396:
1026 moutdwm(ast, 0x1E6E2020, 0x03F1); 913 ast_moutdwm(ast, 0x1E6E2020, 0x03F1);
1027 param->wodt = 1; 914 param->wodt = 1;
1028 param->reg_AC1 = 0x33302825; 915 param->reg_AC1 = 0x33302825;
1029 param->reg_AC2 = 0xCC009617 | trap_AC2; 916 param->reg_AC2 = 0xCC009617 | trap_AC2;
@@ -1033,7 +920,7 @@ static void get_ddr3_info(struct ast_private *ast, struct ast2300_dram_param *pa
1033 param->reg_IOZ = 0x00000034; 920 param->reg_IOZ = 0x00000034;
1034 param->reg_DRV = 0x000000FA; 921 param->reg_DRV = 0x000000FA;
1035 param->reg_DQIDLY = 0x00000089; 922 param->reg_DQIDLY = 0x00000089;
1036 param->reg_FREQ = 0x000050C0; 923 param->reg_FREQ = 0x00005040;
1037 param->madj_max = 96; 924 param->madj_max = 96;
1038 param->dll2_finetune_step = 4; 925 param->dll2_finetune_step = 4;
1039 926
@@ -1053,14 +940,14 @@ static void get_ddr3_info(struct ast_private *ast, struct ast2300_dram_param *pa
1053 break; 940 break;
1054 941
1055 case 408: 942 case 408:
1056 moutdwm(ast, 0x1E6E2020, 0x01F0); 943 ast_moutdwm(ast, 0x1E6E2020, 0x01F0);
1057 param->wodt = 1; 944 param->wodt = 1;
1058 param->reg_AC1 = 0x33302825; 945 param->reg_AC1 = 0x33302825;
1059 param->reg_AC2 = 0xCC009617 | trap_AC2; 946 param->reg_AC2 = 0xCC009617 | trap_AC2;
1060 param->reg_DQSIC = 0x000000E2; 947 param->reg_DQSIC = 0x000000E2;
1061 param->reg_MRS = 0x04001600 | trap_MRS; 948 param->reg_MRS = 0x04001600 | trap_MRS;
1062 param->reg_EMRS = 0x00000000; 949 param->reg_EMRS = 0x00000000;
1063 param->reg_IOZ = 0x00000034; 950 param->reg_IOZ = 0x00000023;
1064 param->reg_DRV = 0x000000FA; 951 param->reg_DRV = 0x000000FA;
1065 param->reg_DQIDLY = 0x00000089; 952 param->reg_DQIDLY = 0x00000089;
1066 param->reg_FREQ = 0x000050C0; 953 param->reg_FREQ = 0x000050C0;
@@ -1083,7 +970,7 @@ static void get_ddr3_info(struct ast_private *ast, struct ast2300_dram_param *pa
1083 970
1084 break; 971 break;
1085 case 456: 972 case 456:
1086 moutdwm(ast, 0x1E6E2020, 0x0230); 973 ast_moutdwm(ast, 0x1E6E2020, 0x0230);
1087 param->wodt = 0; 974 param->wodt = 0;
1088 param->reg_AC1 = 0x33302926; 975 param->reg_AC1 = 0x33302926;
1089 param->reg_AC2 = 0xCD44961A; 976 param->reg_AC2 = 0xCD44961A;
@@ -1097,7 +984,7 @@ static void get_ddr3_info(struct ast_private *ast, struct ast2300_dram_param *pa
1097 param->dll2_finetune_step = 4; 984 param->dll2_finetune_step = 4;
1098 break; 985 break;
1099 case 504: 986 case 504:
1100 moutdwm(ast, 0x1E6E2020, 0x0270); 987 ast_moutdwm(ast, 0x1E6E2020, 0x0270);
1101 param->wodt = 1; 988 param->wodt = 1;
1102 param->reg_AC1 = 0x33302926; 989 param->reg_AC1 = 0x33302926;
1103 param->reg_AC2 = 0xDE44A61D; 990 param->reg_AC2 = 0xDE44A61D;
@@ -1111,7 +998,7 @@ static void get_ddr3_info(struct ast_private *ast, struct ast2300_dram_param *pa
1111 param->dll2_finetune_step = 4; 998 param->dll2_finetune_step = 4;
1112 break; 999 break;
1113 case 528: 1000 case 528:
1114 moutdwm(ast, 0x1E6E2020, 0x0290); 1001 ast_moutdwm(ast, 0x1E6E2020, 0x0290);
1115 param->wodt = 1; 1002 param->wodt = 1;
1116 param->rodt = 1; 1003 param->rodt = 1;
1117 param->reg_AC1 = 0x33302926; 1004 param->reg_AC1 = 0x33302926;
@@ -1127,7 +1014,7 @@ static void get_ddr3_info(struct ast_private *ast, struct ast2300_dram_param *pa
1127 param->dll2_finetune_step = 3; 1014 param->dll2_finetune_step = 3;
1128 break; 1015 break;
1129 case 576: 1016 case 576:
1130 moutdwm(ast, 0x1E6E2020, 0x0140); 1017 ast_moutdwm(ast, 0x1E6E2020, 0x0140);
1131 param->reg_MADJ = 0x00136868; 1018 param->reg_MADJ = 0x00136868;
1132 param->reg_SADJ = 0x00004534; 1019 param->reg_SADJ = 0x00004534;
1133 param->wodt = 1; 1020 param->wodt = 1;
@@ -1145,7 +1032,7 @@ static void get_ddr3_info(struct ast_private *ast, struct ast2300_dram_param *pa
1145 param->dll2_finetune_step = 3; 1032 param->dll2_finetune_step = 3;
1146 break; 1033 break;
1147 case 600: 1034 case 600:
1148 moutdwm(ast, 0x1E6E2020, 0x02E1); 1035 ast_moutdwm(ast, 0x1E6E2020, 0x02E1);
1149 param->reg_MADJ = 0x00136868; 1036 param->reg_MADJ = 0x00136868;
1150 param->reg_SADJ = 0x00004534; 1037 param->reg_SADJ = 0x00004534;
1151 param->wodt = 1; 1038 param->wodt = 1;
@@ -1163,7 +1050,7 @@ static void get_ddr3_info(struct ast_private *ast, struct ast2300_dram_param *pa
1163 param->dll2_finetune_step = 3; 1050 param->dll2_finetune_step = 3;
1164 break; 1051 break;
1165 case 624: 1052 case 624:
1166 moutdwm(ast, 0x1E6E2020, 0x0160); 1053 ast_moutdwm(ast, 0x1E6E2020, 0x0160);
1167 param->reg_MADJ = 0x00136868; 1054 param->reg_MADJ = 0x00136868;
1168 param->reg_SADJ = 0x00004534; 1055 param->reg_SADJ = 0x00004534;
1169 param->wodt = 1; 1056 param->wodt = 1;
@@ -1218,106 +1105,98 @@ static void get_ddr3_info(struct ast_private *ast, struct ast2300_dram_param *pa
1218 1105
1219static void ddr3_init(struct ast_private *ast, struct ast2300_dram_param *param) 1106static void ddr3_init(struct ast_private *ast, struct ast2300_dram_param *param)
1220{ 1107{
1221 u32 data, data2; 1108 u32 data, data2, retry = 0;
1222 1109
1223 moutdwm(ast, 0x1E6E0000, 0xFC600309); 1110ddr3_init_start:
1224 moutdwm(ast, 0x1E6E0018, 0x00000100); 1111 ast_moutdwm(ast, 0x1E6E0000, 0xFC600309);
1225 moutdwm(ast, 0x1E6E0024, 0x00000000); 1112 ast_moutdwm(ast, 0x1E6E0018, 0x00000100);
1226 moutdwm(ast, 0x1E6E0034, 0x00000000); 1113 ast_moutdwm(ast, 0x1E6E0024, 0x00000000);
1114 ast_moutdwm(ast, 0x1E6E0034, 0x00000000);
1227 udelay(10); 1115 udelay(10);
1228 moutdwm(ast, 0x1E6E0064, param->reg_MADJ); 1116 ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ);
1229 moutdwm(ast, 0x1E6E0068, param->reg_SADJ); 1117 ast_moutdwm(ast, 0x1E6E0068, param->reg_SADJ);
1230 udelay(10); 1118 udelay(10);
1231 moutdwm(ast, 0x1E6E0064, param->reg_MADJ | 0xC0000); 1119 ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ | 0xC0000);
1232 udelay(10); 1120 udelay(10);
1233 1121
1234 moutdwm(ast, 0x1E6E0004, param->dram_config); 1122 ast_moutdwm(ast, 0x1E6E0004, param->dram_config);
1235 moutdwm(ast, 0x1E6E0008, 0x90040f); 1123 ast_moutdwm(ast, 0x1E6E0008, 0x90040f);
1236 moutdwm(ast, 0x1E6E0010, param->reg_AC1); 1124 ast_moutdwm(ast, 0x1E6E0010, param->reg_AC1);
1237 moutdwm(ast, 0x1E6E0014, param->reg_AC2); 1125 ast_moutdwm(ast, 0x1E6E0014, param->reg_AC2);
1238 moutdwm(ast, 0x1E6E0020, param->reg_DQSIC); 1126 ast_moutdwm(ast, 0x1E6E0020, param->reg_DQSIC);
1239 moutdwm(ast, 0x1E6E0080, 0x00000000); 1127 ast_moutdwm(ast, 0x1E6E0080, 0x00000000);
1240 moutdwm(ast, 0x1E6E0084, 0x00000000); 1128 ast_moutdwm(ast, 0x1E6E0084, 0x00000000);
1241 moutdwm(ast, 0x1E6E0088, param->reg_DQIDLY); 1129 ast_moutdwm(ast, 0x1E6E0088, param->reg_DQIDLY);
1242 moutdwm(ast, 0x1E6E0018, 0x4040A170); 1130 ast_moutdwm(ast, 0x1E6E0018, 0x4000A170);
1243 moutdwm(ast, 0x1E6E0018, 0x20402370); 1131 ast_moutdwm(ast, 0x1E6E0018, 0x00002370);
1244 moutdwm(ast, 0x1E6E0038, 0x00000000); 1132 ast_moutdwm(ast, 0x1E6E0038, 0x00000000);
1245 moutdwm(ast, 0x1E6E0040, 0xFF444444); 1133 ast_moutdwm(ast, 0x1E6E0040, 0xFF444444);
1246 moutdwm(ast, 0x1E6E0044, 0x22222222); 1134 ast_moutdwm(ast, 0x1E6E0044, 0x22222222);
1247 moutdwm(ast, 0x1E6E0048, 0x22222222); 1135 ast_moutdwm(ast, 0x1E6E0048, 0x22222222);
1248 moutdwm(ast, 0x1E6E004C, 0x00000002); 1136 ast_moutdwm(ast, 0x1E6E004C, 0x00000002);
1249 moutdwm(ast, 0x1E6E0050, 0x80000000); 1137 ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
1250 moutdwm(ast, 0x1E6E0050, 0x00000000); 1138 ast_moutdwm(ast, 0x1E6E0050, 0x00000000);
1251 moutdwm(ast, 0x1E6E0054, 0); 1139 ast_moutdwm(ast, 0x1E6E0054, 0);
1252 moutdwm(ast, 0x1E6E0060, param->reg_DRV); 1140 ast_moutdwm(ast, 0x1E6E0060, param->reg_DRV);
1253 moutdwm(ast, 0x1E6E006C, param->reg_IOZ); 1141 ast_moutdwm(ast, 0x1E6E006C, param->reg_IOZ);
1254 moutdwm(ast, 0x1E6E0070, 0x00000000); 1142 ast_moutdwm(ast, 0x1E6E0070, 0x00000000);
1255 moutdwm(ast, 0x1E6E0074, 0x00000000); 1143 ast_moutdwm(ast, 0x1E6E0074, 0x00000000);
1256 moutdwm(ast, 0x1E6E0078, 0x00000000); 1144 ast_moutdwm(ast, 0x1E6E0078, 0x00000000);
1257 moutdwm(ast, 0x1E6E007C, 0x00000000); 1145 ast_moutdwm(ast, 0x1E6E007C, 0x00000000);
1258 /* Wait MCLK2X lock to MCLK */ 1146 /* Wait MCLK2X lock to MCLK */
1259 do { 1147 do {
1260 data = mindwm(ast, 0x1E6E001C); 1148 data = ast_mindwm(ast, 0x1E6E001C);
1261 } while (!(data & 0x08000000)); 1149 } while (!(data & 0x08000000));
1262 moutdwm(ast, 0x1E6E0034, 0x00000001); 1150 data = ast_mindwm(ast, 0x1E6E001C);
1263 moutdwm(ast, 0x1E6E000C, 0x00005C04);
1264 udelay(10);
1265 moutdwm(ast, 0x1E6E000C, 0x00000000);
1266 moutdwm(ast, 0x1E6E0034, 0x00000000);
1267 data = mindwm(ast, 0x1E6E001C);
1268 data = (data >> 8) & 0xff; 1151 data = (data >> 8) & 0xff;
1269 while ((data & 0x08) || ((data & 0x7) < 2) || (data < 4)) { 1152 while ((data & 0x08) || ((data & 0x7) < 2) || (data < 4)) {
1270 data2 = (mindwm(ast, 0x1E6E0064) & 0xfff3ffff) + 4; 1153 data2 = (ast_mindwm(ast, 0x1E6E0064) & 0xfff3ffff) + 4;
1271 if ((data2 & 0xff) > param->madj_max) { 1154 if ((data2 & 0xff) > param->madj_max) {
1272 break; 1155 break;
1273 } 1156 }
1274 moutdwm(ast, 0x1E6E0064, data2); 1157 ast_moutdwm(ast, 0x1E6E0064, data2);
1275 if (data2 & 0x00100000) { 1158 if (data2 & 0x00100000) {
1276 data2 = ((data2 & 0xff) >> 3) + 3; 1159 data2 = ((data2 & 0xff) >> 3) + 3;
1277 } else { 1160 } else {
1278 data2 = ((data2 & 0xff) >> 2) + 5; 1161 data2 = ((data2 & 0xff) >> 2) + 5;
1279 } 1162 }
1280 data = mindwm(ast, 0x1E6E0068) & 0xffff00ff; 1163 data = ast_mindwm(ast, 0x1E6E0068) & 0xffff00ff;
1281 data2 += data & 0xff; 1164 data2 += data & 0xff;
1282 data = data | (data2 << 8); 1165 data = data | (data2 << 8);
1283 moutdwm(ast, 0x1E6E0068, data); 1166 ast_moutdwm(ast, 0x1E6E0068, data);
1284 udelay(10); 1167 udelay(10);
1285 moutdwm(ast, 0x1E6E0064, mindwm(ast, 0x1E6E0064) | 0xC0000); 1168 ast_moutdwm(ast, 0x1E6E0064, ast_mindwm(ast, 0x1E6E0064) | 0xC0000);
1286 udelay(10); 1169 udelay(10);
1287 data = mindwm(ast, 0x1E6E0018) & 0xfffff1ff; 1170 data = ast_mindwm(ast, 0x1E6E0018) & 0xfffff1ff;
1288 moutdwm(ast, 0x1E6E0018, data); 1171 ast_moutdwm(ast, 0x1E6E0018, data);
1289 data = data | 0x200; 1172 data = data | 0x200;
1290 moutdwm(ast, 0x1E6E0018, data); 1173 ast_moutdwm(ast, 0x1E6E0018, data);
1291 do { 1174 do {
1292 data = mindwm(ast, 0x1E6E001C); 1175 data = ast_mindwm(ast, 0x1E6E001C);
1293 } while (!(data & 0x08000000)); 1176 } while (!(data & 0x08000000));
1294 1177
1295 moutdwm(ast, 0x1E6E0034, 0x00000001); 1178 data = ast_mindwm(ast, 0x1E6E001C);
1296 moutdwm(ast, 0x1E6E000C, 0x00005C04);
1297 udelay(10);
1298 moutdwm(ast, 0x1E6E000C, 0x00000000);
1299 moutdwm(ast, 0x1E6E0034, 0x00000000);
1300 data = mindwm(ast, 0x1E6E001C);
1301 data = (data >> 8) & 0xff; 1179 data = (data >> 8) & 0xff;
1302 } 1180 }
1303 data = mindwm(ast, 0x1E6E0018) | 0xC00; 1181 ast_moutdwm(ast, 0x1E720058, ast_mindwm(ast, 0x1E6E0068) & 0xffff);
1304 moutdwm(ast, 0x1E6E0018, data); 1182 data = ast_mindwm(ast, 0x1E6E0018) | 0xC00;
1183 ast_moutdwm(ast, 0x1E6E0018, data);
1305 1184
1306 moutdwm(ast, 0x1E6E0034, 0x00000001); 1185 ast_moutdwm(ast, 0x1E6E0034, 0x00000001);
1307 moutdwm(ast, 0x1E6E000C, 0x00000040); 1186 ast_moutdwm(ast, 0x1E6E000C, 0x00000040);
1308 udelay(50); 1187 udelay(50);
1309 /* Mode Register Setting */ 1188 /* Mode Register Setting */
1310 moutdwm(ast, 0x1E6E002C, param->reg_MRS | 0x100); 1189 ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS | 0x100);
1311 moutdwm(ast, 0x1E6E0030, param->reg_EMRS); 1190 ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS);
1312 moutdwm(ast, 0x1E6E0028, 0x00000005); 1191 ast_moutdwm(ast, 0x1E6E0028, 0x00000005);
1313 moutdwm(ast, 0x1E6E0028, 0x00000007); 1192 ast_moutdwm(ast, 0x1E6E0028, 0x00000007);
1314 moutdwm(ast, 0x1E6E0028, 0x00000003); 1193 ast_moutdwm(ast, 0x1E6E0028, 0x00000003);
1315 moutdwm(ast, 0x1E6E0028, 0x00000001); 1194 ast_moutdwm(ast, 0x1E6E0028, 0x00000001);
1316 moutdwm(ast, 0x1E6E002C, param->reg_MRS); 1195 ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS);
1317 moutdwm(ast, 0x1E6E000C, 0x00005C08); 1196 ast_moutdwm(ast, 0x1E6E000C, 0x00005C08);
1318 moutdwm(ast, 0x1E6E0028, 0x00000001); 1197 ast_moutdwm(ast, 0x1E6E0028, 0x00000001);
1319 1198
1320 moutdwm(ast, 0x1E6E000C, 0x7FFF5C01); 1199 ast_moutdwm(ast, 0x1E6E000C, 0x00005C01);
1321 data = 0; 1200 data = 0;
1322 if (param->wodt) { 1201 if (param->wodt) {
1323 data = 0x300; 1202 data = 0x300;
@@ -1325,30 +1204,23 @@ static void ddr3_init(struct ast_private *ast, struct ast2300_dram_param *param)
1325 if (param->rodt) { 1204 if (param->rodt) {
1326 data = data | 0x3000 | ((param->reg_AC2 & 0x60000) >> 3); 1205 data = data | 0x3000 | ((param->reg_AC2 & 0x60000) >> 3);
1327 } 1206 }
1328 moutdwm(ast, 0x1E6E0034, data | 0x3); 1207 ast_moutdwm(ast, 0x1E6E0034, data | 0x3);
1329 1208
1330 /* Wait DQI delay lock */
1331 do {
1332 data = mindwm(ast, 0x1E6E0080);
1333 } while (!(data & 0x40000000));
1334 /* Wait DQSI delay lock */
1335 do {
1336 data = mindwm(ast, 0x1E6E0020);
1337 } while (!(data & 0x00000800));
1338 /* Calibrate the DQSI delay */ 1209 /* Calibrate the DQSI delay */
1339 cbr_dll2(ast, param); 1210 if ((cbr_dll2(ast, param) == false) && (retry++ < 10))
1211 goto ddr3_init_start;
1340 1212
1341 moutdwm(ast, 0x1E6E0120, param->reg_FREQ); 1213 ast_moutdwm(ast, 0x1E6E0120, param->reg_FREQ);
1342 /* ECC Memory Initialization */ 1214 /* ECC Memory Initialization */
1343#ifdef ECC 1215#ifdef ECC
1344 moutdwm(ast, 0x1E6E007C, 0x00000000); 1216 ast_moutdwm(ast, 0x1E6E007C, 0x00000000);
1345 moutdwm(ast, 0x1E6E0070, 0x221); 1217 ast_moutdwm(ast, 0x1E6E0070, 0x221);
1346 do { 1218 do {
1347 data = mindwm(ast, 0x1E6E0070); 1219 data = ast_mindwm(ast, 0x1E6E0070);
1348 } while (!(data & 0x00001000)); 1220 } while (!(data & 0x00001000));
1349 moutdwm(ast, 0x1E6E0070, 0x00000000); 1221 ast_moutdwm(ast, 0x1E6E0070, 0x00000000);
1350 moutdwm(ast, 0x1E6E0050, 0x80000000); 1222 ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
1351 moutdwm(ast, 0x1E6E0050, 0x00000000); 1223 ast_moutdwm(ast, 0x1E6E0050, 0x00000000);
1352#endif 1224#endif
1353 1225
1354 1226
@@ -1358,10 +1230,10 @@ static void get_ddr2_info(struct ast_private *ast, struct ast2300_dram_param *pa
1358{ 1230{
1359 u32 trap, trap_AC2, trap_MRS; 1231 u32 trap, trap_AC2, trap_MRS;
1360 1232
1361 moutdwm(ast, 0x1E6E2000, 0x1688A8A8); 1233 ast_moutdwm(ast, 0x1E6E2000, 0x1688A8A8);
1362 1234
1363 /* Ger trap info */ 1235 /* Ger trap info */
1364 trap = (mindwm(ast, 0x1E6E2070) >> 25) & 0x3; 1236 trap = (ast_mindwm(ast, 0x1E6E2070) >> 25) & 0x3;
1365 trap_AC2 = (trap << 20) | (trap << 16); 1237 trap_AC2 = (trap << 20) | (trap << 16);
1366 trap_AC2 += 0x00110000; 1238 trap_AC2 += 0x00110000;
1367 trap_MRS = 0x00000040 | (trap << 4); 1239 trap_MRS = 0x00000040 | (trap << 4);
@@ -1375,7 +1247,7 @@ static void get_ddr2_info(struct ast_private *ast, struct ast2300_dram_param *pa
1375 1247
1376 switch (param->dram_freq) { 1248 switch (param->dram_freq) {
1377 case 264: 1249 case 264:
1378 moutdwm(ast, 0x1E6E2020, 0x0130); 1250 ast_moutdwm(ast, 0x1E6E2020, 0x0130);
1379 param->wodt = 0; 1251 param->wodt = 0;
1380 param->reg_AC1 = 0x11101513; 1252 param->reg_AC1 = 0x11101513;
1381 param->reg_AC2 = 0x78117011; 1253 param->reg_AC2 = 0x78117011;
@@ -1390,7 +1262,7 @@ static void get_ddr2_info(struct ast_private *ast, struct ast2300_dram_param *pa
1390 param->dll2_finetune_step = 3; 1262 param->dll2_finetune_step = 3;
1391 break; 1263 break;
1392 case 336: 1264 case 336:
1393 moutdwm(ast, 0x1E6E2020, 0x0190); 1265 ast_moutdwm(ast, 0x1E6E2020, 0x0190);
1394 param->wodt = 1; 1266 param->wodt = 1;
1395 param->reg_AC1 = 0x22202613; 1267 param->reg_AC1 = 0x22202613;
1396 param->reg_AC2 = 0xAA009016 | trap_AC2; 1268 param->reg_AC2 = 0xAA009016 | trap_AC2;
@@ -1403,10 +1275,25 @@ static void get_ddr2_info(struct ast_private *ast, struct ast2300_dram_param *pa
1403 param->reg_FREQ = 0x00004DC0; 1275 param->reg_FREQ = 0x00004DC0;
1404 param->madj_max = 96; 1276 param->madj_max = 96;
1405 param->dll2_finetune_step = 3; 1277 param->dll2_finetune_step = 3;
1278 switch (param->dram_chipid) {
1279 default:
1280 case AST_DRAM_512Mx16:
1281 param->reg_AC2 = 0xAA009012 | trap_AC2;
1282 break;
1283 case AST_DRAM_1Gx16:
1284 param->reg_AC2 = 0xAA009016 | trap_AC2;
1285 break;
1286 case AST_DRAM_2Gx16:
1287 param->reg_AC2 = 0xAA009023 | trap_AC2;
1288 break;
1289 case AST_DRAM_4Gx16:
1290 param->reg_AC2 = 0xAA00903B | trap_AC2;
1291 break;
1292 }
1406 break; 1293 break;
1407 default: 1294 default:
1408 case 396: 1295 case 396:
1409 moutdwm(ast, 0x1E6E2020, 0x03F1); 1296 ast_moutdwm(ast, 0x1E6E2020, 0x03F1);
1410 param->wodt = 1; 1297 param->wodt = 1;
1411 param->rodt = 0; 1298 param->rodt = 0;
1412 param->reg_AC1 = 0x33302714; 1299 param->reg_AC1 = 0x33302714;
@@ -1417,7 +1304,7 @@ static void get_ddr2_info(struct ast_private *ast, struct ast2300_dram_param *pa
1417 param->reg_DRV = 0x000000FA; 1304 param->reg_DRV = 0x000000FA;
1418 param->reg_IOZ = 0x00000034; 1305 param->reg_IOZ = 0x00000034;
1419 param->reg_DQIDLY = 0x00000089; 1306 param->reg_DQIDLY = 0x00000089;
1420 param->reg_FREQ = 0x000050C0; 1307 param->reg_FREQ = 0x00005040;
1421 param->madj_max = 96; 1308 param->madj_max = 96;
1422 param->dll2_finetune_step = 4; 1309 param->dll2_finetune_step = 4;
1423 1310
@@ -1440,7 +1327,7 @@ static void get_ddr2_info(struct ast_private *ast, struct ast2300_dram_param *pa
1440 break; 1327 break;
1441 1328
1442 case 408: 1329 case 408:
1443 moutdwm(ast, 0x1E6E2020, 0x01F0); 1330 ast_moutdwm(ast, 0x1E6E2020, 0x01F0);
1444 param->wodt = 1; 1331 param->wodt = 1;
1445 param->rodt = 0; 1332 param->rodt = 0;
1446 param->reg_AC1 = 0x33302714; 1333 param->reg_AC1 = 0x33302714;
@@ -1473,7 +1360,7 @@ static void get_ddr2_info(struct ast_private *ast, struct ast2300_dram_param *pa
1473 1360
1474 break; 1361 break;
1475 case 456: 1362 case 456:
1476 moutdwm(ast, 0x1E6E2020, 0x0230); 1363 ast_moutdwm(ast, 0x1E6E2020, 0x0230);
1477 param->wodt = 0; 1364 param->wodt = 0;
1478 param->reg_AC1 = 0x33302815; 1365 param->reg_AC1 = 0x33302815;
1479 param->reg_AC2 = 0xCD44B01E; 1366 param->reg_AC2 = 0xCD44B01E;
@@ -1488,7 +1375,7 @@ static void get_ddr2_info(struct ast_private *ast, struct ast2300_dram_param *pa
1488 param->dll2_finetune_step = 3; 1375 param->dll2_finetune_step = 3;
1489 break; 1376 break;
1490 case 504: 1377 case 504:
1491 moutdwm(ast, 0x1E6E2020, 0x0261); 1378 ast_moutdwm(ast, 0x1E6E2020, 0x0261);
1492 param->wodt = 1; 1379 param->wodt = 1;
1493 param->rodt = 1; 1380 param->rodt = 1;
1494 param->reg_AC1 = 0x33302815; 1381 param->reg_AC1 = 0x33302815;
@@ -1504,7 +1391,7 @@ static void get_ddr2_info(struct ast_private *ast, struct ast2300_dram_param *pa
1504 param->dll2_finetune_step = 3; 1391 param->dll2_finetune_step = 3;
1505 break; 1392 break;
1506 case 528: 1393 case 528:
1507 moutdwm(ast, 0x1E6E2020, 0x0120); 1394 ast_moutdwm(ast, 0x1E6E2020, 0x0120);
1508 param->wodt = 1; 1395 param->wodt = 1;
1509 param->rodt = 1; 1396 param->rodt = 1;
1510 param->reg_AC1 = 0x33302815; 1397 param->reg_AC1 = 0x33302815;
@@ -1520,7 +1407,7 @@ static void get_ddr2_info(struct ast_private *ast, struct ast2300_dram_param *pa
1520 param->dll2_finetune_step = 3; 1407 param->dll2_finetune_step = 3;
1521 break; 1408 break;
1522 case 552: 1409 case 552:
1523 moutdwm(ast, 0x1E6E2020, 0x02A1); 1410 ast_moutdwm(ast, 0x1E6E2020, 0x02A1);
1524 param->wodt = 1; 1411 param->wodt = 1;
1525 param->rodt = 1; 1412 param->rodt = 1;
1526 param->reg_AC1 = 0x43402915; 1413 param->reg_AC1 = 0x43402915;
@@ -1536,7 +1423,7 @@ static void get_ddr2_info(struct ast_private *ast, struct ast2300_dram_param *pa
1536 param->dll2_finetune_step = 3; 1423 param->dll2_finetune_step = 3;
1537 break; 1424 break;
1538 case 576: 1425 case 576:
1539 moutdwm(ast, 0x1E6E2020, 0x0140); 1426 ast_moutdwm(ast, 0x1E6E2020, 0x0140);
1540 param->wodt = 1; 1427 param->wodt = 1;
1541 param->rodt = 1; 1428 param->rodt = 1;
1542 param->reg_AC1 = 0x43402915; 1429 param->reg_AC1 = 0x43402915;
@@ -1588,110 +1475,102 @@ static void get_ddr2_info(struct ast_private *ast, struct ast2300_dram_param *pa
1588 1475
1589static void ddr2_init(struct ast_private *ast, struct ast2300_dram_param *param) 1476static void ddr2_init(struct ast_private *ast, struct ast2300_dram_param *param)
1590{ 1477{
1591 u32 data, data2; 1478 u32 data, data2, retry = 0;
1592 1479
1593 moutdwm(ast, 0x1E6E0000, 0xFC600309); 1480ddr2_init_start:
1594 moutdwm(ast, 0x1E6E0018, 0x00000100); 1481 ast_moutdwm(ast, 0x1E6E0000, 0xFC600309);
1595 moutdwm(ast, 0x1E6E0024, 0x00000000); 1482 ast_moutdwm(ast, 0x1E6E0018, 0x00000100);
1596 moutdwm(ast, 0x1E6E0064, param->reg_MADJ); 1483 ast_moutdwm(ast, 0x1E6E0024, 0x00000000);
1597 moutdwm(ast, 0x1E6E0068, param->reg_SADJ); 1484 ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ);
1485 ast_moutdwm(ast, 0x1E6E0068, param->reg_SADJ);
1598 udelay(10); 1486 udelay(10);
1599 moutdwm(ast, 0x1E6E0064, param->reg_MADJ | 0xC0000); 1487 ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ | 0xC0000);
1600 udelay(10); 1488 udelay(10);
1601 1489
1602 moutdwm(ast, 0x1E6E0004, param->dram_config); 1490 ast_moutdwm(ast, 0x1E6E0004, param->dram_config);
1603 moutdwm(ast, 0x1E6E0008, 0x90040f); 1491 ast_moutdwm(ast, 0x1E6E0008, 0x90040f);
1604 moutdwm(ast, 0x1E6E0010, param->reg_AC1); 1492 ast_moutdwm(ast, 0x1E6E0010, param->reg_AC1);
1605 moutdwm(ast, 0x1E6E0014, param->reg_AC2); 1493 ast_moutdwm(ast, 0x1E6E0014, param->reg_AC2);
1606 moutdwm(ast, 0x1E6E0020, param->reg_DQSIC); 1494 ast_moutdwm(ast, 0x1E6E0020, param->reg_DQSIC);
1607 moutdwm(ast, 0x1E6E0080, 0x00000000); 1495 ast_moutdwm(ast, 0x1E6E0080, 0x00000000);
1608 moutdwm(ast, 0x1E6E0084, 0x00000000); 1496 ast_moutdwm(ast, 0x1E6E0084, 0x00000000);
1609 moutdwm(ast, 0x1E6E0088, param->reg_DQIDLY); 1497 ast_moutdwm(ast, 0x1E6E0088, param->reg_DQIDLY);
1610 moutdwm(ast, 0x1E6E0018, 0x4040A130); 1498 ast_moutdwm(ast, 0x1E6E0018, 0x4000A130);
1611 moutdwm(ast, 0x1E6E0018, 0x20402330); 1499 ast_moutdwm(ast, 0x1E6E0018, 0x00002330);
1612 moutdwm(ast, 0x1E6E0038, 0x00000000); 1500 ast_moutdwm(ast, 0x1E6E0038, 0x00000000);
1613 moutdwm(ast, 0x1E6E0040, 0xFF808000); 1501 ast_moutdwm(ast, 0x1E6E0040, 0xFF808000);
1614 moutdwm(ast, 0x1E6E0044, 0x88848466); 1502 ast_moutdwm(ast, 0x1E6E0044, 0x88848466);
1615 moutdwm(ast, 0x1E6E0048, 0x44440008); 1503 ast_moutdwm(ast, 0x1E6E0048, 0x44440008);
1616 moutdwm(ast, 0x1E6E004C, 0x00000000); 1504 ast_moutdwm(ast, 0x1E6E004C, 0x00000000);
1617 moutdwm(ast, 0x1E6E0050, 0x80000000); 1505 ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
1618 moutdwm(ast, 0x1E6E0050, 0x00000000); 1506 ast_moutdwm(ast, 0x1E6E0050, 0x00000000);
1619 moutdwm(ast, 0x1E6E0054, 0); 1507 ast_moutdwm(ast, 0x1E6E0054, 0);
1620 moutdwm(ast, 0x1E6E0060, param->reg_DRV); 1508 ast_moutdwm(ast, 0x1E6E0060, param->reg_DRV);
1621 moutdwm(ast, 0x1E6E006C, param->reg_IOZ); 1509 ast_moutdwm(ast, 0x1E6E006C, param->reg_IOZ);
1622 moutdwm(ast, 0x1E6E0070, 0x00000000); 1510 ast_moutdwm(ast, 0x1E6E0070, 0x00000000);
1623 moutdwm(ast, 0x1E6E0074, 0x00000000); 1511 ast_moutdwm(ast, 0x1E6E0074, 0x00000000);
1624 moutdwm(ast, 0x1E6E0078, 0x00000000); 1512 ast_moutdwm(ast, 0x1E6E0078, 0x00000000);
1625 moutdwm(ast, 0x1E6E007C, 0x00000000); 1513 ast_moutdwm(ast, 0x1E6E007C, 0x00000000);
1626 1514
1627 /* Wait MCLK2X lock to MCLK */ 1515 /* Wait MCLK2X lock to MCLK */
1628 do { 1516 do {
1629 data = mindwm(ast, 0x1E6E001C); 1517 data = ast_mindwm(ast, 0x1E6E001C);
1630 } while (!(data & 0x08000000)); 1518 } while (!(data & 0x08000000));
1631 moutdwm(ast, 0x1E6E0034, 0x00000001); 1519 data = ast_mindwm(ast, 0x1E6E001C);
1632 moutdwm(ast, 0x1E6E000C, 0x00005C04);
1633 udelay(10);
1634 moutdwm(ast, 0x1E6E000C, 0x00000000);
1635 moutdwm(ast, 0x1E6E0034, 0x00000000);
1636 data = mindwm(ast, 0x1E6E001C);
1637 data = (data >> 8) & 0xff; 1520 data = (data >> 8) & 0xff;
1638 while ((data & 0x08) || ((data & 0x7) < 2) || (data < 4)) { 1521 while ((data & 0x08) || ((data & 0x7) < 2) || (data < 4)) {
1639 data2 = (mindwm(ast, 0x1E6E0064) & 0xfff3ffff) + 4; 1522 data2 = (ast_mindwm(ast, 0x1E6E0064) & 0xfff3ffff) + 4;
1640 if ((data2 & 0xff) > param->madj_max) { 1523 if ((data2 & 0xff) > param->madj_max) {
1641 break; 1524 break;
1642 } 1525 }
1643 moutdwm(ast, 0x1E6E0064, data2); 1526 ast_moutdwm(ast, 0x1E6E0064, data2);
1644 if (data2 & 0x00100000) { 1527 if (data2 & 0x00100000) {
1645 data2 = ((data2 & 0xff) >> 3) + 3; 1528 data2 = ((data2 & 0xff) >> 3) + 3;
1646 } else { 1529 } else {
1647 data2 = ((data2 & 0xff) >> 2) + 5; 1530 data2 = ((data2 & 0xff) >> 2) + 5;
1648 } 1531 }
1649 data = mindwm(ast, 0x1E6E0068) & 0xffff00ff; 1532 data = ast_mindwm(ast, 0x1E6E0068) & 0xffff00ff;
1650 data2 += data & 0xff; 1533 data2 += data & 0xff;
1651 data = data | (data2 << 8); 1534 data = data | (data2 << 8);
1652 moutdwm(ast, 0x1E6E0068, data); 1535 ast_moutdwm(ast, 0x1E6E0068, data);
1653 udelay(10); 1536 udelay(10);
1654 moutdwm(ast, 0x1E6E0064, mindwm(ast, 0x1E6E0064) | 0xC0000); 1537 ast_moutdwm(ast, 0x1E6E0064, ast_mindwm(ast, 0x1E6E0064) | 0xC0000);
1655 udelay(10); 1538 udelay(10);
1656 data = mindwm(ast, 0x1E6E0018) & 0xfffff1ff; 1539 data = ast_mindwm(ast, 0x1E6E0018) & 0xfffff1ff;
1657 moutdwm(ast, 0x1E6E0018, data); 1540 ast_moutdwm(ast, 0x1E6E0018, data);
1658 data = data | 0x200; 1541 data = data | 0x200;
1659 moutdwm(ast, 0x1E6E0018, data); 1542 ast_moutdwm(ast, 0x1E6E0018, data);
1660 do { 1543 do {
1661 data = mindwm(ast, 0x1E6E001C); 1544 data = ast_mindwm(ast, 0x1E6E001C);
1662 } while (!(data & 0x08000000)); 1545 } while (!(data & 0x08000000));
1663 1546
1664 moutdwm(ast, 0x1E6E0034, 0x00000001); 1547 data = ast_mindwm(ast, 0x1E6E001C);
1665 moutdwm(ast, 0x1E6E000C, 0x00005C04);
1666 udelay(10);
1667 moutdwm(ast, 0x1E6E000C, 0x00000000);
1668 moutdwm(ast, 0x1E6E0034, 0x00000000);
1669 data = mindwm(ast, 0x1E6E001C);
1670 data = (data >> 8) & 0xff; 1548 data = (data >> 8) & 0xff;
1671 } 1549 }
1672 data = mindwm(ast, 0x1E6E0018) | 0xC00; 1550 ast_moutdwm(ast, 0x1E720058, ast_mindwm(ast, 0x1E6E0008) & 0xffff);
1673 moutdwm(ast, 0x1E6E0018, data); 1551 data = ast_mindwm(ast, 0x1E6E0018) | 0xC00;
1552 ast_moutdwm(ast, 0x1E6E0018, data);
1674 1553
1675 moutdwm(ast, 0x1E6E0034, 0x00000001); 1554 ast_moutdwm(ast, 0x1E6E0034, 0x00000001);
1676 moutdwm(ast, 0x1E6E000C, 0x00000000); 1555 ast_moutdwm(ast, 0x1E6E000C, 0x00000000);
1677 udelay(50); 1556 udelay(50);
1678 /* Mode Register Setting */ 1557 /* Mode Register Setting */
1679 moutdwm(ast, 0x1E6E002C, param->reg_MRS | 0x100); 1558 ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS | 0x100);
1680 moutdwm(ast, 0x1E6E0030, param->reg_EMRS); 1559 ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS);
1681 moutdwm(ast, 0x1E6E0028, 0x00000005); 1560 ast_moutdwm(ast, 0x1E6E0028, 0x00000005);
1682 moutdwm(ast, 0x1E6E0028, 0x00000007); 1561 ast_moutdwm(ast, 0x1E6E0028, 0x00000007);
1683 moutdwm(ast, 0x1E6E0028, 0x00000003); 1562 ast_moutdwm(ast, 0x1E6E0028, 0x00000003);
1684 moutdwm(ast, 0x1E6E0028, 0x00000001); 1563 ast_moutdwm(ast, 0x1E6E0028, 0x00000001);
1685 1564
1686 moutdwm(ast, 0x1E6E000C, 0x00005C08); 1565 ast_moutdwm(ast, 0x1E6E000C, 0x00005C08);
1687 moutdwm(ast, 0x1E6E002C, param->reg_MRS); 1566 ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS);
1688 moutdwm(ast, 0x1E6E0028, 0x00000001); 1567 ast_moutdwm(ast, 0x1E6E0028, 0x00000001);
1689 moutdwm(ast, 0x1E6E0030, param->reg_EMRS | 0x380); 1568 ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS | 0x380);
1690 moutdwm(ast, 0x1E6E0028, 0x00000003); 1569 ast_moutdwm(ast, 0x1E6E0028, 0x00000003);
1691 moutdwm(ast, 0x1E6E0030, param->reg_EMRS); 1570 ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS);
1692 moutdwm(ast, 0x1E6E0028, 0x00000003); 1571 ast_moutdwm(ast, 0x1E6E0028, 0x00000003);
1693 1572
1694 moutdwm(ast, 0x1E6E000C, 0x7FFF5C01); 1573 ast_moutdwm(ast, 0x1E6E000C, 0x7FFF5C01);
1695 data = 0; 1574 data = 0;
1696 if (param->wodt) { 1575 if (param->wodt) {
1697 data = 0x500; 1576 data = 0x500;
@@ -1699,30 +1578,23 @@ static void ddr2_init(struct ast_private *ast, struct ast2300_dram_param *param)
1699 if (param->rodt) { 1578 if (param->rodt) {
1700 data = data | 0x3000 | ((param->reg_AC2 & 0x60000) >> 3); 1579 data = data | 0x3000 | ((param->reg_AC2 & 0x60000) >> 3);
1701 } 1580 }
1702 moutdwm(ast, 0x1E6E0034, data | 0x3); 1581 ast_moutdwm(ast, 0x1E6E0034, data | 0x3);
1703 moutdwm(ast, 0x1E6E0120, param->reg_FREQ); 1582 ast_moutdwm(ast, 0x1E6E0120, param->reg_FREQ);
1704 1583
1705 /* Wait DQI delay lock */
1706 do {
1707 data = mindwm(ast, 0x1E6E0080);
1708 } while (!(data & 0x40000000));
1709 /* Wait DQSI delay lock */
1710 do {
1711 data = mindwm(ast, 0x1E6E0020);
1712 } while (!(data & 0x00000800));
1713 /* Calibrate the DQSI delay */ 1584 /* Calibrate the DQSI delay */
1714 cbr_dll2(ast, param); 1585 if ((cbr_dll2(ast, param) == false) && (retry++ < 10))
1586 goto ddr2_init_start;
1715 1587
1716 /* ECC Memory Initialization */ 1588 /* ECC Memory Initialization */
1717#ifdef ECC 1589#ifdef ECC
1718 moutdwm(ast, 0x1E6E007C, 0x00000000); 1590 ast_moutdwm(ast, 0x1E6E007C, 0x00000000);
1719 moutdwm(ast, 0x1E6E0070, 0x221); 1591 ast_moutdwm(ast, 0x1E6E0070, 0x221);
1720 do { 1592 do {
1721 data = mindwm(ast, 0x1E6E0070); 1593 data = ast_mindwm(ast, 0x1E6E0070);
1722 } while (!(data & 0x00001000)); 1594 } while (!(data & 0x00001000));
1723 moutdwm(ast, 0x1E6E0070, 0x00000000); 1595 ast_moutdwm(ast, 0x1E6E0070, 0x00000000);
1724 moutdwm(ast, 0x1E6E0050, 0x80000000); 1596 ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
1725 moutdwm(ast, 0x1E6E0050, 0x00000000); 1597 ast_moutdwm(ast, 0x1E6E0050, 0x00000000);
1726#endif 1598#endif
1727 1599
1728} 1600}
@@ -1768,8 +1640,8 @@ static void ast_init_dram_2300(struct drm_device *dev)
1768 ddr2_init(ast, &param); 1640 ddr2_init(ast, &param);
1769 } 1641 }
1770 1642
1771 temp = mindwm(ast, 0x1e6e2040); 1643 temp = ast_mindwm(ast, 0x1e6e2040);
1772 moutdwm(ast, 0x1e6e2040, temp | 0x40); 1644 ast_moutdwm(ast, 0x1e6e2040, temp | 0x40);
1773 } 1645 }
1774 1646
1775 /* wait ready */ 1647 /* wait ready */
diff --git a/drivers/gpu/drm/ast/ast_tables.h b/drivers/gpu/drm/ast/ast_tables.h
index 95fa6aba26bc..4c761dcea972 100644
--- a/drivers/gpu/drm/ast/ast_tables.h
+++ b/drivers/gpu/drm/ast/ast_tables.h
@@ -42,7 +42,7 @@
42#define HBorder 0x00000020 42#define HBorder 0x00000020
43#define VBorder 0x00000010 43#define VBorder 0x00000010
44#define WideScreenMode 0x00000100 44#define WideScreenMode 0x00000100
45 45#define NewModeInfo 0x00000200
46 46
47/* DCLK Index */ 47/* DCLK Index */
48#define VCLK25_175 0x00 48#define VCLK25_175 0x00
@@ -67,6 +67,11 @@
67#define VCLK106_5 0x12 67#define VCLK106_5 0x12
68#define VCLK146_25 0x13 68#define VCLK146_25 0x13
69#define VCLK148_5 0x14 69#define VCLK148_5 0x14
70#define VCLK71 0x15
71#define VCLK88_75 0x16
72#define VCLK119 0x17
73#define VCLK85_5 0x18
74#define VCLK97_75 0x19
70 75
71static struct ast_vbios_dclk_info dclk_table[] = { 76static struct ast_vbios_dclk_info dclk_table[] = {
72 {0x2C, 0xE7, 0x03}, /* 00: VCLK25_175 */ 77 {0x2C, 0xE7, 0x03}, /* 00: VCLK25_175 */
@@ -90,6 +95,10 @@ static struct ast_vbios_dclk_info dclk_table[] = {
90 {0x28, 0x49, 0x80}, /* 12: VCLK106.5 */ 95 {0x28, 0x49, 0x80}, /* 12: VCLK106.5 */
91 {0x37, 0x49, 0x80}, /* 13: VCLK146.25 */ 96 {0x37, 0x49, 0x80}, /* 13: VCLK146.25 */
92 {0x1f, 0x45, 0x80}, /* 14: VCLK148.5 */ 97 {0x1f, 0x45, 0x80}, /* 14: VCLK148.5 */
98 {0x47, 0x6c, 0x80}, /* 15: VCLK71 */
99 {0x25, 0x65, 0x80}, /* 16: VCLK88.75 */
100 {0x77, 0x58, 0x80}, /* 17: VCLK119 */
101 {0x32, 0x67, 0x80}, /* 18: VCLK85_5 */
93}; 102};
94 103
95static struct ast_vbios_stdtable vbios_stdtable[] = { 104static struct ast_vbios_stdtable vbios_stdtable[] = {
@@ -225,41 +234,63 @@ static struct ast_vbios_enhtable res_1600x1200[] = {
225 (SyncPP | Charx8Dot), 0xFF, 1, 0x33 }, 234 (SyncPP | Charx8Dot), 0xFF, 1, 0x33 },
226}; 235};
227 236
228static struct ast_vbios_enhtable res_1920x1200[] = { 237/* 16:9 */
229 {2080, 1920, 48, 32, 1235, 1200, 3, 6, VCLK154, /* 60Hz */ 238static struct ast_vbios_enhtable res_1360x768[] = {
230 (SyncNP | Charx8Dot), 60, 1, 0x34 }, 239 {1792, 1360, 64,112, 795, 768, 3, 6, VCLK85_5, /* 60Hz */
231 {2080, 1920, 48, 32, 1235, 1200, 3, 6, VCLK154, /* 60Hz */ 240 (SyncPP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x39 },
232 (SyncNP | Charx8Dot), 0xFF, 1, 0x34 }, 241 {1792, 1360, 64,112, 795, 768, 3, 6, VCLK85_5, /* end */
242 (SyncPP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 1, 0x39 },
243};
244
245static struct ast_vbios_enhtable res_1600x900[] = {
246 {1760, 1600, 48, 32, 926, 900, 3, 5, VCLK97_75, /* 60Hz CVT RB */
247 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x3A },
248 {1760, 1600, 48, 32, 926, 900, 3, 5, VCLK97_75, /* end */
249 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 1, 0x3A }
233}; 250};
234 251
252static struct ast_vbios_enhtable res_1920x1080[] = {
253 {2200, 1920, 88, 44, 1125, 1080, 4, 5, VCLK148_5, /* 60Hz */
254 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x38 },
255 {2200, 1920, 88, 44, 1125, 1080, 4, 5, VCLK148_5, /* 60Hz */
256 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 1, 0x38 },
257};
258
259
235/* 16:10 */ 260/* 16:10 */
236static struct ast_vbios_enhtable res_1280x800[] = { 261static struct ast_vbios_enhtable res_1280x800[] = {
262 {1440, 1280, 48, 32, 823, 800, 3, 6, VCLK71, /* 60Hz RB */
263 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 35 },
237 {1680, 1280, 72,128, 831, 800, 3, 6, VCLK83_5, /* 60Hz */ 264 {1680, 1280, 72,128, 831, 800, 3, 6, VCLK83_5, /* 60Hz */
238 (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode), 60, 1, 0x35 }, 265 (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x35 },
239 {1680, 1280, 72,128, 831, 800, 3, 6, VCLK83_5, /* 60Hz */ 266 {1680, 1280, 72,128, 831, 800, 3, 6, VCLK83_5, /* 60Hz */
240 (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode), 0xFF, 1, 0x35 }, 267 (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 1, 0x35 },
241 268
242}; 269};
243 270
244static struct ast_vbios_enhtable res_1440x900[] = { 271static struct ast_vbios_enhtable res_1440x900[] = {
272 {1600, 1440, 48, 32, 926, 900, 3, 6, VCLK88_75, /* 60Hz RB */
273 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x36 },
245 {1904, 1440, 80,152, 934, 900, 3, 6, VCLK106_5, /* 60Hz */ 274 {1904, 1440, 80,152, 934, 900, 3, 6, VCLK106_5, /* 60Hz */
246 (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode), 60, 1, 0x36 }, 275 (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x36 },
247 {1904, 1440, 80,152, 934, 900, 3, 6, VCLK106_5, /* 60Hz */ 276 {1904, 1440, 80,152, 934, 900, 3, 6, VCLK106_5, /* 60Hz */
248 (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode), 0xFF, 1, 0x36 }, 277 (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 1, 0x36 },
249}; 278};
250 279
251static struct ast_vbios_enhtable res_1680x1050[] = { 280static struct ast_vbios_enhtable res_1680x1050[] = {
281 {1840, 1680, 48, 32, 1080, 1050, 3, 6, VCLK119, /* 60Hz RB */
282 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x37 },
252 {2240, 1680,104,176, 1089, 1050, 3, 6, VCLK146_25, /* 60Hz */ 283 {2240, 1680,104,176, 1089, 1050, 3, 6, VCLK146_25, /* 60Hz */
253 (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode), 60, 1, 0x37 }, 284 (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x37 },
254 {2240, 1680,104,176, 1089, 1050, 3, 6, VCLK146_25, /* 60Hz */ 285 {2240, 1680,104,176, 1089, 1050, 3, 6, VCLK146_25, /* 60Hz */
255 (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode), 0xFF, 1, 0x37 }, 286 (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 1, 0x37 },
256}; 287};
257 288
258/* HDTV */ 289static struct ast_vbios_enhtable res_1920x1200[] = {
259static struct ast_vbios_enhtable res_1920x1080[] = { 290 {2080, 1920, 48, 32, 1235, 1200, 3, 6, VCLK154, /* 60Hz */
260 {2200, 1920, 88, 44, 1125, 1080, 4, 5, VCLK148_5, /* 60Hz */ 291 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x34 },
261 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode), 60, 1, 0x38 }, 292 {2080, 1920, 48, 32, 1235, 1200, 3, 6, VCLK154, /* 60Hz */
262 {2200, 1920, 88, 44, 1125, 1080, 4, 5, VCLK148_5, /* 60Hz */ 293 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 1, 0x34 },
263 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode), 0xFF, 1, 0x38 },
264}; 294};
295
265#endif 296#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-18 14:15:10 -0500