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authorMarkus Mayer <markus.mayer@linaro.org>2014-01-21 19:10:04 -0500
committerLinus Walleij <linus.walleij@linaro.org>2014-02-06 04:33:45 -0500
commitd762bae45a3dd65d02a35b4252598912f7fbcde0 (patch)
tree2018ca632c29dba416b1eeed43a8d275e6ab1d0f /drivers/gpio
parenta0bbf03270fde9d96a9f814512e77a693648e159 (diff)
gpio: bcm281xx: Fix parameter name for GPIO_CONTROL macro
The GPIO_CONTROL macro returns the control register offset when given a GPIO number. Update the argument name in the macro to reflect that it takes in a GPIO number and not a bank. Signed-off-by: Markus Mayer <markus.mayer@linaro.org> Reviewed-by: Tim Kryger <tim.kryger@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/gpio')
-rw-r--r--drivers/gpio/gpio-bcm-kona.c5
1 files changed, 4 insertions, 1 deletions
diff --git a/drivers/gpio/gpio-bcm-kona.c b/drivers/gpio/gpio-bcm-kona.c
index 233d088ac59f..93a5b010f1e1 100644
--- a/drivers/gpio/gpio-bcm-kona.c
+++ b/drivers/gpio/gpio-bcm-kona.c
@@ -28,6 +28,10 @@
28#define GPIO_BANK(gpio) ((gpio) >> 5) 28#define GPIO_BANK(gpio) ((gpio) >> 5)
29#define GPIO_BIT(gpio) ((gpio) & (GPIO_PER_BANK - 1)) 29#define GPIO_BIT(gpio) ((gpio) & (GPIO_PER_BANK - 1))
30 30
31/* There is a GPIO control register for each GPIO */
32#define GPIO_CONTROL(gpio) (0x00000100 + ((gpio) << 2))
33
34/* The remaining registers are per GPIO bank */
31#define GPIO_OUT_STATUS(bank) (0x00000000 + ((bank) << 2)) 35#define GPIO_OUT_STATUS(bank) (0x00000000 + ((bank) << 2))
32#define GPIO_IN_STATUS(bank) (0x00000020 + ((bank) << 2)) 36#define GPIO_IN_STATUS(bank) (0x00000020 + ((bank) << 2))
33#define GPIO_OUT_SET(bank) (0x00000040 + ((bank) << 2)) 37#define GPIO_OUT_SET(bank) (0x00000040 + ((bank) << 2))
@@ -35,7 +39,6 @@
35#define GPIO_INT_STATUS(bank) (0x00000080 + ((bank) << 2)) 39#define GPIO_INT_STATUS(bank) (0x00000080 + ((bank) << 2))
36#define GPIO_INT_MASK(bank) (0x000000a0 + ((bank) << 2)) 40#define GPIO_INT_MASK(bank) (0x000000a0 + ((bank) << 2))
37#define GPIO_INT_MSKCLR(bank) (0x000000c0 + ((bank) << 2)) 41#define GPIO_INT_MSKCLR(bank) (0x000000c0 + ((bank) << 2))
38#define GPIO_CONTROL(bank) (0x00000100 + ((bank) << 2))
39#define GPIO_PWD_STATUS(bank) (0x00000500 + ((bank) << 2)) 42#define GPIO_PWD_STATUS(bank) (0x00000500 + ((bank) << 2))
40 43
41#define GPIO_GPPWR_OFFSET 0x00000520 44#define GPIO_GPPWR_OFFSET 0x00000520