diff options
author | Tomoya MORINAGA <tomoya-linux@dsn.okisemi.com> | 2011-07-20 20:19:57 -0400 |
---|---|---|
committer | Grant Likely <grant.likely@secretlab.ca> | 2011-10-05 13:59:17 -0400 |
commit | d4260e6dddfe642ab50ec6398aeac794a6aff151 (patch) | |
tree | 4d6e0f7f6552ea3071f7c4a2897e534c58a38ea9 /drivers/gpio | |
parent | c3520a1a84f13becf7489ddee4571eaccf108934 (diff) |
gpio-pch: modify gpio_nums and mask
Currently, the number of GPIO pins is set fixed value(=12).
Also PIN MASK is set as '0xfff'.
However the pins differs by IOH.
This patch sets the value correctly.
Signed-off-by: Tomoya MORINAGA <tomoya-linux@dsn.okisemi.com>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Diffstat (limited to 'drivers/gpio')
-rw-r--r-- | drivers/gpio/gpio-pch.c | 31 |
1 files changed, 25 insertions, 6 deletions
diff --git a/drivers/gpio/gpio-pch.c b/drivers/gpio/gpio-pch.c index d548069d3912..4ac69bd7ad4a 100644 --- a/drivers/gpio/gpio-pch.c +++ b/drivers/gpio/gpio-pch.c | |||
@@ -18,9 +18,6 @@ | |||
18 | #include <linux/pci.h> | 18 | #include <linux/pci.h> |
19 | #include <linux/gpio.h> | 19 | #include <linux/gpio.h> |
20 | 20 | ||
21 | #define PCH_GPIO_ALL_PINS 0xfff /* Mask for GPIO pins 0 to 11 */ | ||
22 | #define GPIO_NUM_PINS 12 /* Specifies number of GPIO PINS GPIO0-GPIO11 */ | ||
23 | |||
24 | struct pch_regs { | 21 | struct pch_regs { |
25 | u32 ien; | 22 | u32 ien; |
26 | u32 istatus; | 23 | u32 istatus; |
@@ -37,6 +34,19 @@ struct pch_regs { | |||
37 | u32 reset; | 34 | u32 reset; |
38 | }; | 35 | }; |
39 | 36 | ||
37 | enum pch_type_t { | ||
38 | INTEL_EG20T_PCH, | ||
39 | OKISEMI_ML7223m_IOH, /* OKISEMI ML7223 IOH PCIe Bus-m */ | ||
40 | OKISEMI_ML7223n_IOH /* OKISEMI ML7223 IOH PCIe Bus-n */ | ||
41 | }; | ||
42 | |||
43 | /* Specifies number of GPIO PINS */ | ||
44 | static int gpio_pins[] = { | ||
45 | [INTEL_EG20T_PCH] = 12, | ||
46 | [OKISEMI_ML7223m_IOH] = 8, | ||
47 | [OKISEMI_ML7223n_IOH] = 8, | ||
48 | }; | ||
49 | |||
40 | /** | 50 | /** |
41 | * struct pch_gpio_reg_data - The register store data. | 51 | * struct pch_gpio_reg_data - The register store data. |
42 | * @po_reg: To store contents of PO register. | 52 | * @po_reg: To store contents of PO register. |
@@ -55,6 +65,7 @@ struct pch_gpio_reg_data { | |||
55 | * @gpio: Data for GPIO infrastructure. | 65 | * @gpio: Data for GPIO infrastructure. |
56 | * @pch_gpio_reg: Memory mapped Register data is saved here | 66 | * @pch_gpio_reg: Memory mapped Register data is saved here |
57 | * when suspend. | 67 | * when suspend. |
68 | * @ioh: IOH ID | ||
58 | * @spinlock: Used for register access protection in | 69 | * @spinlock: Used for register access protection in |
59 | * interrupt context pch_irq_mask, | 70 | * interrupt context pch_irq_mask, |
60 | * pch_irq_unmask and pch_irq_type; | 71 | * pch_irq_unmask and pch_irq_type; |
@@ -66,6 +77,7 @@ struct pch_gpio { | |||
66 | struct gpio_chip gpio; | 77 | struct gpio_chip gpio; |
67 | struct pch_gpio_reg_data pch_gpio_reg; | 78 | struct pch_gpio_reg_data pch_gpio_reg; |
68 | struct mutex lock; | 79 | struct mutex lock; |
80 | enum pch_type_t ioh; | ||
69 | spinlock_t spinlock; | 81 | spinlock_t spinlock; |
70 | }; | 82 | }; |
71 | 83 | ||
@@ -100,7 +112,7 @@ static int pch_gpio_direction_output(struct gpio_chip *gpio, unsigned nr, | |||
100 | u32 reg_val; | 112 | u32 reg_val; |
101 | 113 | ||
102 | mutex_lock(&chip->lock); | 114 | mutex_lock(&chip->lock); |
103 | pm = ioread32(&chip->reg->pm) & PCH_GPIO_ALL_PINS; | 115 | pm = ioread32(&chip->reg->pm) & ((1 << gpio_pins[chip->ioh]) - 1); |
104 | pm |= (1 << nr); | 116 | pm |= (1 << nr); |
105 | iowrite32(pm, &chip->reg->pm); | 117 | iowrite32(pm, &chip->reg->pm); |
106 | 118 | ||
@@ -122,7 +134,7 @@ static int pch_gpio_direction_input(struct gpio_chip *gpio, unsigned nr) | |||
122 | u32 pm; | 134 | u32 pm; |
123 | 135 | ||
124 | mutex_lock(&chip->lock); | 136 | mutex_lock(&chip->lock); |
125 | pm = ioread32(&chip->reg->pm) & PCH_GPIO_ALL_PINS; /*bits 0-11*/ | 137 | pm = ioread32(&chip->reg->pm) & ((1 << gpio_pins[chip->ioh]) - 1); |
126 | pm &= ~(1 << nr); | 138 | pm &= ~(1 << nr); |
127 | iowrite32(pm, &chip->reg->pm); | 139 | iowrite32(pm, &chip->reg->pm); |
128 | mutex_unlock(&chip->lock); | 140 | mutex_unlock(&chip->lock); |
@@ -162,7 +174,7 @@ static void pch_gpio_setup(struct pch_gpio *chip) | |||
162 | gpio->set = pch_gpio_set; | 174 | gpio->set = pch_gpio_set; |
163 | gpio->dbg_show = NULL; | 175 | gpio->dbg_show = NULL; |
164 | gpio->base = -1; | 176 | gpio->base = -1; |
165 | gpio->ngpio = GPIO_NUM_PINS; | 177 | gpio->ngpio = gpio_pins[chip->ioh]; |
166 | gpio->can_sleep = 0; | 178 | gpio->can_sleep = 0; |
167 | } | 179 | } |
168 | 180 | ||
@@ -196,6 +208,13 @@ static int __devinit pch_gpio_probe(struct pci_dev *pdev, | |||
196 | goto err_iomap; | 208 | goto err_iomap; |
197 | } | 209 | } |
198 | 210 | ||
211 | if (pdev->device == 0x8803) | ||
212 | chip->ioh = INTEL_EG20T_PCH; | ||
213 | else if (pdev->device == 0x8014) | ||
214 | chip->ioh = OKISEMI_ML7223m_IOH; | ||
215 | else if (pdev->device == 0x8043) | ||
216 | chip->ioh = OKISEMI_ML7223n_IOH; | ||
217 | |||
199 | chip->reg = chip->base; | 218 | chip->reg = chip->base; |
200 | pci_set_drvdata(pdev, chip); | 219 | pci_set_drvdata(pdev, chip); |
201 | mutex_init(&chip->lock); | 220 | mutex_init(&chip->lock); |