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authorVincent Donnefort <vdonnefort@gmail.com>2014-02-14 09:01:58 -0500
committerLee Jones <lee.jones@linaro.org>2014-03-19 04:58:23 -0400
commit3b9231893e5731e2212645a92f1d3d0776c58e1a (patch)
treeb76f357ab5d09156e4ef837cd6f809f4faca2dc2 /drivers/gpio
parente6540f332447b2fe5c2cd8774890c80f29fe5c75 (diff)
gpio: ich: Add support for Intel Avoton
This patch adds support for Atom C2000 series (Avoton and Rangeley). And has the following options: - New addresses register. - Caching output levels (see Intel external design spec, table 48-29) - No hardware blink. Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Vincent Donnefort <vdonnefort@gmail.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
Diffstat (limited to 'drivers/gpio')
-rw-r--r--drivers/gpio/gpio-ich.c26
1 files changed, 25 insertions, 1 deletions
diff --git a/drivers/gpio/gpio-ich.c b/drivers/gpio/gpio-ich.c
index bfef20f8ab48..e73c6755a5eb 100644
--- a/drivers/gpio/gpio-ich.c
+++ b/drivers/gpio/gpio-ich.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Intel ICH6-10, Series 5 and 6 GPIO driver 2 * Intel ICH6-10, Series 5 and 6, Atom C2000 (Avoton/Rangeley) GPIO driver
3 * 3 *
4 * Copyright (C) 2010 Extreme Engineering Solutions. 4 * Copyright (C) 2010 Extreme Engineering Solutions.
5 * 5 *
@@ -55,6 +55,16 @@ static const u8 ichx_reglen[3] = {
55 0x30, 0x10, 0x10, 55 0x30, 0x10, 0x10,
56}; 56};
57 57
58static const u8 avoton_regs[4][3] = {
59 {0x00, 0x80, 0x00},
60 {0x04, 0x84, 0x00},
61 {0x08, 0x88, 0x00},
62};
63
64static const u8 avoton_reglen[3] = {
65 0x10, 0x10, 0x00,
66};
67
58#define ICHX_WRITE(val, reg, base_res) outl(val, (reg) + (base_res)->start) 68#define ICHX_WRITE(val, reg, base_res) outl(val, (reg) + (base_res)->start)
59#define ICHX_READ(reg, base_res) inl((reg) + (base_res)->start) 69#define ICHX_READ(reg, base_res) inl((reg) + (base_res)->start)
60 70
@@ -353,6 +363,17 @@ static struct ichx_desc intel5_desc = {
353 .reglen = ichx_reglen, 363 .reglen = ichx_reglen,
354}; 364};
355 365
366/* Avoton */
367static struct ichx_desc avoton_desc = {
368 /* Avoton has only 59 GPIOs, but we assume the first set of register
369 * (Core) has 32 instead of 31 to keep gpio-ich compliance
370 */
371 .ngpio = 60,
372 .regs = avoton_regs,
373 .reglen = avoton_reglen,
374 .use_outlvl_cache = true,
375};
376
356static int ichx_gpio_request_regions(struct resource *res_base, 377static int ichx_gpio_request_regions(struct resource *res_base,
357 const char *name, u8 use_gpio) 378 const char *name, u8 use_gpio)
358{ 379{
@@ -427,6 +448,9 @@ static int ichx_gpio_probe(struct platform_device *pdev)
427 case ICH_V10CONS_GPIO: 448 case ICH_V10CONS_GPIO:
428 ichx_priv.desc = &ich10_cons_desc; 449 ichx_priv.desc = &ich10_cons_desc;
429 break; 450 break;
451 case AVOTON_GPIO:
452 ichx_priv.desc = &avoton_desc;
453 break;
430 default: 454 default:
431 return -ENODEV; 455 return -ENODEV;
432 } 456 }