diff options
author | Kukjin Kim <kgene.kim@samsung.com> | 2011-10-04 05:57:43 -0400 |
---|---|---|
committer | Kukjin Kim <kgene.kim@samsung.com> | 2011-10-04 05:57:43 -0400 |
commit | 22be71ea8bf7e9f907e916bf9f6c2bbea9f42553 (patch) | |
tree | edf517ccf09aec82c6a30e69ef885a785fa77167 /drivers/gpio | |
parent | 59ca37f74a6e9d3e9367359f2fcbb286df7d9748 (diff) | |
parent | b391f8cf606679e97b02e3b9dca8a1d9956a5301 (diff) |
Merge branch 'next/topic-gpio-samsung' into next-samsung-devel
Diffstat (limited to 'drivers/gpio')
-rw-r--r-- | drivers/gpio/Kconfig | 16 | ||||
-rw-r--r-- | drivers/gpio/Makefile | 7 | ||||
-rw-r--r-- | drivers/gpio/gpio-exynos4.c | 385 | ||||
-rw-r--r-- | drivers/gpio/gpio-plat-samsung.c | 205 | ||||
-rw-r--r-- | drivers/gpio/gpio-s5pc100.c | 354 | ||||
-rw-r--r-- | drivers/gpio/gpio-s5pv210.c | 287 | ||||
-rw-r--r-- | drivers/gpio/gpio-samsung.c | 2688 |
7 files changed, 2689 insertions, 1253 deletions
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index d539efd96d4b..ca44d2cceb02 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig | |||
@@ -95,10 +95,6 @@ config GPIO_EP93XX | |||
95 | depends on ARCH_EP93XX | 95 | depends on ARCH_EP93XX |
96 | select GPIO_GENERIC | 96 | select GPIO_GENERIC |
97 | 97 | ||
98 | config GPIO_EXYNOS4 | ||
99 | def_bool y | ||
100 | depends on CPU_EXYNOS4210 | ||
101 | |||
102 | config GPIO_MPC5200 | 98 | config GPIO_MPC5200 |
103 | def_bool y | 99 | def_bool y |
104 | depends on PPC_MPC52xx | 100 | depends on PPC_MPC52xx |
@@ -131,18 +127,6 @@ config GPIO_MXS | |||
131 | select GPIO_GENERIC | 127 | select GPIO_GENERIC |
132 | select GENERIC_IRQ_CHIP | 128 | select GENERIC_IRQ_CHIP |
133 | 129 | ||
134 | config GPIO_PLAT_SAMSUNG | ||
135 | def_bool y | ||
136 | depends on SAMSUNG_GPIOLIB_4BIT | ||
137 | |||
138 | config GPIO_S5PC100 | ||
139 | def_bool y | ||
140 | depends on CPU_S5PC100 | ||
141 | |||
142 | config GPIO_S5PV210 | ||
143 | def_bool y | ||
144 | depends on CPU_S5PV210 | ||
145 | |||
146 | config GPIO_PL061 | 130 | config GPIO_PL061 |
147 | bool "PrimeCell PL061 GPIO support" | 131 | bool "PrimeCell PL061 GPIO support" |
148 | depends on ARM_AMBA | 132 | depends on ARM_AMBA |
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 9588948c96f0..62db458c850d 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile | |||
@@ -15,7 +15,6 @@ obj-$(CONFIG_GPIO_BT8XX) += gpio-bt8xx.o | |||
15 | obj-$(CONFIG_GPIO_CS5535) += gpio-cs5535.o | 15 | obj-$(CONFIG_GPIO_CS5535) += gpio-cs5535.o |
16 | obj-$(CONFIG_GPIO_DA9052) += gpio-da9052.o | 16 | obj-$(CONFIG_GPIO_DA9052) += gpio-da9052.o |
17 | obj-$(CONFIG_GPIO_EP93XX) += gpio-ep93xx.o | 17 | obj-$(CONFIG_GPIO_EP93XX) += gpio-ep93xx.o |
18 | obj-$(CONFIG_GPIO_EXYNOS4) += gpio-exynos4.o | ||
19 | obj-$(CONFIG_GPIO_IT8761E) += gpio-it8761e.o | 18 | obj-$(CONFIG_GPIO_IT8761E) += gpio-it8761e.o |
20 | obj-$(CONFIG_GPIO_JANZ_TTL) += gpio-janz-ttl.o | 19 | obj-$(CONFIG_GPIO_JANZ_TTL) += gpio-janz-ttl.o |
21 | obj-$(CONFIG_GPIO_LANGWELL) += gpio-langwell.o | 20 | obj-$(CONFIG_GPIO_LANGWELL) += gpio-langwell.o |
@@ -38,11 +37,7 @@ obj-$(CONFIG_GPIO_PCF857X) += gpio-pcf857x.o | |||
38 | obj-$(CONFIG_GPIO_PCH) += gpio-pch.o | 37 | obj-$(CONFIG_GPIO_PCH) += gpio-pch.o |
39 | obj-$(CONFIG_GPIO_PL061) += gpio-pl061.o | 38 | obj-$(CONFIG_GPIO_PL061) += gpio-pl061.o |
40 | obj-$(CONFIG_GPIO_RDC321X) += gpio-rdc321x.o | 39 | obj-$(CONFIG_GPIO_RDC321X) += gpio-rdc321x.o |
41 | 40 | obj-$(CONFIG_PLAT_SAMSUNG) += gpio-samsung.o | |
42 | obj-$(CONFIG_GPIO_PLAT_SAMSUNG) += gpio-plat-samsung.o | ||
43 | obj-$(CONFIG_GPIO_S5PC100) += gpio-s5pc100.o | ||
44 | obj-$(CONFIG_GPIO_S5PV210) += gpio-s5pv210.o | ||
45 | |||
46 | obj-$(CONFIG_GPIO_SCH) += gpio-sch.o | 41 | obj-$(CONFIG_GPIO_SCH) += gpio-sch.o |
47 | obj-$(CONFIG_GPIO_STMPE) += gpio-stmpe.o | 42 | obj-$(CONFIG_GPIO_STMPE) += gpio-stmpe.o |
48 | obj-$(CONFIG_GPIO_SX150X) += gpio-sx150x.o | 43 | obj-$(CONFIG_GPIO_SX150X) += gpio-sx150x.o |
diff --git a/drivers/gpio/gpio-exynos4.c b/drivers/gpio/gpio-exynos4.c deleted file mode 100644 index d24b337cf1ac..000000000000 --- a/drivers/gpio/gpio-exynos4.c +++ /dev/null | |||
@@ -1,385 +0,0 @@ | |||
1 | /* | ||
2 | * EXYNOS4 - GPIOlib support | ||
3 | * | ||
4 | * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. | ||
5 | * http://www.samsung.com | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License version 2 as | ||
9 | * published by the Free Software Foundation. | ||
10 | */ | ||
11 | |||
12 | #include <linux/kernel.h> | ||
13 | #include <linux/irq.h> | ||
14 | #include <linux/io.h> | ||
15 | #include <linux/gpio.h> | ||
16 | |||
17 | #include <mach/map.h> | ||
18 | |||
19 | #include <plat/gpio-core.h> | ||
20 | #include <plat/gpio-cfg.h> | ||
21 | #include <plat/gpio-cfg-helpers.h> | ||
22 | |||
23 | int s3c_gpio_setpull_exynos4(struct s3c_gpio_chip *chip, | ||
24 | unsigned int off, s3c_gpio_pull_t pull) | ||
25 | { | ||
26 | if (pull == S3C_GPIO_PULL_UP) | ||
27 | pull = 3; | ||
28 | |||
29 | return s3c_gpio_setpull_updown(chip, off, pull); | ||
30 | } | ||
31 | |||
32 | s3c_gpio_pull_t s3c_gpio_getpull_exynos4(struct s3c_gpio_chip *chip, | ||
33 | unsigned int off) | ||
34 | { | ||
35 | s3c_gpio_pull_t pull; | ||
36 | |||
37 | pull = s3c_gpio_getpull_updown(chip, off); | ||
38 | if (pull == 3) | ||
39 | pull = S3C_GPIO_PULL_UP; | ||
40 | |||
41 | return pull; | ||
42 | } | ||
43 | |||
44 | static struct s3c_gpio_cfg gpio_cfg = { | ||
45 | .set_config = s3c_gpio_setcfg_s3c64xx_4bit, | ||
46 | .set_pull = s3c_gpio_setpull_exynos4, | ||
47 | .get_pull = s3c_gpio_getpull_exynos4, | ||
48 | }; | ||
49 | |||
50 | static struct s3c_gpio_cfg gpio_cfg_noint = { | ||
51 | .set_config = s3c_gpio_setcfg_s3c64xx_4bit, | ||
52 | .set_pull = s3c_gpio_setpull_exynos4, | ||
53 | .get_pull = s3c_gpio_getpull_exynos4, | ||
54 | }; | ||
55 | |||
56 | /* | ||
57 | * Following are the gpio banks in v310. | ||
58 | * | ||
59 | * The 'config' member when left to NULL, is initialized to the default | ||
60 | * structure gpio_cfg in the init function below. | ||
61 | * | ||
62 | * The 'base' member is also initialized in the init function below. | ||
63 | * Note: The initialization of 'base' member of s3c_gpio_chip structure | ||
64 | * uses the above macro and depends on the banks being listed in order here. | ||
65 | */ | ||
66 | static struct s3c_gpio_chip exynos4_gpio_part1_4bit[] = { | ||
67 | { | ||
68 | .chip = { | ||
69 | .base = EXYNOS4_GPA0(0), | ||
70 | .ngpio = EXYNOS4_GPIO_A0_NR, | ||
71 | .label = "GPA0", | ||
72 | }, | ||
73 | }, { | ||
74 | .chip = { | ||
75 | .base = EXYNOS4_GPA1(0), | ||
76 | .ngpio = EXYNOS4_GPIO_A1_NR, | ||
77 | .label = "GPA1", | ||
78 | }, | ||
79 | }, { | ||
80 | .chip = { | ||
81 | .base = EXYNOS4_GPB(0), | ||
82 | .ngpio = EXYNOS4_GPIO_B_NR, | ||
83 | .label = "GPB", | ||
84 | }, | ||
85 | }, { | ||
86 | .chip = { | ||
87 | .base = EXYNOS4_GPC0(0), | ||
88 | .ngpio = EXYNOS4_GPIO_C0_NR, | ||
89 | .label = "GPC0", | ||
90 | }, | ||
91 | }, { | ||
92 | .chip = { | ||
93 | .base = EXYNOS4_GPC1(0), | ||
94 | .ngpio = EXYNOS4_GPIO_C1_NR, | ||
95 | .label = "GPC1", | ||
96 | }, | ||
97 | }, { | ||
98 | .chip = { | ||
99 | .base = EXYNOS4_GPD0(0), | ||
100 | .ngpio = EXYNOS4_GPIO_D0_NR, | ||
101 | .label = "GPD0", | ||
102 | }, | ||
103 | }, { | ||
104 | .chip = { | ||
105 | .base = EXYNOS4_GPD1(0), | ||
106 | .ngpio = EXYNOS4_GPIO_D1_NR, | ||
107 | .label = "GPD1", | ||
108 | }, | ||
109 | }, { | ||
110 | .chip = { | ||
111 | .base = EXYNOS4_GPE0(0), | ||
112 | .ngpio = EXYNOS4_GPIO_E0_NR, | ||
113 | .label = "GPE0", | ||
114 | }, | ||
115 | }, { | ||
116 | .chip = { | ||
117 | .base = EXYNOS4_GPE1(0), | ||
118 | .ngpio = EXYNOS4_GPIO_E1_NR, | ||
119 | .label = "GPE1", | ||
120 | }, | ||
121 | }, { | ||
122 | .chip = { | ||
123 | .base = EXYNOS4_GPE2(0), | ||
124 | .ngpio = EXYNOS4_GPIO_E2_NR, | ||
125 | .label = "GPE2", | ||
126 | }, | ||
127 | }, { | ||
128 | .chip = { | ||
129 | .base = EXYNOS4_GPE3(0), | ||
130 | .ngpio = EXYNOS4_GPIO_E3_NR, | ||
131 | .label = "GPE3", | ||
132 | }, | ||
133 | }, { | ||
134 | .chip = { | ||
135 | .base = EXYNOS4_GPE4(0), | ||
136 | .ngpio = EXYNOS4_GPIO_E4_NR, | ||
137 | .label = "GPE4", | ||
138 | }, | ||
139 | }, { | ||
140 | .chip = { | ||
141 | .base = EXYNOS4_GPF0(0), | ||
142 | .ngpio = EXYNOS4_GPIO_F0_NR, | ||
143 | .label = "GPF0", | ||
144 | }, | ||
145 | }, { | ||
146 | .chip = { | ||
147 | .base = EXYNOS4_GPF1(0), | ||
148 | .ngpio = EXYNOS4_GPIO_F1_NR, | ||
149 | .label = "GPF1", | ||
150 | }, | ||
151 | }, { | ||
152 | .chip = { | ||
153 | .base = EXYNOS4_GPF2(0), | ||
154 | .ngpio = EXYNOS4_GPIO_F2_NR, | ||
155 | .label = "GPF2", | ||
156 | }, | ||
157 | }, { | ||
158 | .chip = { | ||
159 | .base = EXYNOS4_GPF3(0), | ||
160 | .ngpio = EXYNOS4_GPIO_F3_NR, | ||
161 | .label = "GPF3", | ||
162 | }, | ||
163 | }, | ||
164 | }; | ||
165 | |||
166 | static struct s3c_gpio_chip exynos4_gpio_part2_4bit[] = { | ||
167 | { | ||
168 | .chip = { | ||
169 | .base = EXYNOS4_GPJ0(0), | ||
170 | .ngpio = EXYNOS4_GPIO_J0_NR, | ||
171 | .label = "GPJ0", | ||
172 | }, | ||
173 | }, { | ||
174 | .chip = { | ||
175 | .base = EXYNOS4_GPJ1(0), | ||
176 | .ngpio = EXYNOS4_GPIO_J1_NR, | ||
177 | .label = "GPJ1", | ||
178 | }, | ||
179 | }, { | ||
180 | .chip = { | ||
181 | .base = EXYNOS4_GPK0(0), | ||
182 | .ngpio = EXYNOS4_GPIO_K0_NR, | ||
183 | .label = "GPK0", | ||
184 | }, | ||
185 | }, { | ||
186 | .chip = { | ||
187 | .base = EXYNOS4_GPK1(0), | ||
188 | .ngpio = EXYNOS4_GPIO_K1_NR, | ||
189 | .label = "GPK1", | ||
190 | }, | ||
191 | }, { | ||
192 | .chip = { | ||
193 | .base = EXYNOS4_GPK2(0), | ||
194 | .ngpio = EXYNOS4_GPIO_K2_NR, | ||
195 | .label = "GPK2", | ||
196 | }, | ||
197 | }, { | ||
198 | .chip = { | ||
199 | .base = EXYNOS4_GPK3(0), | ||
200 | .ngpio = EXYNOS4_GPIO_K3_NR, | ||
201 | .label = "GPK3", | ||
202 | }, | ||
203 | }, { | ||
204 | .chip = { | ||
205 | .base = EXYNOS4_GPL0(0), | ||
206 | .ngpio = EXYNOS4_GPIO_L0_NR, | ||
207 | .label = "GPL0", | ||
208 | }, | ||
209 | }, { | ||
210 | .chip = { | ||
211 | .base = EXYNOS4_GPL1(0), | ||
212 | .ngpio = EXYNOS4_GPIO_L1_NR, | ||
213 | .label = "GPL1", | ||
214 | }, | ||
215 | }, { | ||
216 | .chip = { | ||
217 | .base = EXYNOS4_GPL2(0), | ||
218 | .ngpio = EXYNOS4_GPIO_L2_NR, | ||
219 | .label = "GPL2", | ||
220 | }, | ||
221 | }, { | ||
222 | .config = &gpio_cfg_noint, | ||
223 | .chip = { | ||
224 | .base = EXYNOS4_GPY0(0), | ||
225 | .ngpio = EXYNOS4_GPIO_Y0_NR, | ||
226 | .label = "GPY0", | ||
227 | }, | ||
228 | }, { | ||
229 | .config = &gpio_cfg_noint, | ||
230 | .chip = { | ||
231 | .base = EXYNOS4_GPY1(0), | ||
232 | .ngpio = EXYNOS4_GPIO_Y1_NR, | ||
233 | .label = "GPY1", | ||
234 | }, | ||
235 | }, { | ||
236 | .config = &gpio_cfg_noint, | ||
237 | .chip = { | ||
238 | .base = EXYNOS4_GPY2(0), | ||
239 | .ngpio = EXYNOS4_GPIO_Y2_NR, | ||
240 | .label = "GPY2", | ||
241 | }, | ||
242 | }, { | ||
243 | .config = &gpio_cfg_noint, | ||
244 | .chip = { | ||
245 | .base = EXYNOS4_GPY3(0), | ||
246 | .ngpio = EXYNOS4_GPIO_Y3_NR, | ||
247 | .label = "GPY3", | ||
248 | }, | ||
249 | }, { | ||
250 | .config = &gpio_cfg_noint, | ||
251 | .chip = { | ||
252 | .base = EXYNOS4_GPY4(0), | ||
253 | .ngpio = EXYNOS4_GPIO_Y4_NR, | ||
254 | .label = "GPY4", | ||
255 | }, | ||
256 | }, { | ||
257 | .config = &gpio_cfg_noint, | ||
258 | .chip = { | ||
259 | .base = EXYNOS4_GPY5(0), | ||
260 | .ngpio = EXYNOS4_GPIO_Y5_NR, | ||
261 | .label = "GPY5", | ||
262 | }, | ||
263 | }, { | ||
264 | .config = &gpio_cfg_noint, | ||
265 | .chip = { | ||
266 | .base = EXYNOS4_GPY6(0), | ||
267 | .ngpio = EXYNOS4_GPIO_Y6_NR, | ||
268 | .label = "GPY6", | ||
269 | }, | ||
270 | }, { | ||
271 | .base = (S5P_VA_GPIO2 + 0xC00), | ||
272 | .config = &gpio_cfg_noint, | ||
273 | .irq_base = IRQ_EINT(0), | ||
274 | .chip = { | ||
275 | .base = EXYNOS4_GPX0(0), | ||
276 | .ngpio = EXYNOS4_GPIO_X0_NR, | ||
277 | .label = "GPX0", | ||
278 | .to_irq = samsung_gpiolib_to_irq, | ||
279 | }, | ||
280 | }, { | ||
281 | .base = (S5P_VA_GPIO2 + 0xC20), | ||
282 | .config = &gpio_cfg_noint, | ||
283 | .irq_base = IRQ_EINT(8), | ||
284 | .chip = { | ||
285 | .base = EXYNOS4_GPX1(0), | ||
286 | .ngpio = EXYNOS4_GPIO_X1_NR, | ||
287 | .label = "GPX1", | ||
288 | .to_irq = samsung_gpiolib_to_irq, | ||
289 | }, | ||
290 | }, { | ||
291 | .base = (S5P_VA_GPIO2 + 0xC40), | ||
292 | .config = &gpio_cfg_noint, | ||
293 | .irq_base = IRQ_EINT(16), | ||
294 | .chip = { | ||
295 | .base = EXYNOS4_GPX2(0), | ||
296 | .ngpio = EXYNOS4_GPIO_X2_NR, | ||
297 | .label = "GPX2", | ||
298 | .to_irq = samsung_gpiolib_to_irq, | ||
299 | }, | ||
300 | }, { | ||
301 | .base = (S5P_VA_GPIO2 + 0xC60), | ||
302 | .config = &gpio_cfg_noint, | ||
303 | .irq_base = IRQ_EINT(24), | ||
304 | .chip = { | ||
305 | .base = EXYNOS4_GPX3(0), | ||
306 | .ngpio = EXYNOS4_GPIO_X3_NR, | ||
307 | .label = "GPX3", | ||
308 | .to_irq = samsung_gpiolib_to_irq, | ||
309 | }, | ||
310 | }, | ||
311 | }; | ||
312 | |||
313 | static struct s3c_gpio_chip exynos4_gpio_part3_4bit[] = { | ||
314 | { | ||
315 | .chip = { | ||
316 | .base = EXYNOS4_GPZ(0), | ||
317 | .ngpio = EXYNOS4_GPIO_Z_NR, | ||
318 | .label = "GPZ", | ||
319 | }, | ||
320 | }, | ||
321 | }; | ||
322 | |||
323 | static __init int exynos4_gpiolib_init(void) | ||
324 | { | ||
325 | struct s3c_gpio_chip *chip; | ||
326 | int i; | ||
327 | int group = 0; | ||
328 | int nr_chips; | ||
329 | |||
330 | /* GPIO part 1 */ | ||
331 | |||
332 | chip = exynos4_gpio_part1_4bit; | ||
333 | nr_chips = ARRAY_SIZE(exynos4_gpio_part1_4bit); | ||
334 | |||
335 | for (i = 0; i < nr_chips; i++, chip++) { | ||
336 | if (chip->config == NULL) { | ||
337 | chip->config = &gpio_cfg; | ||
338 | /* Assign the GPIO interrupt group */ | ||
339 | chip->group = group++; | ||
340 | } | ||
341 | if (chip->base == NULL) | ||
342 | chip->base = S5P_VA_GPIO1 + (i) * 0x20; | ||
343 | } | ||
344 | |||
345 | samsung_gpiolib_add_4bit_chips(exynos4_gpio_part1_4bit, nr_chips); | ||
346 | |||
347 | /* GPIO part 2 */ | ||
348 | |||
349 | chip = exynos4_gpio_part2_4bit; | ||
350 | nr_chips = ARRAY_SIZE(exynos4_gpio_part2_4bit); | ||
351 | |||
352 | for (i = 0; i < nr_chips; i++, chip++) { | ||
353 | if (chip->config == NULL) { | ||
354 | chip->config = &gpio_cfg; | ||
355 | /* Assign the GPIO interrupt group */ | ||
356 | chip->group = group++; | ||
357 | } | ||
358 | if (chip->base == NULL) | ||
359 | chip->base = S5P_VA_GPIO2 + (i) * 0x20; | ||
360 | } | ||
361 | |||
362 | samsung_gpiolib_add_4bit_chips(exynos4_gpio_part2_4bit, nr_chips); | ||
363 | |||
364 | /* GPIO part 3 */ | ||
365 | |||
366 | chip = exynos4_gpio_part3_4bit; | ||
367 | nr_chips = ARRAY_SIZE(exynos4_gpio_part3_4bit); | ||
368 | |||
369 | for (i = 0; i < nr_chips; i++, chip++) { | ||
370 | if (chip->config == NULL) { | ||
371 | chip->config = &gpio_cfg; | ||
372 | /* Assign the GPIO interrupt group */ | ||
373 | chip->group = group++; | ||
374 | } | ||
375 | if (chip->base == NULL) | ||
376 | chip->base = S5P_VA_GPIO3 + (i) * 0x20; | ||
377 | } | ||
378 | |||
379 | samsung_gpiolib_add_4bit_chips(exynos4_gpio_part3_4bit, nr_chips); | ||
380 | s5p_register_gpioint_bank(IRQ_GPIO_XA, 0, IRQ_GPIO1_NR_GROUPS); | ||
381 | s5p_register_gpioint_bank(IRQ_GPIO_XB, IRQ_GPIO1_NR_GROUPS, IRQ_GPIO2_NR_GROUPS); | ||
382 | |||
383 | return 0; | ||
384 | } | ||
385 | core_initcall(exynos4_gpiolib_init); | ||
diff --git a/drivers/gpio/gpio-plat-samsung.c b/drivers/gpio/gpio-plat-samsung.c deleted file mode 100644 index ef67f1952a72..000000000000 --- a/drivers/gpio/gpio-plat-samsung.c +++ /dev/null | |||
@@ -1,205 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright 2008 Openmoko, Inc. | ||
3 | * Copyright 2008 Simtec Electronics | ||
4 | * Ben Dooks <ben@simtec.co.uk> | ||
5 | * http://armlinux.simtec.co.uk/ | ||
6 | * | ||
7 | * Copyright (c) 2009 Samsung Electronics Co., Ltd. | ||
8 | * http://www.samsung.com/ | ||
9 | * | ||
10 | * SAMSUNG - GPIOlib support | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or modify | ||
13 | * it under the terms of the GNU General Public License version 2 as | ||
14 | * published by the Free Software Foundation. | ||
15 | */ | ||
16 | |||
17 | #include <linux/kernel.h> | ||
18 | #include <linux/irq.h> | ||
19 | #include <linux/io.h> | ||
20 | #include <linux/gpio.h> | ||
21 | #include <plat/gpio-core.h> | ||
22 | #include <plat/gpio-cfg.h> | ||
23 | #include <plat/gpio-cfg-helpers.h> | ||
24 | |||
25 | #ifndef DEBUG_GPIO | ||
26 | #define gpio_dbg(x...) do { } while (0) | ||
27 | #else | ||
28 | #define gpio_dbg(x...) printk(KERN_DEBUG x) | ||
29 | #endif | ||
30 | |||
31 | /* The samsung_gpiolib_4bit routines are to control the gpio banks where | ||
32 | * the gpio configuration register (GPxCON) has 4 bits per GPIO, as the | ||
33 | * following example: | ||
34 | * | ||
35 | * base + 0x00: Control register, 4 bits per gpio | ||
36 | * gpio n: 4 bits starting at (4*n) | ||
37 | * 0000 = input, 0001 = output, others mean special-function | ||
38 | * base + 0x04: Data register, 1 bit per gpio | ||
39 | * bit n: data bit n | ||
40 | * | ||
41 | * Note, since the data register is one bit per gpio and is at base + 0x4 | ||
42 | * we can use s3c_gpiolib_get and s3c_gpiolib_set to change the state of | ||
43 | * the output. | ||
44 | */ | ||
45 | |||
46 | static int samsung_gpiolib_4bit_input(struct gpio_chip *chip, | ||
47 | unsigned int offset) | ||
48 | { | ||
49 | struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); | ||
50 | void __iomem *base = ourchip->base; | ||
51 | unsigned long con; | ||
52 | |||
53 | con = __raw_readl(base + GPIOCON_OFF); | ||
54 | con &= ~(0xf << con_4bit_shift(offset)); | ||
55 | __raw_writel(con, base + GPIOCON_OFF); | ||
56 | |||
57 | gpio_dbg("%s: %p: CON now %08lx\n", __func__, base, con); | ||
58 | |||
59 | return 0; | ||
60 | } | ||
61 | |||
62 | static int samsung_gpiolib_4bit_output(struct gpio_chip *chip, | ||
63 | unsigned int offset, int value) | ||
64 | { | ||
65 | struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); | ||
66 | void __iomem *base = ourchip->base; | ||
67 | unsigned long con; | ||
68 | unsigned long dat; | ||
69 | |||
70 | con = __raw_readl(base + GPIOCON_OFF); | ||
71 | con &= ~(0xf << con_4bit_shift(offset)); | ||
72 | con |= 0x1 << con_4bit_shift(offset); | ||
73 | |||
74 | dat = __raw_readl(base + GPIODAT_OFF); | ||
75 | |||
76 | if (value) | ||
77 | dat |= 1 << offset; | ||
78 | else | ||
79 | dat &= ~(1 << offset); | ||
80 | |||
81 | __raw_writel(dat, base + GPIODAT_OFF); | ||
82 | __raw_writel(con, base + GPIOCON_OFF); | ||
83 | __raw_writel(dat, base + GPIODAT_OFF); | ||
84 | |||
85 | gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat); | ||
86 | |||
87 | return 0; | ||
88 | } | ||
89 | |||
90 | /* The next set of routines are for the case where the GPIO configuration | ||
91 | * registers are 4 bits per GPIO but there is more than one register (the | ||
92 | * bank has more than 8 GPIOs. | ||
93 | * | ||
94 | * This case is the similar to the 4 bit case, but the registers are as | ||
95 | * follows: | ||
96 | * | ||
97 | * base + 0x00: Control register, 4 bits per gpio (lower 8 GPIOs) | ||
98 | * gpio n: 4 bits starting at (4*n) | ||
99 | * 0000 = input, 0001 = output, others mean special-function | ||
100 | * base + 0x04: Control register, 4 bits per gpio (up to 8 additions GPIOs) | ||
101 | * gpio n: 4 bits starting at (4*n) | ||
102 | * 0000 = input, 0001 = output, others mean special-function | ||
103 | * base + 0x08: Data register, 1 bit per gpio | ||
104 | * bit n: data bit n | ||
105 | * | ||
106 | * To allow us to use the s3c_gpiolib_get and s3c_gpiolib_set routines we | ||
107 | * store the 'base + 0x4' address so that these routines see the data | ||
108 | * register at ourchip->base + 0x04. | ||
109 | */ | ||
110 | |||
111 | static int samsung_gpiolib_4bit2_input(struct gpio_chip *chip, | ||
112 | unsigned int offset) | ||
113 | { | ||
114 | struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); | ||
115 | void __iomem *base = ourchip->base; | ||
116 | void __iomem *regcon = base; | ||
117 | unsigned long con; | ||
118 | |||
119 | if (offset > 7) | ||
120 | offset -= 8; | ||
121 | else | ||
122 | regcon -= 4; | ||
123 | |||
124 | con = __raw_readl(regcon); | ||
125 | con &= ~(0xf << con_4bit_shift(offset)); | ||
126 | __raw_writel(con, regcon); | ||
127 | |||
128 | gpio_dbg("%s: %p: CON %08lx\n", __func__, base, con); | ||
129 | |||
130 | return 0; | ||
131 | } | ||
132 | |||
133 | static int samsung_gpiolib_4bit2_output(struct gpio_chip *chip, | ||
134 | unsigned int offset, int value) | ||
135 | { | ||
136 | struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); | ||
137 | void __iomem *base = ourchip->base; | ||
138 | void __iomem *regcon = base; | ||
139 | unsigned long con; | ||
140 | unsigned long dat; | ||
141 | unsigned con_offset = offset; | ||
142 | |||
143 | if (con_offset > 7) | ||
144 | con_offset -= 8; | ||
145 | else | ||
146 | regcon -= 4; | ||
147 | |||
148 | con = __raw_readl(regcon); | ||
149 | con &= ~(0xf << con_4bit_shift(con_offset)); | ||
150 | con |= 0x1 << con_4bit_shift(con_offset); | ||
151 | |||
152 | dat = __raw_readl(base + GPIODAT_OFF); | ||
153 | |||
154 | if (value) | ||
155 | dat |= 1 << offset; | ||
156 | else | ||
157 | dat &= ~(1 << offset); | ||
158 | |||
159 | __raw_writel(dat, base + GPIODAT_OFF); | ||
160 | __raw_writel(con, regcon); | ||
161 | __raw_writel(dat, base + GPIODAT_OFF); | ||
162 | |||
163 | gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat); | ||
164 | |||
165 | return 0; | ||
166 | } | ||
167 | |||
168 | void __init samsung_gpiolib_add_4bit(struct s3c_gpio_chip *chip) | ||
169 | { | ||
170 | chip->chip.direction_input = samsung_gpiolib_4bit_input; | ||
171 | chip->chip.direction_output = samsung_gpiolib_4bit_output; | ||
172 | chip->pm = __gpio_pm(&s3c_gpio_pm_4bit); | ||
173 | } | ||
174 | |||
175 | void __init samsung_gpiolib_add_4bit2(struct s3c_gpio_chip *chip) | ||
176 | { | ||
177 | chip->chip.direction_input = samsung_gpiolib_4bit2_input; | ||
178 | chip->chip.direction_output = samsung_gpiolib_4bit2_output; | ||
179 | chip->pm = __gpio_pm(&s3c_gpio_pm_4bit); | ||
180 | } | ||
181 | |||
182 | void __init samsung_gpiolib_add_4bit_chips(struct s3c_gpio_chip *chip, | ||
183 | int nr_chips) | ||
184 | { | ||
185 | for (; nr_chips > 0; nr_chips--, chip++) { | ||
186 | samsung_gpiolib_add_4bit(chip); | ||
187 | s3c_gpiolib_add(chip); | ||
188 | } | ||
189 | } | ||
190 | |||
191 | void __init samsung_gpiolib_add_4bit2_chips(struct s3c_gpio_chip *chip, | ||
192 | int nr_chips) | ||
193 | { | ||
194 | for (; nr_chips > 0; nr_chips--, chip++) { | ||
195 | samsung_gpiolib_add_4bit2(chip); | ||
196 | s3c_gpiolib_add(chip); | ||
197 | } | ||
198 | } | ||
199 | |||
200 | void __init samsung_gpiolib_add_2bit_chips(struct s3c_gpio_chip *chip, | ||
201 | int nr_chips) | ||
202 | { | ||
203 | for (; nr_chips > 0; nr_chips--, chip++) | ||
204 | s3c_gpiolib_add(chip); | ||
205 | } | ||
diff --git a/drivers/gpio/gpio-s5pc100.c b/drivers/gpio/gpio-s5pc100.c deleted file mode 100644 index 7f87b0c76e0b..000000000000 --- a/drivers/gpio/gpio-s5pc100.c +++ /dev/null | |||
@@ -1,354 +0,0 @@ | |||
1 | /* | ||
2 | * S5PC100 - GPIOlib support | ||
3 | * | ||
4 | * Copyright (c) 2010 Samsung Electronics Co., Ltd. | ||
5 | * http://www.samsung.com | ||
6 | * | ||
7 | * Copyright 2009 Samsung Electronics Co | ||
8 | * Kyungmin Park <kyungmin.park@samsung.com> | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #include <linux/kernel.h> | ||
16 | #include <linux/irq.h> | ||
17 | #include <linux/io.h> | ||
18 | #include <linux/gpio.h> | ||
19 | |||
20 | #include <mach/map.h> | ||
21 | #include <mach/regs-gpio.h> | ||
22 | |||
23 | #include <plat/gpio-core.h> | ||
24 | #include <plat/gpio-cfg.h> | ||
25 | #include <plat/gpio-cfg-helpers.h> | ||
26 | |||
27 | /* S5PC100 GPIO bank summary: | ||
28 | * | ||
29 | * Bank GPIOs Style INT Type | ||
30 | * A0 8 4Bit GPIO_INT0 | ||
31 | * A1 5 4Bit GPIO_INT1 | ||
32 | * B 8 4Bit GPIO_INT2 | ||
33 | * C 5 4Bit GPIO_INT3 | ||
34 | * D 7 4Bit GPIO_INT4 | ||
35 | * E0 8 4Bit GPIO_INT5 | ||
36 | * E1 6 4Bit GPIO_INT6 | ||
37 | * F0 8 4Bit GPIO_INT7 | ||
38 | * F1 8 4Bit GPIO_INT8 | ||
39 | * F2 8 4Bit GPIO_INT9 | ||
40 | * F3 4 4Bit GPIO_INT10 | ||
41 | * G0 8 4Bit GPIO_INT11 | ||
42 | * G1 3 4Bit GPIO_INT12 | ||
43 | * G2 7 4Bit GPIO_INT13 | ||
44 | * G3 7 4Bit GPIO_INT14 | ||
45 | * H0 8 4Bit WKUP_INT | ||
46 | * H1 8 4Bit WKUP_INT | ||
47 | * H2 8 4Bit WKUP_INT | ||
48 | * H3 8 4Bit WKUP_INT | ||
49 | * I 8 4Bit GPIO_INT15 | ||
50 | * J0 8 4Bit GPIO_INT16 | ||
51 | * J1 5 4Bit GPIO_INT17 | ||
52 | * J2 8 4Bit GPIO_INT18 | ||
53 | * J3 8 4Bit GPIO_INT19 | ||
54 | * J4 4 4Bit GPIO_INT20 | ||
55 | * K0 8 4Bit None | ||
56 | * K1 6 4Bit None | ||
57 | * K2 8 4Bit None | ||
58 | * K3 8 4Bit None | ||
59 | * L0 8 4Bit None | ||
60 | * L1 8 4Bit None | ||
61 | * L2 8 4Bit None | ||
62 | * L3 8 4Bit None | ||
63 | */ | ||
64 | |||
65 | static struct s3c_gpio_cfg gpio_cfg = { | ||
66 | .set_config = s3c_gpio_setcfg_s3c64xx_4bit, | ||
67 | .set_pull = s3c_gpio_setpull_updown, | ||
68 | .get_pull = s3c_gpio_getpull_updown, | ||
69 | }; | ||
70 | |||
71 | static struct s3c_gpio_cfg gpio_cfg_eint = { | ||
72 | .cfg_eint = 0xf, | ||
73 | .set_config = s3c_gpio_setcfg_s3c64xx_4bit, | ||
74 | .set_pull = s3c_gpio_setpull_updown, | ||
75 | .get_pull = s3c_gpio_getpull_updown, | ||
76 | }; | ||
77 | |||
78 | static struct s3c_gpio_cfg gpio_cfg_noint = { | ||
79 | .set_config = s3c_gpio_setcfg_s3c64xx_4bit, | ||
80 | .set_pull = s3c_gpio_setpull_updown, | ||
81 | .get_pull = s3c_gpio_getpull_updown, | ||
82 | }; | ||
83 | |||
84 | /* | ||
85 | * GPIO bank's base address given the index of the bank in the | ||
86 | * list of all gpio banks. | ||
87 | */ | ||
88 | #define S5PC100_BANK_BASE(bank_nr) (S5P_VA_GPIO + ((bank_nr) * 0x20)) | ||
89 | |||
90 | /* | ||
91 | * Following are the gpio banks in S5PC100. | ||
92 | * | ||
93 | * The 'config' member when left to NULL, is initialized to the default | ||
94 | * structure gpio_cfg in the init function below. | ||
95 | * | ||
96 | * The 'base' member is also initialized in the init function below. | ||
97 | * Note: The initialization of 'base' member of s3c_gpio_chip structure | ||
98 | * uses the above macro and depends on the banks being listed in order here. | ||
99 | */ | ||
100 | static struct s3c_gpio_chip s5pc100_gpio_chips[] = { | ||
101 | { | ||
102 | .chip = { | ||
103 | .base = S5PC100_GPA0(0), | ||
104 | .ngpio = S5PC100_GPIO_A0_NR, | ||
105 | .label = "GPA0", | ||
106 | }, | ||
107 | }, { | ||
108 | .chip = { | ||
109 | .base = S5PC100_GPA1(0), | ||
110 | .ngpio = S5PC100_GPIO_A1_NR, | ||
111 | .label = "GPA1", | ||
112 | }, | ||
113 | }, { | ||
114 | .chip = { | ||
115 | .base = S5PC100_GPB(0), | ||
116 | .ngpio = S5PC100_GPIO_B_NR, | ||
117 | .label = "GPB", | ||
118 | }, | ||
119 | }, { | ||
120 | .chip = { | ||
121 | .base = S5PC100_GPC(0), | ||
122 | .ngpio = S5PC100_GPIO_C_NR, | ||
123 | .label = "GPC", | ||
124 | }, | ||
125 | }, { | ||
126 | .chip = { | ||
127 | .base = S5PC100_GPD(0), | ||
128 | .ngpio = S5PC100_GPIO_D_NR, | ||
129 | .label = "GPD", | ||
130 | }, | ||
131 | }, { | ||
132 | .chip = { | ||
133 | .base = S5PC100_GPE0(0), | ||
134 | .ngpio = S5PC100_GPIO_E0_NR, | ||
135 | .label = "GPE0", | ||
136 | }, | ||
137 | }, { | ||
138 | .chip = { | ||
139 | .base = S5PC100_GPE1(0), | ||
140 | .ngpio = S5PC100_GPIO_E1_NR, | ||
141 | .label = "GPE1", | ||
142 | }, | ||
143 | }, { | ||
144 | .chip = { | ||
145 | .base = S5PC100_GPF0(0), | ||
146 | .ngpio = S5PC100_GPIO_F0_NR, | ||
147 | .label = "GPF0", | ||
148 | }, | ||
149 | }, { | ||
150 | .chip = { | ||
151 | .base = S5PC100_GPF1(0), | ||
152 | .ngpio = S5PC100_GPIO_F1_NR, | ||
153 | .label = "GPF1", | ||
154 | }, | ||
155 | }, { | ||
156 | .chip = { | ||
157 | .base = S5PC100_GPF2(0), | ||
158 | .ngpio = S5PC100_GPIO_F2_NR, | ||
159 | .label = "GPF2", | ||
160 | }, | ||
161 | }, { | ||
162 | .chip = { | ||
163 | .base = S5PC100_GPF3(0), | ||
164 | .ngpio = S5PC100_GPIO_F3_NR, | ||
165 | .label = "GPF3", | ||
166 | }, | ||
167 | }, { | ||
168 | .chip = { | ||
169 | .base = S5PC100_GPG0(0), | ||
170 | .ngpio = S5PC100_GPIO_G0_NR, | ||
171 | .label = "GPG0", | ||
172 | }, | ||
173 | }, { | ||
174 | .chip = { | ||
175 | .base = S5PC100_GPG1(0), | ||
176 | .ngpio = S5PC100_GPIO_G1_NR, | ||
177 | .label = "GPG1", | ||
178 | }, | ||
179 | }, { | ||
180 | .chip = { | ||
181 | .base = S5PC100_GPG2(0), | ||
182 | .ngpio = S5PC100_GPIO_G2_NR, | ||
183 | .label = "GPG2", | ||
184 | }, | ||
185 | }, { | ||
186 | .chip = { | ||
187 | .base = S5PC100_GPG3(0), | ||
188 | .ngpio = S5PC100_GPIO_G3_NR, | ||
189 | .label = "GPG3", | ||
190 | }, | ||
191 | }, { | ||
192 | .chip = { | ||
193 | .base = S5PC100_GPI(0), | ||
194 | .ngpio = S5PC100_GPIO_I_NR, | ||
195 | .label = "GPI", | ||
196 | }, | ||
197 | }, { | ||
198 | .chip = { | ||
199 | .base = S5PC100_GPJ0(0), | ||
200 | .ngpio = S5PC100_GPIO_J0_NR, | ||
201 | .label = "GPJ0", | ||
202 | }, | ||
203 | }, { | ||
204 | .chip = { | ||
205 | .base = S5PC100_GPJ1(0), | ||
206 | .ngpio = S5PC100_GPIO_J1_NR, | ||
207 | .label = "GPJ1", | ||
208 | }, | ||
209 | }, { | ||
210 | .chip = { | ||
211 | .base = S5PC100_GPJ2(0), | ||
212 | .ngpio = S5PC100_GPIO_J2_NR, | ||
213 | .label = "GPJ2", | ||
214 | }, | ||
215 | }, { | ||
216 | .chip = { | ||
217 | .base = S5PC100_GPJ3(0), | ||
218 | .ngpio = S5PC100_GPIO_J3_NR, | ||
219 | .label = "GPJ3", | ||
220 | }, | ||
221 | }, { | ||
222 | .chip = { | ||
223 | .base = S5PC100_GPJ4(0), | ||
224 | .ngpio = S5PC100_GPIO_J4_NR, | ||
225 | .label = "GPJ4", | ||
226 | }, | ||
227 | }, { | ||
228 | .config = &gpio_cfg_noint, | ||
229 | .chip = { | ||
230 | .base = S5PC100_GPK0(0), | ||
231 | .ngpio = S5PC100_GPIO_K0_NR, | ||
232 | .label = "GPK0", | ||
233 | }, | ||
234 | }, { | ||
235 | .config = &gpio_cfg_noint, | ||
236 | .chip = { | ||
237 | .base = S5PC100_GPK1(0), | ||
238 | .ngpio = S5PC100_GPIO_K1_NR, | ||
239 | .label = "GPK1", | ||
240 | }, | ||
241 | }, { | ||
242 | .config = &gpio_cfg_noint, | ||
243 | .chip = { | ||
244 | .base = S5PC100_GPK2(0), | ||
245 | .ngpio = S5PC100_GPIO_K2_NR, | ||
246 | .label = "GPK2", | ||
247 | }, | ||
248 | }, { | ||
249 | .config = &gpio_cfg_noint, | ||
250 | .chip = { | ||
251 | .base = S5PC100_GPK3(0), | ||
252 | .ngpio = S5PC100_GPIO_K3_NR, | ||
253 | .label = "GPK3", | ||
254 | }, | ||
255 | }, { | ||
256 | .config = &gpio_cfg_noint, | ||
257 | .chip = { | ||
258 | .base = S5PC100_GPL0(0), | ||
259 | .ngpio = S5PC100_GPIO_L0_NR, | ||
260 | .label = "GPL0", | ||
261 | }, | ||
262 | }, { | ||
263 | .config = &gpio_cfg_noint, | ||
264 | .chip = { | ||
265 | .base = S5PC100_GPL1(0), | ||
266 | .ngpio = S5PC100_GPIO_L1_NR, | ||
267 | .label = "GPL1", | ||
268 | }, | ||
269 | }, { | ||
270 | .config = &gpio_cfg_noint, | ||
271 | .chip = { | ||
272 | .base = S5PC100_GPL2(0), | ||
273 | .ngpio = S5PC100_GPIO_L2_NR, | ||
274 | .label = "GPL2", | ||
275 | }, | ||
276 | }, { | ||
277 | .config = &gpio_cfg_noint, | ||
278 | .chip = { | ||
279 | .base = S5PC100_GPL3(0), | ||
280 | .ngpio = S5PC100_GPIO_L3_NR, | ||
281 | .label = "GPL3", | ||
282 | }, | ||
283 | }, { | ||
284 | .config = &gpio_cfg_noint, | ||
285 | .chip = { | ||
286 | .base = S5PC100_GPL4(0), | ||
287 | .ngpio = S5PC100_GPIO_L4_NR, | ||
288 | .label = "GPL4", | ||
289 | }, | ||
290 | }, { | ||
291 | .base = (S5P_VA_GPIO + 0xC00), | ||
292 | .config = &gpio_cfg_eint, | ||
293 | .irq_base = IRQ_EINT(0), | ||
294 | .chip = { | ||
295 | .base = S5PC100_GPH0(0), | ||
296 | .ngpio = S5PC100_GPIO_H0_NR, | ||
297 | .label = "GPH0", | ||
298 | .to_irq = samsung_gpiolib_to_irq, | ||
299 | }, | ||
300 | }, { | ||
301 | .base = (S5P_VA_GPIO + 0xC20), | ||
302 | .config = &gpio_cfg_eint, | ||
303 | .irq_base = IRQ_EINT(8), | ||
304 | .chip = { | ||
305 | .base = S5PC100_GPH1(0), | ||
306 | .ngpio = S5PC100_GPIO_H1_NR, | ||
307 | .label = "GPH1", | ||
308 | .to_irq = samsung_gpiolib_to_irq, | ||
309 | }, | ||
310 | }, { | ||
311 | .base = (S5P_VA_GPIO + 0xC40), | ||
312 | .config = &gpio_cfg_eint, | ||
313 | .irq_base = IRQ_EINT(16), | ||
314 | .chip = { | ||
315 | .base = S5PC100_GPH2(0), | ||
316 | .ngpio = S5PC100_GPIO_H2_NR, | ||
317 | .label = "GPH2", | ||
318 | .to_irq = samsung_gpiolib_to_irq, | ||
319 | }, | ||
320 | }, { | ||
321 | .base = (S5P_VA_GPIO + 0xC60), | ||
322 | .config = &gpio_cfg_eint, | ||
323 | .irq_base = IRQ_EINT(24), | ||
324 | .chip = { | ||
325 | .base = S5PC100_GPH3(0), | ||
326 | .ngpio = S5PC100_GPIO_H3_NR, | ||
327 | .label = "GPH3", | ||
328 | .to_irq = samsung_gpiolib_to_irq, | ||
329 | }, | ||
330 | }, | ||
331 | }; | ||
332 | |||
333 | static __init int s5pc100_gpiolib_init(void) | ||
334 | { | ||
335 | struct s3c_gpio_chip *chip = s5pc100_gpio_chips; | ||
336 | int nr_chips = ARRAY_SIZE(s5pc100_gpio_chips); | ||
337 | int gpioint_group = 0; | ||
338 | int i; | ||
339 | |||
340 | for (i = 0; i < nr_chips; i++, chip++) { | ||
341 | if (chip->config == NULL) { | ||
342 | chip->config = &gpio_cfg; | ||
343 | chip->group = gpioint_group++; | ||
344 | } | ||
345 | if (chip->base == NULL) | ||
346 | chip->base = S5PC100_BANK_BASE(i); | ||
347 | } | ||
348 | |||
349 | samsung_gpiolib_add_4bit_chips(s5pc100_gpio_chips, nr_chips); | ||
350 | s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR); | ||
351 | |||
352 | return 0; | ||
353 | } | ||
354 | core_initcall(s5pc100_gpiolib_init); | ||
diff --git a/drivers/gpio/gpio-s5pv210.c b/drivers/gpio/gpio-s5pv210.c deleted file mode 100644 index eb12f1602de9..000000000000 --- a/drivers/gpio/gpio-s5pv210.c +++ /dev/null | |||
@@ -1,287 +0,0 @@ | |||
1 | /* | ||
2 | * S5PV210 - GPIOlib support | ||
3 | * | ||
4 | * Copyright (c) 2010 Samsung Electronics Co., Ltd. | ||
5 | * http://www.samsung.com/ | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License version 2 as | ||
9 | * published by the Free Software Foundation. | ||
10 | */ | ||
11 | |||
12 | #include <linux/kernel.h> | ||
13 | #include <linux/irq.h> | ||
14 | #include <linux/io.h> | ||
15 | #include <linux/gpio.h> | ||
16 | #include <plat/gpio-core.h> | ||
17 | #include <plat/gpio-cfg.h> | ||
18 | #include <plat/gpio-cfg-helpers.h> | ||
19 | #include <mach/map.h> | ||
20 | |||
21 | static struct s3c_gpio_cfg gpio_cfg = { | ||
22 | .set_config = s3c_gpio_setcfg_s3c64xx_4bit, | ||
23 | .set_pull = s3c_gpio_setpull_updown, | ||
24 | .get_pull = s3c_gpio_getpull_updown, | ||
25 | }; | ||
26 | |||
27 | static struct s3c_gpio_cfg gpio_cfg_noint = { | ||
28 | .set_config = s3c_gpio_setcfg_s3c64xx_4bit, | ||
29 | .set_pull = s3c_gpio_setpull_updown, | ||
30 | .get_pull = s3c_gpio_getpull_updown, | ||
31 | }; | ||
32 | |||
33 | /* GPIO bank's base address given the index of the bank in the | ||
34 | * list of all gpio banks. | ||
35 | */ | ||
36 | #define S5PV210_BANK_BASE(bank_nr) (S5P_VA_GPIO + ((bank_nr) * 0x20)) | ||
37 | |||
38 | /* | ||
39 | * Following are the gpio banks in v210. | ||
40 | * | ||
41 | * The 'config' member when left to NULL, is initialized to the default | ||
42 | * structure gpio_cfg in the init function below. | ||
43 | * | ||
44 | * The 'base' member is also initialized in the init function below. | ||
45 | * Note: The initialization of 'base' member of s3c_gpio_chip structure | ||
46 | * uses the above macro and depends on the banks being listed in order here. | ||
47 | */ | ||
48 | static struct s3c_gpio_chip s5pv210_gpio_4bit[] = { | ||
49 | { | ||
50 | .chip = { | ||
51 | .base = S5PV210_GPA0(0), | ||
52 | .ngpio = S5PV210_GPIO_A0_NR, | ||
53 | .label = "GPA0", | ||
54 | }, | ||
55 | }, { | ||
56 | .chip = { | ||
57 | .base = S5PV210_GPA1(0), | ||
58 | .ngpio = S5PV210_GPIO_A1_NR, | ||
59 | .label = "GPA1", | ||
60 | }, | ||
61 | }, { | ||
62 | .chip = { | ||
63 | .base = S5PV210_GPB(0), | ||
64 | .ngpio = S5PV210_GPIO_B_NR, | ||
65 | .label = "GPB", | ||
66 | }, | ||
67 | }, { | ||
68 | .chip = { | ||
69 | .base = S5PV210_GPC0(0), | ||
70 | .ngpio = S5PV210_GPIO_C0_NR, | ||
71 | .label = "GPC0", | ||
72 | }, | ||
73 | }, { | ||
74 | .chip = { | ||
75 | .base = S5PV210_GPC1(0), | ||
76 | .ngpio = S5PV210_GPIO_C1_NR, | ||
77 | .label = "GPC1", | ||
78 | }, | ||
79 | }, { | ||
80 | .chip = { | ||
81 | .base = S5PV210_GPD0(0), | ||
82 | .ngpio = S5PV210_GPIO_D0_NR, | ||
83 | .label = "GPD0", | ||
84 | }, | ||
85 | }, { | ||
86 | .chip = { | ||
87 | .base = S5PV210_GPD1(0), | ||
88 | .ngpio = S5PV210_GPIO_D1_NR, | ||
89 | .label = "GPD1", | ||
90 | }, | ||
91 | }, { | ||
92 | .chip = { | ||
93 | .base = S5PV210_GPE0(0), | ||
94 | .ngpio = S5PV210_GPIO_E0_NR, | ||
95 | .label = "GPE0", | ||
96 | }, | ||
97 | }, { | ||
98 | .chip = { | ||
99 | .base = S5PV210_GPE1(0), | ||
100 | .ngpio = S5PV210_GPIO_E1_NR, | ||
101 | .label = "GPE1", | ||
102 | }, | ||
103 | }, { | ||
104 | .chip = { | ||
105 | .base = S5PV210_GPF0(0), | ||
106 | .ngpio = S5PV210_GPIO_F0_NR, | ||
107 | .label = "GPF0", | ||
108 | }, | ||
109 | }, { | ||
110 | .chip = { | ||
111 | .base = S5PV210_GPF1(0), | ||
112 | .ngpio = S5PV210_GPIO_F1_NR, | ||
113 | .label = "GPF1", | ||
114 | }, | ||
115 | }, { | ||
116 | .chip = { | ||
117 | .base = S5PV210_GPF2(0), | ||
118 | .ngpio = S5PV210_GPIO_F2_NR, | ||
119 | .label = "GPF2", | ||
120 | }, | ||
121 | }, { | ||
122 | .chip = { | ||
123 | .base = S5PV210_GPF3(0), | ||
124 | .ngpio = S5PV210_GPIO_F3_NR, | ||
125 | .label = "GPF3", | ||
126 | }, | ||
127 | }, { | ||
128 | .chip = { | ||
129 | .base = S5PV210_GPG0(0), | ||
130 | .ngpio = S5PV210_GPIO_G0_NR, | ||
131 | .label = "GPG0", | ||
132 | }, | ||
133 | }, { | ||
134 | .chip = { | ||
135 | .base = S5PV210_GPG1(0), | ||
136 | .ngpio = S5PV210_GPIO_G1_NR, | ||
137 | .label = "GPG1", | ||
138 | }, | ||
139 | }, { | ||
140 | .chip = { | ||
141 | .base = S5PV210_GPG2(0), | ||
142 | .ngpio = S5PV210_GPIO_G2_NR, | ||
143 | .label = "GPG2", | ||
144 | }, | ||
145 | }, { | ||
146 | .chip = { | ||
147 | .base = S5PV210_GPG3(0), | ||
148 | .ngpio = S5PV210_GPIO_G3_NR, | ||
149 | .label = "GPG3", | ||
150 | }, | ||
151 | }, { | ||
152 | .config = &gpio_cfg_noint, | ||
153 | .chip = { | ||
154 | .base = S5PV210_GPI(0), | ||
155 | .ngpio = S5PV210_GPIO_I_NR, | ||
156 | .label = "GPI", | ||
157 | }, | ||
158 | }, { | ||
159 | .chip = { | ||
160 | .base = S5PV210_GPJ0(0), | ||
161 | .ngpio = S5PV210_GPIO_J0_NR, | ||
162 | .label = "GPJ0", | ||
163 | }, | ||
164 | }, { | ||
165 | .chip = { | ||
166 | .base = S5PV210_GPJ1(0), | ||
167 | .ngpio = S5PV210_GPIO_J1_NR, | ||
168 | .label = "GPJ1", | ||
169 | }, | ||
170 | }, { | ||
171 | .chip = { | ||
172 | .base = S5PV210_GPJ2(0), | ||
173 | .ngpio = S5PV210_GPIO_J2_NR, | ||
174 | .label = "GPJ2", | ||
175 | }, | ||
176 | }, { | ||
177 | .chip = { | ||
178 | .base = S5PV210_GPJ3(0), | ||
179 | .ngpio = S5PV210_GPIO_J3_NR, | ||
180 | .label = "GPJ3", | ||
181 | }, | ||
182 | }, { | ||
183 | .chip = { | ||
184 | .base = S5PV210_GPJ4(0), | ||
185 | .ngpio = S5PV210_GPIO_J4_NR, | ||
186 | .label = "GPJ4", | ||
187 | }, | ||
188 | }, { | ||
189 | .config = &gpio_cfg_noint, | ||
190 | .chip = { | ||
191 | .base = S5PV210_MP01(0), | ||
192 | .ngpio = S5PV210_GPIO_MP01_NR, | ||
193 | .label = "MP01", | ||
194 | }, | ||
195 | }, { | ||
196 | .config = &gpio_cfg_noint, | ||
197 | .chip = { | ||
198 | .base = S5PV210_MP02(0), | ||
199 | .ngpio = S5PV210_GPIO_MP02_NR, | ||
200 | .label = "MP02", | ||
201 | }, | ||
202 | }, { | ||
203 | .config = &gpio_cfg_noint, | ||
204 | .chip = { | ||
205 | .base = S5PV210_MP03(0), | ||
206 | .ngpio = S5PV210_GPIO_MP03_NR, | ||
207 | .label = "MP03", | ||
208 | }, | ||
209 | }, { | ||
210 | .config = &gpio_cfg_noint, | ||
211 | .chip = { | ||
212 | .base = S5PV210_MP04(0), | ||
213 | .ngpio = S5PV210_GPIO_MP04_NR, | ||
214 | .label = "MP04", | ||
215 | }, | ||
216 | }, { | ||
217 | .config = &gpio_cfg_noint, | ||
218 | .chip = { | ||
219 | .base = S5PV210_MP05(0), | ||
220 | .ngpio = S5PV210_GPIO_MP05_NR, | ||
221 | .label = "MP05", | ||
222 | }, | ||
223 | }, { | ||
224 | .base = (S5P_VA_GPIO + 0xC00), | ||
225 | .config = &gpio_cfg_noint, | ||
226 | .irq_base = IRQ_EINT(0), | ||
227 | .chip = { | ||
228 | .base = S5PV210_GPH0(0), | ||
229 | .ngpio = S5PV210_GPIO_H0_NR, | ||
230 | .label = "GPH0", | ||
231 | .to_irq = samsung_gpiolib_to_irq, | ||
232 | }, | ||
233 | }, { | ||
234 | .base = (S5P_VA_GPIO + 0xC20), | ||
235 | .config = &gpio_cfg_noint, | ||
236 | .irq_base = IRQ_EINT(8), | ||
237 | .chip = { | ||
238 | .base = S5PV210_GPH1(0), | ||
239 | .ngpio = S5PV210_GPIO_H1_NR, | ||
240 | .label = "GPH1", | ||
241 | .to_irq = samsung_gpiolib_to_irq, | ||
242 | }, | ||
243 | }, { | ||
244 | .base = (S5P_VA_GPIO + 0xC40), | ||
245 | .config = &gpio_cfg_noint, | ||
246 | .irq_base = IRQ_EINT(16), | ||
247 | .chip = { | ||
248 | .base = S5PV210_GPH2(0), | ||
249 | .ngpio = S5PV210_GPIO_H2_NR, | ||
250 | .label = "GPH2", | ||
251 | .to_irq = samsung_gpiolib_to_irq, | ||
252 | }, | ||
253 | }, { | ||
254 | .base = (S5P_VA_GPIO + 0xC60), | ||
255 | .config = &gpio_cfg_noint, | ||
256 | .irq_base = IRQ_EINT(24), | ||
257 | .chip = { | ||
258 | .base = S5PV210_GPH3(0), | ||
259 | .ngpio = S5PV210_GPIO_H3_NR, | ||
260 | .label = "GPH3", | ||
261 | .to_irq = samsung_gpiolib_to_irq, | ||
262 | }, | ||
263 | }, | ||
264 | }; | ||
265 | |||
266 | static __init int s5pv210_gpiolib_init(void) | ||
267 | { | ||
268 | struct s3c_gpio_chip *chip = s5pv210_gpio_4bit; | ||
269 | int nr_chips = ARRAY_SIZE(s5pv210_gpio_4bit); | ||
270 | int gpioint_group = 0; | ||
271 | int i = 0; | ||
272 | |||
273 | for (i = 0; i < nr_chips; i++, chip++) { | ||
274 | if (chip->config == NULL) { | ||
275 | chip->config = &gpio_cfg; | ||
276 | chip->group = gpioint_group++; | ||
277 | } | ||
278 | if (chip->base == NULL) | ||
279 | chip->base = S5PV210_BANK_BASE(i); | ||
280 | } | ||
281 | |||
282 | samsung_gpiolib_add_4bit_chips(s5pv210_gpio_4bit, nr_chips); | ||
283 | s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR); | ||
284 | |||
285 | return 0; | ||
286 | } | ||
287 | core_initcall(s5pv210_gpiolib_init); | ||
diff --git a/drivers/gpio/gpio-samsung.c b/drivers/gpio/gpio-samsung.c new file mode 100644 index 000000000000..b6be77ae4973 --- /dev/null +++ b/drivers/gpio/gpio-samsung.c | |||
@@ -0,0 +1,2688 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd. | ||
3 | * http://www.samsung.com/ | ||
4 | * | ||
5 | * Copyright 2008 Openmoko, Inc. | ||
6 | * Copyright 2008 Simtec Electronics | ||
7 | * Ben Dooks <ben@simtec.co.uk> | ||
8 | * http://armlinux.simtec.co.uk/ | ||
9 | * | ||
10 | * SAMSUNG - GPIOlib support | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or modify | ||
13 | * it under the terms of the GNU General Public License version 2 as | ||
14 | * published by the Free Software Foundation. | ||
15 | */ | ||
16 | |||
17 | #include <linux/kernel.h> | ||
18 | #include <linux/irq.h> | ||
19 | #include <linux/io.h> | ||
20 | #include <linux/gpio.h> | ||
21 | #include <linux/init.h> | ||
22 | #include <linux/spinlock.h> | ||
23 | #include <linux/module.h> | ||
24 | #include <linux/interrupt.h> | ||
25 | #include <linux/sysdev.h> | ||
26 | #include <linux/ioport.h> | ||
27 | |||
28 | #include <asm/irq.h> | ||
29 | |||
30 | #include <mach/hardware.h> | ||
31 | #include <mach/map.h> | ||
32 | #include <mach/regs-clock.h> | ||
33 | #include <mach/regs-gpio.h> | ||
34 | |||
35 | #include <plat/cpu.h> | ||
36 | #include <plat/gpio-core.h> | ||
37 | #include <plat/gpio-cfg.h> | ||
38 | #include <plat/gpio-cfg-helpers.h> | ||
39 | #include <plat/gpio-fns.h> | ||
40 | #include <plat/pm.h> | ||
41 | |||
42 | #ifndef DEBUG_GPIO | ||
43 | #define gpio_dbg(x...) do { } while (0) | ||
44 | #else | ||
45 | #define gpio_dbg(x...) printk(KERN_DEBUG x) | ||
46 | #endif | ||
47 | |||
48 | int samsung_gpio_setpull_updown(struct samsung_gpio_chip *chip, | ||
49 | unsigned int off, samsung_gpio_pull_t pull) | ||
50 | { | ||
51 | void __iomem *reg = chip->base + 0x08; | ||
52 | int shift = off * 2; | ||
53 | u32 pup; | ||
54 | |||
55 | pup = __raw_readl(reg); | ||
56 | pup &= ~(3 << shift); | ||
57 | pup |= pull << shift; | ||
58 | __raw_writel(pup, reg); | ||
59 | |||
60 | return 0; | ||
61 | } | ||
62 | |||
63 | samsung_gpio_pull_t samsung_gpio_getpull_updown(struct samsung_gpio_chip *chip, | ||
64 | unsigned int off) | ||
65 | { | ||
66 | void __iomem *reg = chip->base + 0x08; | ||
67 | int shift = off * 2; | ||
68 | u32 pup = __raw_readl(reg); | ||
69 | |||
70 | pup >>= shift; | ||
71 | pup &= 0x3; | ||
72 | |||
73 | return (__force samsung_gpio_pull_t)pup; | ||
74 | } | ||
75 | |||
76 | int s3c2443_gpio_setpull(struct samsung_gpio_chip *chip, | ||
77 | unsigned int off, samsung_gpio_pull_t pull) | ||
78 | { | ||
79 | switch (pull) { | ||
80 | case S3C_GPIO_PULL_NONE: | ||
81 | pull = 0x01; | ||
82 | break; | ||
83 | case S3C_GPIO_PULL_UP: | ||
84 | pull = 0x00; | ||
85 | break; | ||
86 | case S3C_GPIO_PULL_DOWN: | ||
87 | pull = 0x02; | ||
88 | break; | ||
89 | } | ||
90 | return samsung_gpio_setpull_updown(chip, off, pull); | ||
91 | } | ||
92 | |||
93 | samsung_gpio_pull_t s3c2443_gpio_getpull(struct samsung_gpio_chip *chip, | ||
94 | unsigned int off) | ||
95 | { | ||
96 | samsung_gpio_pull_t pull; | ||
97 | |||
98 | pull = samsung_gpio_getpull_updown(chip, off); | ||
99 | |||
100 | switch (pull) { | ||
101 | case 0x00: | ||
102 | pull = S3C_GPIO_PULL_UP; | ||
103 | break; | ||
104 | case 0x01: | ||
105 | case 0x03: | ||
106 | pull = S3C_GPIO_PULL_NONE; | ||
107 | break; | ||
108 | case 0x02: | ||
109 | pull = S3C_GPIO_PULL_DOWN; | ||
110 | break; | ||
111 | } | ||
112 | |||
113 | return pull; | ||
114 | } | ||
115 | |||
116 | static int s3c24xx_gpio_setpull_1(struct samsung_gpio_chip *chip, | ||
117 | unsigned int off, samsung_gpio_pull_t pull, | ||
118 | samsung_gpio_pull_t updown) | ||
119 | { | ||
120 | void __iomem *reg = chip->base + 0x08; | ||
121 | u32 pup = __raw_readl(reg); | ||
122 | |||
123 | if (pull == updown) | ||
124 | pup &= ~(1 << off); | ||
125 | else if (pull == S3C_GPIO_PULL_NONE) | ||
126 | pup |= (1 << off); | ||
127 | else | ||
128 | return -EINVAL; | ||
129 | |||
130 | __raw_writel(pup, reg); | ||
131 | return 0; | ||
132 | } | ||
133 | |||
134 | static samsung_gpio_pull_t s3c24xx_gpio_getpull_1(struct samsung_gpio_chip *chip, | ||
135 | unsigned int off, | ||
136 | samsung_gpio_pull_t updown) | ||
137 | { | ||
138 | void __iomem *reg = chip->base + 0x08; | ||
139 | u32 pup = __raw_readl(reg); | ||
140 | |||
141 | pup &= (1 << off); | ||
142 | return pup ? S3C_GPIO_PULL_NONE : updown; | ||
143 | } | ||
144 | |||
145 | samsung_gpio_pull_t s3c24xx_gpio_getpull_1up(struct samsung_gpio_chip *chip, | ||
146 | unsigned int off) | ||
147 | { | ||
148 | return s3c24xx_gpio_getpull_1(chip, off, S3C_GPIO_PULL_UP); | ||
149 | } | ||
150 | |||
151 | int s3c24xx_gpio_setpull_1up(struct samsung_gpio_chip *chip, | ||
152 | unsigned int off, samsung_gpio_pull_t pull) | ||
153 | { | ||
154 | return s3c24xx_gpio_setpull_1(chip, off, pull, S3C_GPIO_PULL_UP); | ||
155 | } | ||
156 | |||
157 | samsung_gpio_pull_t s3c24xx_gpio_getpull_1down(struct samsung_gpio_chip *chip, | ||
158 | unsigned int off) | ||
159 | { | ||
160 | return s3c24xx_gpio_getpull_1(chip, off, S3C_GPIO_PULL_DOWN); | ||
161 | } | ||
162 | |||
163 | int s3c24xx_gpio_setpull_1down(struct samsung_gpio_chip *chip, | ||
164 | unsigned int off, samsung_gpio_pull_t pull) | ||
165 | { | ||
166 | return s3c24xx_gpio_setpull_1(chip, off, pull, S3C_GPIO_PULL_DOWN); | ||
167 | } | ||
168 | |||
169 | static int exynos4_gpio_setpull(struct samsung_gpio_chip *chip, | ||
170 | unsigned int off, samsung_gpio_pull_t pull) | ||
171 | { | ||
172 | if (pull == S3C_GPIO_PULL_UP) | ||
173 | pull = 3; | ||
174 | |||
175 | return samsung_gpio_setpull_updown(chip, off, pull); | ||
176 | } | ||
177 | |||
178 | static samsung_gpio_pull_t exynos4_gpio_getpull(struct samsung_gpio_chip *chip, | ||
179 | unsigned int off) | ||
180 | { | ||
181 | samsung_gpio_pull_t pull; | ||
182 | |||
183 | pull = samsung_gpio_getpull_updown(chip, off); | ||
184 | |||
185 | if (pull == 3) | ||
186 | pull = S3C_GPIO_PULL_UP; | ||
187 | |||
188 | return pull; | ||
189 | } | ||
190 | |||
191 | /* | ||
192 | * samsung_gpio_setcfg_2bit - Samsung 2bit style GPIO configuration. | ||
193 | * @chip: The gpio chip that is being configured. | ||
194 | * @off: The offset for the GPIO being configured. | ||
195 | * @cfg: The configuration value to set. | ||
196 | * | ||
197 | * This helper deal with the GPIO cases where the control register | ||
198 | * has two bits of configuration per gpio, which have the following | ||
199 | * functions: | ||
200 | * 00 = input | ||
201 | * 01 = output | ||
202 | * 1x = special function | ||
203 | */ | ||
204 | |||
205 | static int samsung_gpio_setcfg_2bit(struct samsung_gpio_chip *chip, | ||
206 | unsigned int off, unsigned int cfg) | ||
207 | { | ||
208 | void __iomem *reg = chip->base; | ||
209 | unsigned int shift = off * 2; | ||
210 | u32 con; | ||
211 | |||
212 | if (samsung_gpio_is_cfg_special(cfg)) { | ||
213 | cfg &= 0xf; | ||
214 | if (cfg > 3) | ||
215 | return -EINVAL; | ||
216 | |||
217 | cfg <<= shift; | ||
218 | } | ||
219 | |||
220 | con = __raw_readl(reg); | ||
221 | con &= ~(0x3 << shift); | ||
222 | con |= cfg; | ||
223 | __raw_writel(con, reg); | ||
224 | |||
225 | return 0; | ||
226 | } | ||
227 | |||
228 | /* | ||
229 | * samsung_gpio_getcfg_2bit - Samsung 2bit style GPIO configuration read. | ||
230 | * @chip: The gpio chip that is being configured. | ||
231 | * @off: The offset for the GPIO being configured. | ||
232 | * | ||
233 | * The reverse of samsung_gpio_setcfg_2bit(). Will return a value whicg | ||
234 | * could be directly passed back to samsung_gpio_setcfg_2bit(), from the | ||
235 | * S3C_GPIO_SPECIAL() macro. | ||
236 | */ | ||
237 | |||
238 | static unsigned int samsung_gpio_getcfg_2bit(struct samsung_gpio_chip *chip, | ||
239 | unsigned int off) | ||
240 | { | ||
241 | u32 con; | ||
242 | |||
243 | con = __raw_readl(chip->base); | ||
244 | con >>= off * 2; | ||
245 | con &= 3; | ||
246 | |||
247 | /* this conversion works for IN and OUT as well as special mode */ | ||
248 | return S3C_GPIO_SPECIAL(con); | ||
249 | } | ||
250 | |||
251 | /* | ||
252 | * samsung_gpio_setcfg_4bit - Samsung 4bit single register GPIO config. | ||
253 | * @chip: The gpio chip that is being configured. | ||
254 | * @off: The offset for the GPIO being configured. | ||
255 | * @cfg: The configuration value to set. | ||
256 | * | ||
257 | * This helper deal with the GPIO cases where the control register has 4 bits | ||
258 | * of control per GPIO, generally in the form of: | ||
259 | * 0000 = Input | ||
260 | * 0001 = Output | ||
261 | * others = Special functions (dependent on bank) | ||
262 | * | ||
263 | * Note, since the code to deal with the case where there are two control | ||
264 | * registers instead of one, we do not have a separate set of functions for | ||
265 | * each case. | ||
266 | */ | ||
267 | |||
268 | static int samsung_gpio_setcfg_4bit(struct samsung_gpio_chip *chip, | ||
269 | unsigned int off, unsigned int cfg) | ||
270 | { | ||
271 | void __iomem *reg = chip->base; | ||
272 | unsigned int shift = (off & 7) * 4; | ||
273 | u32 con; | ||
274 | |||
275 | if (off < 8 && chip->chip.ngpio > 8) | ||
276 | reg -= 4; | ||
277 | |||
278 | if (samsung_gpio_is_cfg_special(cfg)) { | ||
279 | cfg &= 0xf; | ||
280 | cfg <<= shift; | ||
281 | } | ||
282 | |||
283 | con = __raw_readl(reg); | ||
284 | con &= ~(0xf << shift); | ||
285 | con |= cfg; | ||
286 | __raw_writel(con, reg); | ||
287 | |||
288 | return 0; | ||
289 | } | ||
290 | |||
291 | /* | ||
292 | * samsung_gpio_getcfg_4bit - Samsung 4bit single register GPIO config read. | ||
293 | * @chip: The gpio chip that is being configured. | ||
294 | * @off: The offset for the GPIO being configured. | ||
295 | * | ||
296 | * The reverse of samsung_gpio_setcfg_4bit(), turning a gpio configuration | ||
297 | * register setting into a value the software can use, such as could be passed | ||
298 | * to samsung_gpio_setcfg_4bit(). | ||
299 | * | ||
300 | * @sa samsung_gpio_getcfg_2bit | ||
301 | */ | ||
302 | |||
303 | static unsigned samsung_gpio_getcfg_4bit(struct samsung_gpio_chip *chip, | ||
304 | unsigned int off) | ||
305 | { | ||
306 | void __iomem *reg = chip->base; | ||
307 | unsigned int shift = (off & 7) * 4; | ||
308 | u32 con; | ||
309 | |||
310 | if (off < 8 && chip->chip.ngpio > 8) | ||
311 | reg -= 4; | ||
312 | |||
313 | con = __raw_readl(reg); | ||
314 | con >>= shift; | ||
315 | con &= 0xf; | ||
316 | |||
317 | /* this conversion works for IN and OUT as well as special mode */ | ||
318 | return S3C_GPIO_SPECIAL(con); | ||
319 | } | ||
320 | |||
321 | /* | ||
322 | * s3c24xx_gpio_setcfg_abank - S3C24XX style GPIO configuration (Bank A) | ||
323 | * @chip: The gpio chip that is being configured. | ||
324 | * @off: The offset for the GPIO being configured. | ||
325 | * @cfg: The configuration value to set. | ||
326 | * | ||
327 | * This helper deal with the GPIO cases where the control register | ||
328 | * has one bit of configuration for the gpio, where setting the bit | ||
329 | * means the pin is in special function mode and unset means output. | ||
330 | */ | ||
331 | |||
332 | static int s3c24xx_gpio_setcfg_abank(struct samsung_gpio_chip *chip, | ||
333 | unsigned int off, unsigned int cfg) | ||
334 | { | ||
335 | void __iomem *reg = chip->base; | ||
336 | unsigned int shift = off; | ||
337 | u32 con; | ||
338 | |||
339 | if (samsung_gpio_is_cfg_special(cfg)) { | ||
340 | cfg &= 0xf; | ||
341 | |||
342 | /* Map output to 0, and SFN2 to 1 */ | ||
343 | cfg -= 1; | ||
344 | if (cfg > 1) | ||
345 | return -EINVAL; | ||
346 | |||
347 | cfg <<= shift; | ||
348 | } | ||
349 | |||
350 | con = __raw_readl(reg); | ||
351 | con &= ~(0x1 << shift); | ||
352 | con |= cfg; | ||
353 | __raw_writel(con, reg); | ||
354 | |||
355 | return 0; | ||
356 | } | ||
357 | |||
358 | /* | ||
359 | * s3c24xx_gpio_getcfg_abank - S3C24XX style GPIO configuration read (Bank A) | ||
360 | * @chip: The gpio chip that is being configured. | ||
361 | * @off: The offset for the GPIO being configured. | ||
362 | * | ||
363 | * The reverse of s3c24xx_gpio_setcfg_abank() turning an GPIO into a usable | ||
364 | * GPIO configuration value. | ||
365 | * | ||
366 | * @sa samsung_gpio_getcfg_2bit | ||
367 | * @sa samsung_gpio_getcfg_4bit | ||
368 | */ | ||
369 | |||
370 | static unsigned s3c24xx_gpio_getcfg_abank(struct samsung_gpio_chip *chip, | ||
371 | unsigned int off) | ||
372 | { | ||
373 | u32 con; | ||
374 | |||
375 | con = __raw_readl(chip->base); | ||
376 | con >>= off; | ||
377 | con &= 1; | ||
378 | con++; | ||
379 | |||
380 | return S3C_GPIO_SFN(con); | ||
381 | } | ||
382 | |||
383 | static int s5p64x0_gpio_setcfg_rbank(struct samsung_gpio_chip *chip, | ||
384 | unsigned int off, unsigned int cfg) | ||
385 | { | ||
386 | void __iomem *reg = chip->base; | ||
387 | unsigned int shift; | ||
388 | u32 con; | ||
389 | |||
390 | switch (off) { | ||
391 | case 0: | ||
392 | case 1: | ||
393 | case 2: | ||
394 | case 3: | ||
395 | case 4: | ||
396 | case 5: | ||
397 | shift = (off & 7) * 4; | ||
398 | reg -= 4; | ||
399 | break; | ||
400 | case 6: | ||
401 | shift = ((off + 1) & 7) * 4; | ||
402 | reg -= 4; | ||
403 | default: | ||
404 | shift = ((off + 1) & 7) * 4; | ||
405 | break; | ||
406 | } | ||
407 | |||
408 | if (samsung_gpio_is_cfg_special(cfg)) { | ||
409 | cfg &= 0xf; | ||
410 | cfg <<= shift; | ||
411 | } | ||
412 | |||
413 | con = __raw_readl(reg); | ||
414 | con &= ~(0xf << shift); | ||
415 | con |= cfg; | ||
416 | __raw_writel(con, reg); | ||
417 | |||
418 | return 0; | ||
419 | } | ||
420 | |||
421 | static void __init samsung_gpiolib_set_cfg(struct samsung_gpio_cfg *chipcfg, | ||
422 | int nr_chips) | ||
423 | { | ||
424 | for (; nr_chips > 0; nr_chips--, chipcfg++) { | ||
425 | if (!chipcfg->set_config) | ||
426 | chipcfg->set_config = samsung_gpio_setcfg_4bit; | ||
427 | if (!chipcfg->get_config) | ||
428 | chipcfg->get_config = samsung_gpio_getcfg_4bit; | ||
429 | if (!chipcfg->set_pull) | ||
430 | chipcfg->set_pull = samsung_gpio_setpull_updown; | ||
431 | if (!chipcfg->get_pull) | ||
432 | chipcfg->get_pull = samsung_gpio_getpull_updown; | ||
433 | } | ||
434 | } | ||
435 | |||
436 | struct samsung_gpio_cfg s3c24xx_gpiocfg_default = { | ||
437 | .set_config = samsung_gpio_setcfg_2bit, | ||
438 | .get_config = samsung_gpio_getcfg_2bit, | ||
439 | }; | ||
440 | |||
441 | static struct samsung_gpio_cfg s3c24xx_gpiocfg_banka = { | ||
442 | .set_config = s3c24xx_gpio_setcfg_abank, | ||
443 | .get_config = s3c24xx_gpio_getcfg_abank, | ||
444 | }; | ||
445 | |||
446 | static struct samsung_gpio_cfg exynos4_gpio_cfg = { | ||
447 | .set_pull = exynos4_gpio_setpull, | ||
448 | .get_pull = exynos4_gpio_getpull, | ||
449 | .set_config = samsung_gpio_setcfg_4bit, | ||
450 | .get_config = samsung_gpio_getcfg_4bit, | ||
451 | }; | ||
452 | |||
453 | static struct samsung_gpio_cfg s5p64x0_gpio_cfg_rbank = { | ||
454 | .cfg_eint = 0x3, | ||
455 | .set_config = s5p64x0_gpio_setcfg_rbank, | ||
456 | .get_config = samsung_gpio_getcfg_4bit, | ||
457 | .set_pull = samsung_gpio_setpull_updown, | ||
458 | .get_pull = samsung_gpio_getpull_updown, | ||
459 | }; | ||
460 | |||
461 | static struct samsung_gpio_cfg samsung_gpio_cfgs[] = { | ||
462 | { | ||
463 | .cfg_eint = 0x0, | ||
464 | }, { | ||
465 | .cfg_eint = 0x3, | ||
466 | }, { | ||
467 | .cfg_eint = 0x7, | ||
468 | }, { | ||
469 | .cfg_eint = 0xF, | ||
470 | }, { | ||
471 | .cfg_eint = 0x0, | ||
472 | .set_config = samsung_gpio_setcfg_2bit, | ||
473 | .get_config = samsung_gpio_getcfg_2bit, | ||
474 | }, { | ||
475 | .cfg_eint = 0x2, | ||
476 | .set_config = samsung_gpio_setcfg_2bit, | ||
477 | .get_config = samsung_gpio_getcfg_2bit, | ||
478 | }, { | ||
479 | .cfg_eint = 0x3, | ||
480 | .set_config = samsung_gpio_setcfg_2bit, | ||
481 | .get_config = samsung_gpio_getcfg_2bit, | ||
482 | }, { | ||
483 | .set_config = samsung_gpio_setcfg_2bit, | ||
484 | .get_config = samsung_gpio_getcfg_2bit, | ||
485 | }, | ||
486 | }; | ||
487 | |||
488 | /* | ||
489 | * Default routines for controlling GPIO, based on the original S3C24XX | ||
490 | * GPIO functions which deal with the case where each gpio bank of the | ||
491 | * chip is as following: | ||
492 | * | ||
493 | * base + 0x00: Control register, 2 bits per gpio | ||
494 | * gpio n: 2 bits starting at (2*n) | ||
495 | * 00 = input, 01 = output, others mean special-function | ||
496 | * base + 0x04: Data register, 1 bit per gpio | ||
497 | * bit n: data bit n | ||
498 | */ | ||
499 | |||
500 | static int samsung_gpiolib_2bit_input(struct gpio_chip *chip, unsigned offset) | ||
501 | { | ||
502 | struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip); | ||
503 | void __iomem *base = ourchip->base; | ||
504 | unsigned long flags; | ||
505 | unsigned long con; | ||
506 | |||
507 | samsung_gpio_lock(ourchip, flags); | ||
508 | |||
509 | con = __raw_readl(base + 0x00); | ||
510 | con &= ~(3 << (offset * 2)); | ||
511 | |||
512 | __raw_writel(con, base + 0x00); | ||
513 | |||
514 | samsung_gpio_unlock(ourchip, flags); | ||
515 | return 0; | ||
516 | } | ||
517 | |||
518 | static int samsung_gpiolib_2bit_output(struct gpio_chip *chip, | ||
519 | unsigned offset, int value) | ||
520 | { | ||
521 | struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip); | ||
522 | void __iomem *base = ourchip->base; | ||
523 | unsigned long flags; | ||
524 | unsigned long dat; | ||
525 | unsigned long con; | ||
526 | |||
527 | samsung_gpio_lock(ourchip, flags); | ||
528 | |||
529 | dat = __raw_readl(base + 0x04); | ||
530 | dat &= ~(1 << offset); | ||
531 | if (value) | ||
532 | dat |= 1 << offset; | ||
533 | __raw_writel(dat, base + 0x04); | ||
534 | |||
535 | con = __raw_readl(base + 0x00); | ||
536 | con &= ~(3 << (offset * 2)); | ||
537 | con |= 1 << (offset * 2); | ||
538 | |||
539 | __raw_writel(con, base + 0x00); | ||
540 | __raw_writel(dat, base + 0x04); | ||
541 | |||
542 | samsung_gpio_unlock(ourchip, flags); | ||
543 | return 0; | ||
544 | } | ||
545 | |||
546 | /* | ||
547 | * The samsung_gpiolib_4bit routines are to control the gpio banks where | ||
548 | * the gpio configuration register (GPxCON) has 4 bits per GPIO, as the | ||
549 | * following example: | ||
550 | * | ||
551 | * base + 0x00: Control register, 4 bits per gpio | ||
552 | * gpio n: 4 bits starting at (4*n) | ||
553 | * 0000 = input, 0001 = output, others mean special-function | ||
554 | * base + 0x04: Data register, 1 bit per gpio | ||
555 | * bit n: data bit n | ||
556 | * | ||
557 | * Note, since the data register is one bit per gpio and is at base + 0x4 | ||
558 | * we can use samsung_gpiolib_get and samsung_gpiolib_set to change the | ||
559 | * state of the output. | ||
560 | */ | ||
561 | |||
562 | static int samsung_gpiolib_4bit_input(struct gpio_chip *chip, | ||
563 | unsigned int offset) | ||
564 | { | ||
565 | struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip); | ||
566 | void __iomem *base = ourchip->base; | ||
567 | unsigned long con; | ||
568 | |||
569 | con = __raw_readl(base + GPIOCON_OFF); | ||
570 | con &= ~(0xf << con_4bit_shift(offset)); | ||
571 | __raw_writel(con, base + GPIOCON_OFF); | ||
572 | |||
573 | gpio_dbg("%s: %p: CON now %08lx\n", __func__, base, con); | ||
574 | |||
575 | return 0; | ||
576 | } | ||
577 | |||
578 | static int samsung_gpiolib_4bit_output(struct gpio_chip *chip, | ||
579 | unsigned int offset, int value) | ||
580 | { | ||
581 | struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip); | ||
582 | void __iomem *base = ourchip->base; | ||
583 | unsigned long con; | ||
584 | unsigned long dat; | ||
585 | |||
586 | con = __raw_readl(base + GPIOCON_OFF); | ||
587 | con &= ~(0xf << con_4bit_shift(offset)); | ||
588 | con |= 0x1 << con_4bit_shift(offset); | ||
589 | |||
590 | dat = __raw_readl(base + GPIODAT_OFF); | ||
591 | |||
592 | if (value) | ||
593 | dat |= 1 << offset; | ||
594 | else | ||
595 | dat &= ~(1 << offset); | ||
596 | |||
597 | __raw_writel(dat, base + GPIODAT_OFF); | ||
598 | __raw_writel(con, base + GPIOCON_OFF); | ||
599 | __raw_writel(dat, base + GPIODAT_OFF); | ||
600 | |||
601 | gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat); | ||
602 | |||
603 | return 0; | ||
604 | } | ||
605 | |||
606 | /* | ||
607 | * The next set of routines are for the case where the GPIO configuration | ||
608 | * registers are 4 bits per GPIO but there is more than one register (the | ||
609 | * bank has more than 8 GPIOs. | ||
610 | * | ||
611 | * This case is the similar to the 4 bit case, but the registers are as | ||
612 | * follows: | ||
613 | * | ||
614 | * base + 0x00: Control register, 4 bits per gpio (lower 8 GPIOs) | ||
615 | * gpio n: 4 bits starting at (4*n) | ||
616 | * 0000 = input, 0001 = output, others mean special-function | ||
617 | * base + 0x04: Control register, 4 bits per gpio (up to 8 additions GPIOs) | ||
618 | * gpio n: 4 bits starting at (4*n) | ||
619 | * 0000 = input, 0001 = output, others mean special-function | ||
620 | * base + 0x08: Data register, 1 bit per gpio | ||
621 | * bit n: data bit n | ||
622 | * | ||
623 | * To allow us to use the samsung_gpiolib_get and samsung_gpiolib_set | ||
624 | * routines we store the 'base + 0x4' address so that these routines see | ||
625 | * the data register at ourchip->base + 0x04. | ||
626 | */ | ||
627 | |||
628 | static int samsung_gpiolib_4bit2_input(struct gpio_chip *chip, | ||
629 | unsigned int offset) | ||
630 | { | ||
631 | struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip); | ||
632 | void __iomem *base = ourchip->base; | ||
633 | void __iomem *regcon = base; | ||
634 | unsigned long con; | ||
635 | |||
636 | if (offset > 7) | ||
637 | offset -= 8; | ||
638 | else | ||
639 | regcon -= 4; | ||
640 | |||
641 | con = __raw_readl(regcon); | ||
642 | con &= ~(0xf << con_4bit_shift(offset)); | ||
643 | __raw_writel(con, regcon); | ||
644 | |||
645 | gpio_dbg("%s: %p: CON %08lx\n", __func__, base, con); | ||
646 | |||
647 | return 0; | ||
648 | } | ||
649 | |||
650 | static int samsung_gpiolib_4bit2_output(struct gpio_chip *chip, | ||
651 | unsigned int offset, int value) | ||
652 | { | ||
653 | struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip); | ||
654 | void __iomem *base = ourchip->base; | ||
655 | void __iomem *regcon = base; | ||
656 | unsigned long con; | ||
657 | unsigned long dat; | ||
658 | unsigned con_offset = offset; | ||
659 | |||
660 | if (con_offset > 7) | ||
661 | con_offset -= 8; | ||
662 | else | ||
663 | regcon -= 4; | ||
664 | |||
665 | con = __raw_readl(regcon); | ||
666 | con &= ~(0xf << con_4bit_shift(con_offset)); | ||
667 | con |= 0x1 << con_4bit_shift(con_offset); | ||
668 | |||
669 | dat = __raw_readl(base + GPIODAT_OFF); | ||
670 | |||
671 | if (value) | ||
672 | dat |= 1 << offset; | ||
673 | else | ||
674 | dat &= ~(1 << offset); | ||
675 | |||
676 | __raw_writel(dat, base + GPIODAT_OFF); | ||
677 | __raw_writel(con, regcon); | ||
678 | __raw_writel(dat, base + GPIODAT_OFF); | ||
679 | |||
680 | gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat); | ||
681 | |||
682 | return 0; | ||
683 | } | ||
684 | |||
685 | /* The next set of routines are for the case of s3c24xx bank a */ | ||
686 | |||
687 | static int s3c24xx_gpiolib_banka_input(struct gpio_chip *chip, unsigned offset) | ||
688 | { | ||
689 | return -EINVAL; | ||
690 | } | ||
691 | |||
692 | static int s3c24xx_gpiolib_banka_output(struct gpio_chip *chip, | ||
693 | unsigned offset, int value) | ||
694 | { | ||
695 | struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip); | ||
696 | void __iomem *base = ourchip->base; | ||
697 | unsigned long flags; | ||
698 | unsigned long dat; | ||
699 | unsigned long con; | ||
700 | |||
701 | local_irq_save(flags); | ||
702 | |||
703 | con = __raw_readl(base + 0x00); | ||
704 | dat = __raw_readl(base + 0x04); | ||
705 | |||
706 | dat &= ~(1 << offset); | ||
707 | if (value) | ||
708 | dat |= 1 << offset; | ||
709 | |||
710 | __raw_writel(dat, base + 0x04); | ||
711 | |||
712 | con &= ~(1 << offset); | ||
713 | |||
714 | __raw_writel(con, base + 0x00); | ||
715 | __raw_writel(dat, base + 0x04); | ||
716 | |||
717 | local_irq_restore(flags); | ||
718 | return 0; | ||
719 | } | ||
720 | |||
721 | /* The next set of routines are for the case of s5p64x0 bank r */ | ||
722 | |||
723 | static int s5p64x0_gpiolib_rbank_input(struct gpio_chip *chip, | ||
724 | unsigned int offset) | ||
725 | { | ||
726 | struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip); | ||
727 | void __iomem *base = ourchip->base; | ||
728 | void __iomem *regcon = base; | ||
729 | unsigned long con; | ||
730 | unsigned long flags; | ||
731 | |||
732 | switch (offset) { | ||
733 | case 6: | ||
734 | offset += 1; | ||
735 | case 0: | ||
736 | case 1: | ||
737 | case 2: | ||
738 | case 3: | ||
739 | case 4: | ||
740 | case 5: | ||
741 | regcon -= 4; | ||
742 | break; | ||
743 | default: | ||
744 | offset -= 7; | ||
745 | break; | ||
746 | } | ||
747 | |||
748 | samsung_gpio_lock(ourchip, flags); | ||
749 | |||
750 | con = __raw_readl(regcon); | ||
751 | con &= ~(0xf << con_4bit_shift(offset)); | ||
752 | __raw_writel(con, regcon); | ||
753 | |||
754 | samsung_gpio_unlock(ourchip, flags); | ||
755 | |||
756 | return 0; | ||
757 | } | ||
758 | |||
759 | static int s5p64x0_gpiolib_rbank_output(struct gpio_chip *chip, | ||
760 | unsigned int offset, int value) | ||
761 | { | ||
762 | struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip); | ||
763 | void __iomem *base = ourchip->base; | ||
764 | void __iomem *regcon = base; | ||
765 | unsigned long con; | ||
766 | unsigned long dat; | ||
767 | unsigned long flags; | ||
768 | unsigned con_offset = offset; | ||
769 | |||
770 | switch (con_offset) { | ||
771 | case 6: | ||
772 | con_offset += 1; | ||
773 | case 0: | ||
774 | case 1: | ||
775 | case 2: | ||
776 | case 3: | ||
777 | case 4: | ||
778 | case 5: | ||
779 | regcon -= 4; | ||
780 | break; | ||
781 | default: | ||
782 | con_offset -= 7; | ||
783 | break; | ||
784 | } | ||
785 | |||
786 | samsung_gpio_lock(ourchip, flags); | ||
787 | |||
788 | con = __raw_readl(regcon); | ||
789 | con &= ~(0xf << con_4bit_shift(con_offset)); | ||
790 | con |= 0x1 << con_4bit_shift(con_offset); | ||
791 | |||
792 | dat = __raw_readl(base + GPIODAT_OFF); | ||
793 | if (value) | ||
794 | dat |= 1 << offset; | ||
795 | else | ||
796 | dat &= ~(1 << offset); | ||
797 | |||
798 | __raw_writel(con, regcon); | ||
799 | __raw_writel(dat, base + GPIODAT_OFF); | ||
800 | |||
801 | samsung_gpio_unlock(ourchip, flags); | ||
802 | |||
803 | return 0; | ||
804 | } | ||
805 | |||
806 | static void samsung_gpiolib_set(struct gpio_chip *chip, | ||
807 | unsigned offset, int value) | ||
808 | { | ||
809 | struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip); | ||
810 | void __iomem *base = ourchip->base; | ||
811 | unsigned long flags; | ||
812 | unsigned long dat; | ||
813 | |||
814 | samsung_gpio_lock(ourchip, flags); | ||
815 | |||
816 | dat = __raw_readl(base + 0x04); | ||
817 | dat &= ~(1 << offset); | ||
818 | if (value) | ||
819 | dat |= 1 << offset; | ||
820 | __raw_writel(dat, base + 0x04); | ||
821 | |||
822 | samsung_gpio_unlock(ourchip, flags); | ||
823 | } | ||
824 | |||
825 | static int samsung_gpiolib_get(struct gpio_chip *chip, unsigned offset) | ||
826 | { | ||
827 | struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip); | ||
828 | unsigned long val; | ||
829 | |||
830 | val = __raw_readl(ourchip->base + 0x04); | ||
831 | val >>= offset; | ||
832 | val &= 1; | ||
833 | |||
834 | return val; | ||
835 | } | ||
836 | |||
837 | /* | ||
838 | * CONFIG_S3C_GPIO_TRACK enables the tracking of the s3c specific gpios | ||
839 | * for use with the configuration calls, and other parts of the s3c gpiolib | ||
840 | * support code. | ||
841 | * | ||
842 | * Not all s3c support code will need this, as some configurations of cpu | ||
843 | * may only support one or two different configuration options and have an | ||
844 | * easy gpio to samsung_gpio_chip mapping function. If this is the case, then | ||
845 | * the machine support file should provide its own samsung_gpiolib_getchip() | ||
846 | * and any other necessary functions. | ||
847 | */ | ||
848 | |||
849 | #ifdef CONFIG_S3C_GPIO_TRACK | ||
850 | struct samsung_gpio_chip *s3c_gpios[S3C_GPIO_END]; | ||
851 | |||
852 | static __init void s3c_gpiolib_track(struct samsung_gpio_chip *chip) | ||
853 | { | ||
854 | unsigned int gpn; | ||
855 | int i; | ||
856 | |||
857 | gpn = chip->chip.base; | ||
858 | for (i = 0; i < chip->chip.ngpio; i++, gpn++) { | ||
859 | BUG_ON(gpn >= ARRAY_SIZE(s3c_gpios)); | ||
860 | s3c_gpios[gpn] = chip; | ||
861 | } | ||
862 | } | ||
863 | #endif /* CONFIG_S3C_GPIO_TRACK */ | ||
864 | |||
865 | /* | ||
866 | * samsung_gpiolib_add() - add the Samsung gpio_chip. | ||
867 | * @chip: The chip to register | ||
868 | * | ||
869 | * This is a wrapper to gpiochip_add() that takes our specific gpio chip | ||
870 | * information and makes the necessary alterations for the platform and | ||
871 | * notes the information for use with the configuration systems and any | ||
872 | * other parts of the system. | ||
873 | */ | ||
874 | |||
875 | static void __init samsung_gpiolib_add(struct samsung_gpio_chip *chip) | ||
876 | { | ||
877 | struct gpio_chip *gc = &chip->chip; | ||
878 | int ret; | ||
879 | |||
880 | BUG_ON(!chip->base); | ||
881 | BUG_ON(!gc->label); | ||
882 | BUG_ON(!gc->ngpio); | ||
883 | |||
884 | spin_lock_init(&chip->lock); | ||
885 | |||
886 | if (!gc->direction_input) | ||
887 | gc->direction_input = samsung_gpiolib_2bit_input; | ||
888 | if (!gc->direction_output) | ||
889 | gc->direction_output = samsung_gpiolib_2bit_output; | ||
890 | if (!gc->set) | ||
891 | gc->set = samsung_gpiolib_set; | ||
892 | if (!gc->get) | ||
893 | gc->get = samsung_gpiolib_get; | ||
894 | |||
895 | #ifdef CONFIG_PM | ||
896 | if (chip->pm != NULL) { | ||
897 | if (!chip->pm->save || !chip->pm->resume) | ||
898 | printk(KERN_ERR "gpio: %s has missing PM functions\n", | ||
899 | gc->label); | ||
900 | } else | ||
901 | printk(KERN_ERR "gpio: %s has no PM function\n", gc->label); | ||
902 | #endif | ||
903 | |||
904 | /* gpiochip_add() prints own failure message on error. */ | ||
905 | ret = gpiochip_add(gc); | ||
906 | if (ret >= 0) | ||
907 | s3c_gpiolib_track(chip); | ||
908 | } | ||
909 | |||
910 | static void __init s3c24xx_gpiolib_add_chips(struct samsung_gpio_chip *chip, | ||
911 | int nr_chips, void __iomem *base) | ||
912 | { | ||
913 | int i; | ||
914 | struct gpio_chip *gc = &chip->chip; | ||
915 | |||
916 | for (i = 0 ; i < nr_chips; i++, chip++) { | ||
917 | if (!chip->config) | ||
918 | chip->config = &s3c24xx_gpiocfg_default; | ||
919 | if (!chip->pm) | ||
920 | chip->pm = __gpio_pm(&samsung_gpio_pm_2bit); | ||
921 | if ((base != NULL) && (chip->base == NULL)) | ||
922 | chip->base = base + ((i) * 0x10); | ||
923 | |||
924 | if (!gc->direction_input) | ||
925 | gc->direction_input = samsung_gpiolib_2bit_input; | ||
926 | if (!gc->direction_output) | ||
927 | gc->direction_output = samsung_gpiolib_2bit_output; | ||
928 | |||
929 | samsung_gpiolib_add(chip); | ||
930 | } | ||
931 | } | ||
932 | |||
933 | static void __init samsung_gpiolib_add_2bit_chips(struct samsung_gpio_chip *chip, | ||
934 | int nr_chips, void __iomem *base, | ||
935 | unsigned int offset) | ||
936 | { | ||
937 | int i; | ||
938 | |||
939 | for (i = 0 ; i < nr_chips; i++, chip++) { | ||
940 | chip->chip.direction_input = samsung_gpiolib_2bit_input; | ||
941 | chip->chip.direction_output = samsung_gpiolib_2bit_output; | ||
942 | |||
943 | if (!chip->config) | ||
944 | chip->config = &samsung_gpio_cfgs[7]; | ||
945 | if (!chip->pm) | ||
946 | chip->pm = __gpio_pm(&samsung_gpio_pm_2bit); | ||
947 | if ((base != NULL) && (chip->base == NULL)) | ||
948 | chip->base = base + ((i) * offset); | ||
949 | |||
950 | samsung_gpiolib_add(chip); | ||
951 | } | ||
952 | } | ||
953 | |||
954 | /* | ||
955 | * samsung_gpiolib_add_4bit_chips - 4bit single register GPIO config. | ||
956 | * @chip: The gpio chip that is being configured. | ||
957 | * @nr_chips: The no of chips (gpio ports) for the GPIO being configured. | ||
958 | * | ||
959 | * This helper deal with the GPIO cases where the control register has 4 bits | ||
960 | * of control per GPIO, generally in the form of: | ||
961 | * 0000 = Input | ||
962 | * 0001 = Output | ||
963 | * others = Special functions (dependent on bank) | ||
964 | * | ||
965 | * Note, since the code to deal with the case where there are two control | ||
966 | * registers instead of one, we do not have a separate set of function | ||
967 | * (samsung_gpiolib_add_4bit2_chips)for each case. | ||
968 | */ | ||
969 | |||
970 | static void __init samsung_gpiolib_add_4bit_chips(struct samsung_gpio_chip *chip, | ||
971 | int nr_chips, void __iomem *base) | ||
972 | { | ||
973 | int i; | ||
974 | |||
975 | for (i = 0 ; i < nr_chips; i++, chip++) { | ||
976 | chip->chip.direction_input = samsung_gpiolib_4bit_input; | ||
977 | chip->chip.direction_output = samsung_gpiolib_4bit_output; | ||
978 | |||
979 | if (!chip->config) | ||
980 | chip->config = &samsung_gpio_cfgs[2]; | ||
981 | if (!chip->pm) | ||
982 | chip->pm = __gpio_pm(&samsung_gpio_pm_4bit); | ||
983 | if ((base != NULL) && (chip->base == NULL)) | ||
984 | chip->base = base + ((i) * 0x20); | ||
985 | |||
986 | samsung_gpiolib_add(chip); | ||
987 | } | ||
988 | } | ||
989 | |||
990 | static void __init samsung_gpiolib_add_4bit2_chips(struct samsung_gpio_chip *chip, | ||
991 | int nr_chips) | ||
992 | { | ||
993 | for (; nr_chips > 0; nr_chips--, chip++) { | ||
994 | chip->chip.direction_input = samsung_gpiolib_4bit2_input; | ||
995 | chip->chip.direction_output = samsung_gpiolib_4bit2_output; | ||
996 | |||
997 | if (!chip->config) | ||
998 | chip->config = &samsung_gpio_cfgs[2]; | ||
999 | if (!chip->pm) | ||
1000 | chip->pm = __gpio_pm(&samsung_gpio_pm_4bit); | ||
1001 | |||
1002 | samsung_gpiolib_add(chip); | ||
1003 | } | ||
1004 | } | ||
1005 | |||
1006 | static void __init s5p64x0_gpiolib_add_rbank(struct samsung_gpio_chip *chip, | ||
1007 | int nr_chips) | ||
1008 | { | ||
1009 | for (; nr_chips > 0; nr_chips--, chip++) { | ||
1010 | chip->chip.direction_input = s5p64x0_gpiolib_rbank_input; | ||
1011 | chip->chip.direction_output = s5p64x0_gpiolib_rbank_output; | ||
1012 | |||
1013 | if (!chip->pm) | ||
1014 | chip->pm = __gpio_pm(&samsung_gpio_pm_4bit); | ||
1015 | |||
1016 | samsung_gpiolib_add(chip); | ||
1017 | } | ||
1018 | } | ||
1019 | |||
1020 | int samsung_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset) | ||
1021 | { | ||
1022 | struct samsung_gpio_chip *samsung_chip = container_of(chip, struct samsung_gpio_chip, chip); | ||
1023 | |||
1024 | return samsung_chip->irq_base + offset; | ||
1025 | } | ||
1026 | |||
1027 | #ifdef CONFIG_PLAT_S3C24XX | ||
1028 | static int s3c24xx_gpiolib_fbank_to_irq(struct gpio_chip *chip, unsigned offset) | ||
1029 | { | ||
1030 | if (offset < 4) | ||
1031 | return IRQ_EINT0 + offset; | ||
1032 | |||
1033 | if (offset < 8) | ||
1034 | return IRQ_EINT4 + offset - 4; | ||
1035 | |||
1036 | return -EINVAL; | ||
1037 | } | ||
1038 | #endif | ||
1039 | |||
1040 | #ifdef CONFIG_PLAT_S3C64XX | ||
1041 | static int s3c64xx_gpiolib_mbank_to_irq(struct gpio_chip *chip, unsigned pin) | ||
1042 | { | ||
1043 | return pin < 5 ? IRQ_EINT(23) + pin : -ENXIO; | ||
1044 | } | ||
1045 | |||
1046 | static int s3c64xx_gpiolib_lbank_to_irq(struct gpio_chip *chip, unsigned pin) | ||
1047 | { | ||
1048 | return pin >= 8 ? IRQ_EINT(16) + pin - 8 : -ENXIO; | ||
1049 | } | ||
1050 | #endif | ||
1051 | |||
1052 | struct samsung_gpio_chip s3c24xx_gpios[] = { | ||
1053 | #ifdef CONFIG_PLAT_S3C24XX | ||
1054 | { | ||
1055 | .config = &s3c24xx_gpiocfg_banka, | ||
1056 | .chip = { | ||
1057 | .base = S3C2410_GPA(0), | ||
1058 | .owner = THIS_MODULE, | ||
1059 | .label = "GPIOA", | ||
1060 | .ngpio = 24, | ||
1061 | .direction_input = s3c24xx_gpiolib_banka_input, | ||
1062 | .direction_output = s3c24xx_gpiolib_banka_output, | ||
1063 | }, | ||
1064 | }, { | ||
1065 | .chip = { | ||
1066 | .base = S3C2410_GPB(0), | ||
1067 | .owner = THIS_MODULE, | ||
1068 | .label = "GPIOB", | ||
1069 | .ngpio = 16, | ||
1070 | }, | ||
1071 | }, { | ||
1072 | .chip = { | ||
1073 | .base = S3C2410_GPC(0), | ||
1074 | .owner = THIS_MODULE, | ||
1075 | .label = "GPIOC", | ||
1076 | .ngpio = 16, | ||
1077 | }, | ||
1078 | }, { | ||
1079 | .chip = { | ||
1080 | .base = S3C2410_GPD(0), | ||
1081 | .owner = THIS_MODULE, | ||
1082 | .label = "GPIOD", | ||
1083 | .ngpio = 16, | ||
1084 | }, | ||
1085 | }, { | ||
1086 | .chip = { | ||
1087 | .base = S3C2410_GPE(0), | ||
1088 | .label = "GPIOE", | ||
1089 | .owner = THIS_MODULE, | ||
1090 | .ngpio = 16, | ||
1091 | }, | ||
1092 | }, { | ||
1093 | .chip = { | ||
1094 | .base = S3C2410_GPF(0), | ||
1095 | .owner = THIS_MODULE, | ||
1096 | .label = "GPIOF", | ||
1097 | .ngpio = 8, | ||
1098 | .to_irq = s3c24xx_gpiolib_fbank_to_irq, | ||
1099 | }, | ||
1100 | }, { | ||
1101 | .irq_base = IRQ_EINT8, | ||
1102 | .chip = { | ||
1103 | .base = S3C2410_GPG(0), | ||
1104 | .owner = THIS_MODULE, | ||
1105 | .label = "GPIOG", | ||
1106 | .ngpio = 16, | ||
1107 | .to_irq = samsung_gpiolib_to_irq, | ||
1108 | }, | ||
1109 | }, { | ||
1110 | .chip = { | ||
1111 | .base = S3C2410_GPH(0), | ||
1112 | .owner = THIS_MODULE, | ||
1113 | .label = "GPIOH", | ||
1114 | .ngpio = 11, | ||
1115 | }, | ||
1116 | }, | ||
1117 | /* GPIOS for the S3C2443 and later devices. */ | ||
1118 | { | ||
1119 | .base = S3C2440_GPJCON, | ||
1120 | .chip = { | ||
1121 | .base = S3C2410_GPJ(0), | ||
1122 | .owner = THIS_MODULE, | ||
1123 | .label = "GPIOJ", | ||
1124 | .ngpio = 16, | ||
1125 | }, | ||
1126 | }, { | ||
1127 | .base = S3C2443_GPKCON, | ||
1128 | .chip = { | ||
1129 | .base = S3C2410_GPK(0), | ||
1130 | .owner = THIS_MODULE, | ||
1131 | .label = "GPIOK", | ||
1132 | .ngpio = 16, | ||
1133 | }, | ||
1134 | }, { | ||
1135 | .base = S3C2443_GPLCON, | ||
1136 | .chip = { | ||
1137 | .base = S3C2410_GPL(0), | ||
1138 | .owner = THIS_MODULE, | ||
1139 | .label = "GPIOL", | ||
1140 | .ngpio = 15, | ||
1141 | }, | ||
1142 | }, { | ||
1143 | .base = S3C2443_GPMCON, | ||
1144 | .chip = { | ||
1145 | .base = S3C2410_GPM(0), | ||
1146 | .owner = THIS_MODULE, | ||
1147 | .label = "GPIOM", | ||
1148 | .ngpio = 2, | ||
1149 | }, | ||
1150 | }, | ||
1151 | #endif | ||
1152 | }; | ||
1153 | |||
1154 | /* | ||
1155 | * GPIO bank summary: | ||
1156 | * | ||
1157 | * Bank GPIOs Style SlpCon ExtInt Group | ||
1158 | * A 8 4Bit Yes 1 | ||
1159 | * B 7 4Bit Yes 1 | ||
1160 | * C 8 4Bit Yes 2 | ||
1161 | * D 5 4Bit Yes 3 | ||
1162 | * E 5 4Bit Yes None | ||
1163 | * F 16 2Bit Yes 4 [1] | ||
1164 | * G 7 4Bit Yes 5 | ||
1165 | * H 10 4Bit[2] Yes 6 | ||
1166 | * I 16 2Bit Yes None | ||
1167 | * J 12 2Bit Yes None | ||
1168 | * K 16 4Bit[2] No None | ||
1169 | * L 15 4Bit[2] No None | ||
1170 | * M 6 4Bit No IRQ_EINT | ||
1171 | * N 16 2Bit No IRQ_EINT | ||
1172 | * O 16 2Bit Yes 7 | ||
1173 | * P 15 2Bit Yes 8 | ||
1174 | * Q 9 2Bit Yes 9 | ||
1175 | * | ||
1176 | * [1] BANKF pins 14,15 do not form part of the external interrupt sources | ||
1177 | * [2] BANK has two control registers, GPxCON0 and GPxCON1 | ||
1178 | */ | ||
1179 | |||
1180 | static struct samsung_gpio_chip s3c64xx_gpios_4bit[] = { | ||
1181 | #ifdef CONFIG_PLAT_S3C64XX | ||
1182 | { | ||
1183 | .chip = { | ||
1184 | .base = S3C64XX_GPA(0), | ||
1185 | .ngpio = S3C64XX_GPIO_A_NR, | ||
1186 | .label = "GPA", | ||
1187 | }, | ||
1188 | }, { | ||
1189 | .chip = { | ||
1190 | .base = S3C64XX_GPB(0), | ||
1191 | .ngpio = S3C64XX_GPIO_B_NR, | ||
1192 | .label = "GPB", | ||
1193 | }, | ||
1194 | }, { | ||
1195 | .chip = { | ||
1196 | .base = S3C64XX_GPC(0), | ||
1197 | .ngpio = S3C64XX_GPIO_C_NR, | ||
1198 | .label = "GPC", | ||
1199 | }, | ||
1200 | }, { | ||
1201 | .chip = { | ||
1202 | .base = S3C64XX_GPD(0), | ||
1203 | .ngpio = S3C64XX_GPIO_D_NR, | ||
1204 | .label = "GPD", | ||
1205 | }, | ||
1206 | }, { | ||
1207 | .config = &samsung_gpio_cfgs[0], | ||
1208 | .chip = { | ||
1209 | .base = S3C64XX_GPE(0), | ||
1210 | .ngpio = S3C64XX_GPIO_E_NR, | ||
1211 | .label = "GPE", | ||
1212 | }, | ||
1213 | }, { | ||
1214 | .base = S3C64XX_GPG_BASE, | ||
1215 | .chip = { | ||
1216 | .base = S3C64XX_GPG(0), | ||
1217 | .ngpio = S3C64XX_GPIO_G_NR, | ||
1218 | .label = "GPG", | ||
1219 | }, | ||
1220 | }, { | ||
1221 | .base = S3C64XX_GPM_BASE, | ||
1222 | .config = &samsung_gpio_cfgs[1], | ||
1223 | .chip = { | ||
1224 | .base = S3C64XX_GPM(0), | ||
1225 | .ngpio = S3C64XX_GPIO_M_NR, | ||
1226 | .label = "GPM", | ||
1227 | .to_irq = s3c64xx_gpiolib_mbank_to_irq, | ||
1228 | }, | ||
1229 | }, | ||
1230 | #endif | ||
1231 | }; | ||
1232 | |||
1233 | static struct samsung_gpio_chip s3c64xx_gpios_4bit2[] = { | ||
1234 | #ifdef CONFIG_PLAT_S3C64XX | ||
1235 | { | ||
1236 | .base = S3C64XX_GPH_BASE + 0x4, | ||
1237 | .chip = { | ||
1238 | .base = S3C64XX_GPH(0), | ||
1239 | .ngpio = S3C64XX_GPIO_H_NR, | ||
1240 | .label = "GPH", | ||
1241 | }, | ||
1242 | }, { | ||
1243 | .base = S3C64XX_GPK_BASE + 0x4, | ||
1244 | .config = &samsung_gpio_cfgs[0], | ||
1245 | .chip = { | ||
1246 | .base = S3C64XX_GPK(0), | ||
1247 | .ngpio = S3C64XX_GPIO_K_NR, | ||
1248 | .label = "GPK", | ||
1249 | }, | ||
1250 | }, { | ||
1251 | .base = S3C64XX_GPL_BASE + 0x4, | ||
1252 | .config = &samsung_gpio_cfgs[1], | ||
1253 | .chip = { | ||
1254 | .base = S3C64XX_GPL(0), | ||
1255 | .ngpio = S3C64XX_GPIO_L_NR, | ||
1256 | .label = "GPL", | ||
1257 | .to_irq = s3c64xx_gpiolib_lbank_to_irq, | ||
1258 | }, | ||
1259 | }, | ||
1260 | #endif | ||
1261 | }; | ||
1262 | |||
1263 | static struct samsung_gpio_chip s3c64xx_gpios_2bit[] = { | ||
1264 | #ifdef CONFIG_PLAT_S3C64XX | ||
1265 | { | ||
1266 | .base = S3C64XX_GPF_BASE, | ||
1267 | .config = &samsung_gpio_cfgs[6], | ||
1268 | .chip = { | ||
1269 | .base = S3C64XX_GPF(0), | ||
1270 | .ngpio = S3C64XX_GPIO_F_NR, | ||
1271 | .label = "GPF", | ||
1272 | }, | ||
1273 | }, { | ||
1274 | .config = &samsung_gpio_cfgs[7], | ||
1275 | .chip = { | ||
1276 | .base = S3C64XX_GPI(0), | ||
1277 | .ngpio = S3C64XX_GPIO_I_NR, | ||
1278 | .label = "GPI", | ||
1279 | }, | ||
1280 | }, { | ||
1281 | .config = &samsung_gpio_cfgs[7], | ||
1282 | .chip = { | ||
1283 | .base = S3C64XX_GPJ(0), | ||
1284 | .ngpio = S3C64XX_GPIO_J_NR, | ||
1285 | .label = "GPJ", | ||
1286 | }, | ||
1287 | }, { | ||
1288 | .config = &samsung_gpio_cfgs[6], | ||
1289 | .chip = { | ||
1290 | .base = S3C64XX_GPO(0), | ||
1291 | .ngpio = S3C64XX_GPIO_O_NR, | ||
1292 | .label = "GPO", | ||
1293 | }, | ||
1294 | }, { | ||
1295 | .config = &samsung_gpio_cfgs[6], | ||
1296 | .chip = { | ||
1297 | .base = S3C64XX_GPP(0), | ||
1298 | .ngpio = S3C64XX_GPIO_P_NR, | ||
1299 | .label = "GPP", | ||
1300 | }, | ||
1301 | }, { | ||
1302 | .config = &samsung_gpio_cfgs[6], | ||
1303 | .chip = { | ||
1304 | .base = S3C64XX_GPQ(0), | ||
1305 | .ngpio = S3C64XX_GPIO_Q_NR, | ||
1306 | .label = "GPQ", | ||
1307 | }, | ||
1308 | }, { | ||
1309 | .base = S3C64XX_GPN_BASE, | ||
1310 | .irq_base = IRQ_EINT(0), | ||
1311 | .config = &samsung_gpio_cfgs[5], | ||
1312 | .chip = { | ||
1313 | .base = S3C64XX_GPN(0), | ||
1314 | .ngpio = S3C64XX_GPIO_N_NR, | ||
1315 | .label = "GPN", | ||
1316 | .to_irq = samsung_gpiolib_to_irq, | ||
1317 | }, | ||
1318 | }, | ||
1319 | #endif | ||
1320 | }; | ||
1321 | |||
1322 | /* | ||
1323 | * S5P6440 GPIO bank summary: | ||
1324 | * | ||
1325 | * Bank GPIOs Style SlpCon ExtInt Group | ||
1326 | * A 6 4Bit Yes 1 | ||
1327 | * B 7 4Bit Yes 1 | ||
1328 | * C 8 4Bit Yes 2 | ||
1329 | * F 2 2Bit Yes 4 [1] | ||
1330 | * G 7 4Bit Yes 5 | ||
1331 | * H 10 4Bit[2] Yes 6 | ||
1332 | * I 16 2Bit Yes None | ||
1333 | * J 12 2Bit Yes None | ||
1334 | * N 16 2Bit No IRQ_EINT | ||
1335 | * P 8 2Bit Yes 8 | ||
1336 | * R 15 4Bit[2] Yes 8 | ||
1337 | */ | ||
1338 | |||
1339 | static struct samsung_gpio_chip s5p6440_gpios_4bit[] = { | ||
1340 | #ifdef CONFIG_CPU_S5P6440 | ||
1341 | { | ||
1342 | .chip = { | ||
1343 | .base = S5P6440_GPA(0), | ||
1344 | .ngpio = S5P6440_GPIO_A_NR, | ||
1345 | .label = "GPA", | ||
1346 | }, | ||
1347 | }, { | ||
1348 | .chip = { | ||
1349 | .base = S5P6440_GPB(0), | ||
1350 | .ngpio = S5P6440_GPIO_B_NR, | ||
1351 | .label = "GPB", | ||
1352 | }, | ||
1353 | }, { | ||
1354 | .chip = { | ||
1355 | .base = S5P6440_GPC(0), | ||
1356 | .ngpio = S5P6440_GPIO_C_NR, | ||
1357 | .label = "GPC", | ||
1358 | }, | ||
1359 | }, { | ||
1360 | .base = S5P64X0_GPG_BASE, | ||
1361 | .chip = { | ||
1362 | .base = S5P6440_GPG(0), | ||
1363 | .ngpio = S5P6440_GPIO_G_NR, | ||
1364 | .label = "GPG", | ||
1365 | }, | ||
1366 | }, | ||
1367 | #endif | ||
1368 | }; | ||
1369 | |||
1370 | static struct samsung_gpio_chip s5p6440_gpios_4bit2[] = { | ||
1371 | #ifdef CONFIG_CPU_S5P6440 | ||
1372 | { | ||
1373 | .base = S5P64X0_GPH_BASE + 0x4, | ||
1374 | .chip = { | ||
1375 | .base = S5P6440_GPH(0), | ||
1376 | .ngpio = S5P6440_GPIO_H_NR, | ||
1377 | .label = "GPH", | ||
1378 | }, | ||
1379 | }, | ||
1380 | #endif | ||
1381 | }; | ||
1382 | |||
1383 | static struct samsung_gpio_chip s5p6440_gpios_rbank[] = { | ||
1384 | #ifdef CONFIG_CPU_S5P6440 | ||
1385 | { | ||
1386 | .base = S5P64X0_GPR_BASE + 0x4, | ||
1387 | .config = &s5p64x0_gpio_cfg_rbank, | ||
1388 | .chip = { | ||
1389 | .base = S5P6440_GPR(0), | ||
1390 | .ngpio = S5P6440_GPIO_R_NR, | ||
1391 | .label = "GPR", | ||
1392 | }, | ||
1393 | }, | ||
1394 | #endif | ||
1395 | }; | ||
1396 | |||
1397 | static struct samsung_gpio_chip s5p6440_gpios_2bit[] = { | ||
1398 | #ifdef CONFIG_CPU_S5P6440 | ||
1399 | { | ||
1400 | .base = S5P64X0_GPF_BASE, | ||
1401 | .config = &samsung_gpio_cfgs[6], | ||
1402 | .chip = { | ||
1403 | .base = S5P6440_GPF(0), | ||
1404 | .ngpio = S5P6440_GPIO_F_NR, | ||
1405 | .label = "GPF", | ||
1406 | }, | ||
1407 | }, { | ||
1408 | .base = S5P64X0_GPI_BASE, | ||
1409 | .config = &samsung_gpio_cfgs[4], | ||
1410 | .chip = { | ||
1411 | .base = S5P6440_GPI(0), | ||
1412 | .ngpio = S5P6440_GPIO_I_NR, | ||
1413 | .label = "GPI", | ||
1414 | }, | ||
1415 | }, { | ||
1416 | .base = S5P64X0_GPJ_BASE, | ||
1417 | .config = &samsung_gpio_cfgs[4], | ||
1418 | .chip = { | ||
1419 | .base = S5P6440_GPJ(0), | ||
1420 | .ngpio = S5P6440_GPIO_J_NR, | ||
1421 | .label = "GPJ", | ||
1422 | }, | ||
1423 | }, { | ||
1424 | .base = S5P64X0_GPN_BASE, | ||
1425 | .config = &samsung_gpio_cfgs[5], | ||
1426 | .chip = { | ||
1427 | .base = S5P6440_GPN(0), | ||
1428 | .ngpio = S5P6440_GPIO_N_NR, | ||
1429 | .label = "GPN", | ||
1430 | }, | ||
1431 | }, { | ||
1432 | .base = S5P64X0_GPP_BASE, | ||
1433 | .config = &samsung_gpio_cfgs[6], | ||
1434 | .chip = { | ||
1435 | .base = S5P6440_GPP(0), | ||
1436 | .ngpio = S5P6440_GPIO_P_NR, | ||
1437 | .label = "GPP", | ||
1438 | }, | ||
1439 | }, | ||
1440 | #endif | ||
1441 | }; | ||
1442 | |||
1443 | /* | ||
1444 | * S5P6450 GPIO bank summary: | ||
1445 | * | ||
1446 | * Bank GPIOs Style SlpCon ExtInt Group | ||
1447 | * A 6 4Bit Yes 1 | ||
1448 | * B 7 4Bit Yes 1 | ||
1449 | * C 8 4Bit Yes 2 | ||
1450 | * D 8 4Bit Yes None | ||
1451 | * F 2 2Bit Yes None | ||
1452 | * G 14 4Bit[2] Yes 5 | ||
1453 | * H 10 4Bit[2] Yes 6 | ||
1454 | * I 16 2Bit Yes None | ||
1455 | * J 12 2Bit Yes None | ||
1456 | * K 5 4Bit Yes None | ||
1457 | * N 16 2Bit No IRQ_EINT | ||
1458 | * P 11 2Bit Yes 8 | ||
1459 | * Q 14 2Bit Yes None | ||
1460 | * R 15 4Bit[2] Yes None | ||
1461 | * S 8 2Bit Yes None | ||
1462 | * | ||
1463 | * [1] BANKF pins 14,15 do not form part of the external interrupt sources | ||
1464 | * [2] BANK has two control registers, GPxCON0 and GPxCON1 | ||
1465 | */ | ||
1466 | |||
1467 | static struct samsung_gpio_chip s5p6450_gpios_4bit[] = { | ||
1468 | #ifdef CONFIG_CPU_S5P6450 | ||
1469 | { | ||
1470 | .chip = { | ||
1471 | .base = S5P6450_GPA(0), | ||
1472 | .ngpio = S5P6450_GPIO_A_NR, | ||
1473 | .label = "GPA", | ||
1474 | }, | ||
1475 | }, { | ||
1476 | .chip = { | ||
1477 | .base = S5P6450_GPB(0), | ||
1478 | .ngpio = S5P6450_GPIO_B_NR, | ||
1479 | .label = "GPB", | ||
1480 | }, | ||
1481 | }, { | ||
1482 | .chip = { | ||
1483 | .base = S5P6450_GPC(0), | ||
1484 | .ngpio = S5P6450_GPIO_C_NR, | ||
1485 | .label = "GPC", | ||
1486 | }, | ||
1487 | }, { | ||
1488 | .chip = { | ||
1489 | .base = S5P6450_GPD(0), | ||
1490 | .ngpio = S5P6450_GPIO_D_NR, | ||
1491 | .label = "GPD", | ||
1492 | }, | ||
1493 | }, { | ||
1494 | .base = S5P6450_GPK_BASE, | ||
1495 | .chip = { | ||
1496 | .base = S5P6450_GPK(0), | ||
1497 | .ngpio = S5P6450_GPIO_K_NR, | ||
1498 | .label = "GPK", | ||
1499 | }, | ||
1500 | }, | ||
1501 | #endif | ||
1502 | }; | ||
1503 | |||
1504 | static struct samsung_gpio_chip s5p6450_gpios_4bit2[] = { | ||
1505 | #ifdef CONFIG_CPU_S5P6450 | ||
1506 | { | ||
1507 | .base = S5P64X0_GPG_BASE + 0x4, | ||
1508 | .chip = { | ||
1509 | .base = S5P6450_GPG(0), | ||
1510 | .ngpio = S5P6450_GPIO_G_NR, | ||
1511 | .label = "GPG", | ||
1512 | }, | ||
1513 | }, { | ||
1514 | .base = S5P64X0_GPH_BASE + 0x4, | ||
1515 | .chip = { | ||
1516 | .base = S5P6450_GPH(0), | ||
1517 | .ngpio = S5P6450_GPIO_H_NR, | ||
1518 | .label = "GPH", | ||
1519 | }, | ||
1520 | }, | ||
1521 | #endif | ||
1522 | }; | ||
1523 | |||
1524 | static struct samsung_gpio_chip s5p6450_gpios_rbank[] = { | ||
1525 | #ifdef CONFIG_CPU_S5P6450 | ||
1526 | { | ||
1527 | .base = S5P64X0_GPR_BASE + 0x4, | ||
1528 | .config = &s5p64x0_gpio_cfg_rbank, | ||
1529 | .chip = { | ||
1530 | .base = S5P6450_GPR(0), | ||
1531 | .ngpio = S5P6450_GPIO_R_NR, | ||
1532 | .label = "GPR", | ||
1533 | }, | ||
1534 | }, | ||
1535 | #endif | ||
1536 | }; | ||
1537 | |||
1538 | static struct samsung_gpio_chip s5p6450_gpios_2bit[] = { | ||
1539 | #ifdef CONFIG_CPU_S5P6450 | ||
1540 | { | ||
1541 | .base = S5P64X0_GPF_BASE, | ||
1542 | .config = &samsung_gpio_cfgs[6], | ||
1543 | .chip = { | ||
1544 | .base = S5P6450_GPF(0), | ||
1545 | .ngpio = S5P6450_GPIO_F_NR, | ||
1546 | .label = "GPF", | ||
1547 | }, | ||
1548 | }, { | ||
1549 | .base = S5P64X0_GPI_BASE, | ||
1550 | .config = &samsung_gpio_cfgs[4], | ||
1551 | .chip = { | ||
1552 | .base = S5P6450_GPI(0), | ||
1553 | .ngpio = S5P6450_GPIO_I_NR, | ||
1554 | .label = "GPI", | ||
1555 | }, | ||
1556 | }, { | ||
1557 | .base = S5P64X0_GPJ_BASE, | ||
1558 | .config = &samsung_gpio_cfgs[4], | ||
1559 | .chip = { | ||
1560 | .base = S5P6450_GPJ(0), | ||
1561 | .ngpio = S5P6450_GPIO_J_NR, | ||
1562 | .label = "GPJ", | ||
1563 | }, | ||
1564 | }, { | ||
1565 | .base = S5P64X0_GPN_BASE, | ||
1566 | .config = &samsung_gpio_cfgs[5], | ||
1567 | .chip = { | ||
1568 | .base = S5P6450_GPN(0), | ||
1569 | .ngpio = S5P6450_GPIO_N_NR, | ||
1570 | .label = "GPN", | ||
1571 | }, | ||
1572 | }, { | ||
1573 | .base = S5P64X0_GPP_BASE, | ||
1574 | .config = &samsung_gpio_cfgs[6], | ||
1575 | .chip = { | ||
1576 | .base = S5P6450_GPP(0), | ||
1577 | .ngpio = S5P6450_GPIO_P_NR, | ||
1578 | .label = "GPP", | ||
1579 | }, | ||
1580 | }, { | ||
1581 | .base = S5P6450_GPQ_BASE, | ||
1582 | .config = &samsung_gpio_cfgs[5], | ||
1583 | .chip = { | ||
1584 | .base = S5P6450_GPQ(0), | ||
1585 | .ngpio = S5P6450_GPIO_Q_NR, | ||
1586 | .label = "GPQ", | ||
1587 | }, | ||
1588 | }, { | ||
1589 | .base = S5P6450_GPS_BASE, | ||
1590 | .config = &samsung_gpio_cfgs[6], | ||
1591 | .chip = { | ||
1592 | .base = S5P6450_GPS(0), | ||
1593 | .ngpio = S5P6450_GPIO_S_NR, | ||
1594 | .label = "GPS", | ||
1595 | }, | ||
1596 | }, | ||
1597 | #endif | ||
1598 | }; | ||
1599 | |||
1600 | /* | ||
1601 | * S5PC100 GPIO bank summary: | ||
1602 | * | ||
1603 | * Bank GPIOs Style INT Type | ||
1604 | * A0 8 4Bit GPIO_INT0 | ||
1605 | * A1 5 4Bit GPIO_INT1 | ||
1606 | * B 8 4Bit GPIO_INT2 | ||
1607 | * C 5 4Bit GPIO_INT3 | ||
1608 | * D 7 4Bit GPIO_INT4 | ||
1609 | * E0 8 4Bit GPIO_INT5 | ||
1610 | * E1 6 4Bit GPIO_INT6 | ||
1611 | * F0 8 4Bit GPIO_INT7 | ||
1612 | * F1 8 4Bit GPIO_INT8 | ||
1613 | * F2 8 4Bit GPIO_INT9 | ||
1614 | * F3 4 4Bit GPIO_INT10 | ||
1615 | * G0 8 4Bit GPIO_INT11 | ||
1616 | * G1 3 4Bit GPIO_INT12 | ||
1617 | * G2 7 4Bit GPIO_INT13 | ||
1618 | * G3 7 4Bit GPIO_INT14 | ||
1619 | * H0 8 4Bit WKUP_INT | ||
1620 | * H1 8 4Bit WKUP_INT | ||
1621 | * H2 8 4Bit WKUP_INT | ||
1622 | * H3 8 4Bit WKUP_INT | ||
1623 | * I 8 4Bit GPIO_INT15 | ||
1624 | * J0 8 4Bit GPIO_INT16 | ||
1625 | * J1 5 4Bit GPIO_INT17 | ||
1626 | * J2 8 4Bit GPIO_INT18 | ||
1627 | * J3 8 4Bit GPIO_INT19 | ||
1628 | * J4 4 4Bit GPIO_INT20 | ||
1629 | * K0 8 4Bit None | ||
1630 | * K1 6 4Bit None | ||
1631 | * K2 8 4Bit None | ||
1632 | * K3 8 4Bit None | ||
1633 | * L0 8 4Bit None | ||
1634 | * L1 8 4Bit None | ||
1635 | * L2 8 4Bit None | ||
1636 | * L3 8 4Bit None | ||
1637 | */ | ||
1638 | |||
1639 | static struct samsung_gpio_chip s5pc100_gpios_4bit[] = { | ||
1640 | #ifdef CONFIG_CPU_S5PC100 | ||
1641 | { | ||
1642 | .chip = { | ||
1643 | .base = S5PC100_GPA0(0), | ||
1644 | .ngpio = S5PC100_GPIO_A0_NR, | ||
1645 | .label = "GPA0", | ||
1646 | }, | ||
1647 | }, { | ||
1648 | .chip = { | ||
1649 | .base = S5PC100_GPA1(0), | ||
1650 | .ngpio = S5PC100_GPIO_A1_NR, | ||
1651 | .label = "GPA1", | ||
1652 | }, | ||
1653 | }, { | ||
1654 | .chip = { | ||
1655 | .base = S5PC100_GPB(0), | ||
1656 | .ngpio = S5PC100_GPIO_B_NR, | ||
1657 | .label = "GPB", | ||
1658 | }, | ||
1659 | }, { | ||
1660 | .chip = { | ||
1661 | .base = S5PC100_GPC(0), | ||
1662 | .ngpio = S5PC100_GPIO_C_NR, | ||
1663 | .label = "GPC", | ||
1664 | }, | ||
1665 | }, { | ||
1666 | .chip = { | ||
1667 | .base = S5PC100_GPD(0), | ||
1668 | .ngpio = S5PC100_GPIO_D_NR, | ||
1669 | .label = "GPD", | ||
1670 | }, | ||
1671 | }, { | ||
1672 | .chip = { | ||
1673 | .base = S5PC100_GPE0(0), | ||
1674 | .ngpio = S5PC100_GPIO_E0_NR, | ||
1675 | .label = "GPE0", | ||
1676 | }, | ||
1677 | }, { | ||
1678 | .chip = { | ||
1679 | .base = S5PC100_GPE1(0), | ||
1680 | .ngpio = S5PC100_GPIO_E1_NR, | ||
1681 | .label = "GPE1", | ||
1682 | }, | ||
1683 | }, { | ||
1684 | .chip = { | ||
1685 | .base = S5PC100_GPF0(0), | ||
1686 | .ngpio = S5PC100_GPIO_F0_NR, | ||
1687 | .label = "GPF0", | ||
1688 | }, | ||
1689 | }, { | ||
1690 | .chip = { | ||
1691 | .base = S5PC100_GPF1(0), | ||
1692 | .ngpio = S5PC100_GPIO_F1_NR, | ||
1693 | .label = "GPF1", | ||
1694 | }, | ||
1695 | }, { | ||
1696 | .chip = { | ||
1697 | .base = S5PC100_GPF2(0), | ||
1698 | .ngpio = S5PC100_GPIO_F2_NR, | ||
1699 | .label = "GPF2", | ||
1700 | }, | ||
1701 | }, { | ||
1702 | .chip = { | ||
1703 | .base = S5PC100_GPF3(0), | ||
1704 | .ngpio = S5PC100_GPIO_F3_NR, | ||
1705 | .label = "GPF3", | ||
1706 | }, | ||
1707 | }, { | ||
1708 | .chip = { | ||
1709 | .base = S5PC100_GPG0(0), | ||
1710 | .ngpio = S5PC100_GPIO_G0_NR, | ||
1711 | .label = "GPG0", | ||
1712 | }, | ||
1713 | }, { | ||
1714 | .chip = { | ||
1715 | .base = S5PC100_GPG1(0), | ||
1716 | .ngpio = S5PC100_GPIO_G1_NR, | ||
1717 | .label = "GPG1", | ||
1718 | }, | ||
1719 | }, { | ||
1720 | .chip = { | ||
1721 | .base = S5PC100_GPG2(0), | ||
1722 | .ngpio = S5PC100_GPIO_G2_NR, | ||
1723 | .label = "GPG2", | ||
1724 | }, | ||
1725 | }, { | ||
1726 | .chip = { | ||
1727 | .base = S5PC100_GPG3(0), | ||
1728 | .ngpio = S5PC100_GPIO_G3_NR, | ||
1729 | .label = "GPG3", | ||
1730 | }, | ||
1731 | }, { | ||
1732 | .chip = { | ||
1733 | .base = S5PC100_GPI(0), | ||
1734 | .ngpio = S5PC100_GPIO_I_NR, | ||
1735 | .label = "GPI", | ||
1736 | }, | ||
1737 | }, { | ||
1738 | .chip = { | ||
1739 | .base = S5PC100_GPJ0(0), | ||
1740 | .ngpio = S5PC100_GPIO_J0_NR, | ||
1741 | .label = "GPJ0", | ||
1742 | }, | ||
1743 | }, { | ||
1744 | .chip = { | ||
1745 | .base = S5PC100_GPJ1(0), | ||
1746 | .ngpio = S5PC100_GPIO_J1_NR, | ||
1747 | .label = "GPJ1", | ||
1748 | }, | ||
1749 | }, { | ||
1750 | .chip = { | ||
1751 | .base = S5PC100_GPJ2(0), | ||
1752 | .ngpio = S5PC100_GPIO_J2_NR, | ||
1753 | .label = "GPJ2", | ||
1754 | }, | ||
1755 | }, { | ||
1756 | .chip = { | ||
1757 | .base = S5PC100_GPJ3(0), | ||
1758 | .ngpio = S5PC100_GPIO_J3_NR, | ||
1759 | .label = "GPJ3", | ||
1760 | }, | ||
1761 | }, { | ||
1762 | .chip = { | ||
1763 | .base = S5PC100_GPJ4(0), | ||
1764 | .ngpio = S5PC100_GPIO_J4_NR, | ||
1765 | .label = "GPJ4", | ||
1766 | }, | ||
1767 | }, { | ||
1768 | .chip = { | ||
1769 | .base = S5PC100_GPK0(0), | ||
1770 | .ngpio = S5PC100_GPIO_K0_NR, | ||
1771 | .label = "GPK0", | ||
1772 | }, | ||
1773 | }, { | ||
1774 | .chip = { | ||
1775 | .base = S5PC100_GPK1(0), | ||
1776 | .ngpio = S5PC100_GPIO_K1_NR, | ||
1777 | .label = "GPK1", | ||
1778 | }, | ||
1779 | }, { | ||
1780 | .chip = { | ||
1781 | .base = S5PC100_GPK2(0), | ||
1782 | .ngpio = S5PC100_GPIO_K2_NR, | ||
1783 | .label = "GPK2", | ||
1784 | }, | ||
1785 | }, { | ||
1786 | .chip = { | ||
1787 | .base = S5PC100_GPK3(0), | ||
1788 | .ngpio = S5PC100_GPIO_K3_NR, | ||
1789 | .label = "GPK3", | ||
1790 | }, | ||
1791 | }, { | ||
1792 | .chip = { | ||
1793 | .base = S5PC100_GPL0(0), | ||
1794 | .ngpio = S5PC100_GPIO_L0_NR, | ||
1795 | .label = "GPL0", | ||
1796 | }, | ||
1797 | }, { | ||
1798 | .chip = { | ||
1799 | .base = S5PC100_GPL1(0), | ||
1800 | .ngpio = S5PC100_GPIO_L1_NR, | ||
1801 | .label = "GPL1", | ||
1802 | }, | ||
1803 | }, { | ||
1804 | .chip = { | ||
1805 | .base = S5PC100_GPL2(0), | ||
1806 | .ngpio = S5PC100_GPIO_L2_NR, | ||
1807 | .label = "GPL2", | ||
1808 | }, | ||
1809 | }, { | ||
1810 | .chip = { | ||
1811 | .base = S5PC100_GPL3(0), | ||
1812 | .ngpio = S5PC100_GPIO_L3_NR, | ||
1813 | .label = "GPL3", | ||
1814 | }, | ||
1815 | }, { | ||
1816 | .chip = { | ||
1817 | .base = S5PC100_GPL4(0), | ||
1818 | .ngpio = S5PC100_GPIO_L4_NR, | ||
1819 | .label = "GPL4", | ||
1820 | }, | ||
1821 | }, { | ||
1822 | .base = (S5P_VA_GPIO + 0xC00), | ||
1823 | .irq_base = IRQ_EINT(0), | ||
1824 | .chip = { | ||
1825 | .base = S5PC100_GPH0(0), | ||
1826 | .ngpio = S5PC100_GPIO_H0_NR, | ||
1827 | .label = "GPH0", | ||
1828 | .to_irq = samsung_gpiolib_to_irq, | ||
1829 | }, | ||
1830 | }, { | ||
1831 | .base = (S5P_VA_GPIO + 0xC20), | ||
1832 | .irq_base = IRQ_EINT(8), | ||
1833 | .chip = { | ||
1834 | .base = S5PC100_GPH1(0), | ||
1835 | .ngpio = S5PC100_GPIO_H1_NR, | ||
1836 | .label = "GPH1", | ||
1837 | .to_irq = samsung_gpiolib_to_irq, | ||
1838 | }, | ||
1839 | }, { | ||
1840 | .base = (S5P_VA_GPIO + 0xC40), | ||
1841 | .irq_base = IRQ_EINT(16), | ||
1842 | .chip = { | ||
1843 | .base = S5PC100_GPH2(0), | ||
1844 | .ngpio = S5PC100_GPIO_H2_NR, | ||
1845 | .label = "GPH2", | ||
1846 | .to_irq = samsung_gpiolib_to_irq, | ||
1847 | }, | ||
1848 | }, { | ||
1849 | .base = (S5P_VA_GPIO + 0xC60), | ||
1850 | .irq_base = IRQ_EINT(24), | ||
1851 | .chip = { | ||
1852 | .base = S5PC100_GPH3(0), | ||
1853 | .ngpio = S5PC100_GPIO_H3_NR, | ||
1854 | .label = "GPH3", | ||
1855 | .to_irq = samsung_gpiolib_to_irq, | ||
1856 | }, | ||
1857 | }, | ||
1858 | #endif | ||
1859 | }; | ||
1860 | |||
1861 | /* | ||
1862 | * Followings are the gpio banks in S5PV210/S5PC110 | ||
1863 | * | ||
1864 | * The 'config' member when left to NULL, is initialized to the default | ||
1865 | * structure samsung_gpio_cfgs[3] in the init function below. | ||
1866 | * | ||
1867 | * The 'base' member is also initialized in the init function below. | ||
1868 | * Note: The initialization of 'base' member of samsung_gpio_chip structure | ||
1869 | * uses the above macro and depends on the banks being listed in order here. | ||
1870 | */ | ||
1871 | |||
1872 | static struct samsung_gpio_chip s5pv210_gpios_4bit[] = { | ||
1873 | #ifdef CONFIG_CPU_S5PV210 | ||
1874 | { | ||
1875 | .chip = { | ||
1876 | .base = S5PV210_GPA0(0), | ||
1877 | .ngpio = S5PV210_GPIO_A0_NR, | ||
1878 | .label = "GPA0", | ||
1879 | }, | ||
1880 | }, { | ||
1881 | .chip = { | ||
1882 | .base = S5PV210_GPA1(0), | ||
1883 | .ngpio = S5PV210_GPIO_A1_NR, | ||
1884 | .label = "GPA1", | ||
1885 | }, | ||
1886 | }, { | ||
1887 | .chip = { | ||
1888 | .base = S5PV210_GPB(0), | ||
1889 | .ngpio = S5PV210_GPIO_B_NR, | ||
1890 | .label = "GPB", | ||
1891 | }, | ||
1892 | }, { | ||
1893 | .chip = { | ||
1894 | .base = S5PV210_GPC0(0), | ||
1895 | .ngpio = S5PV210_GPIO_C0_NR, | ||
1896 | .label = "GPC0", | ||
1897 | }, | ||
1898 | }, { | ||
1899 | .chip = { | ||
1900 | .base = S5PV210_GPC1(0), | ||
1901 | .ngpio = S5PV210_GPIO_C1_NR, | ||
1902 | .label = "GPC1", | ||
1903 | }, | ||
1904 | }, { | ||
1905 | .chip = { | ||
1906 | .base = S5PV210_GPD0(0), | ||
1907 | .ngpio = S5PV210_GPIO_D0_NR, | ||
1908 | .label = "GPD0", | ||
1909 | }, | ||
1910 | }, { | ||
1911 | .chip = { | ||
1912 | .base = S5PV210_GPD1(0), | ||
1913 | .ngpio = S5PV210_GPIO_D1_NR, | ||
1914 | .label = "GPD1", | ||
1915 | }, | ||
1916 | }, { | ||
1917 | .chip = { | ||
1918 | .base = S5PV210_GPE0(0), | ||
1919 | .ngpio = S5PV210_GPIO_E0_NR, | ||
1920 | .label = "GPE0", | ||
1921 | }, | ||
1922 | }, { | ||
1923 | .chip = { | ||
1924 | .base = S5PV210_GPE1(0), | ||
1925 | .ngpio = S5PV210_GPIO_E1_NR, | ||
1926 | .label = "GPE1", | ||
1927 | }, | ||
1928 | }, { | ||
1929 | .chip = { | ||
1930 | .base = S5PV210_GPF0(0), | ||
1931 | .ngpio = S5PV210_GPIO_F0_NR, | ||
1932 | .label = "GPF0", | ||
1933 | }, | ||
1934 | }, { | ||
1935 | .chip = { | ||
1936 | .base = S5PV210_GPF1(0), | ||
1937 | .ngpio = S5PV210_GPIO_F1_NR, | ||
1938 | .label = "GPF1", | ||
1939 | }, | ||
1940 | }, { | ||
1941 | .chip = { | ||
1942 | .base = S5PV210_GPF2(0), | ||
1943 | .ngpio = S5PV210_GPIO_F2_NR, | ||
1944 | .label = "GPF2", | ||
1945 | }, | ||
1946 | }, { | ||
1947 | .chip = { | ||
1948 | .base = S5PV210_GPF3(0), | ||
1949 | .ngpio = S5PV210_GPIO_F3_NR, | ||
1950 | .label = "GPF3", | ||
1951 | }, | ||
1952 | }, { | ||
1953 | .chip = { | ||
1954 | .base = S5PV210_GPG0(0), | ||
1955 | .ngpio = S5PV210_GPIO_G0_NR, | ||
1956 | .label = "GPG0", | ||
1957 | }, | ||
1958 | }, { | ||
1959 | .chip = { | ||
1960 | .base = S5PV210_GPG1(0), | ||
1961 | .ngpio = S5PV210_GPIO_G1_NR, | ||
1962 | .label = "GPG1", | ||
1963 | }, | ||
1964 | }, { | ||
1965 | .chip = { | ||
1966 | .base = S5PV210_GPG2(0), | ||
1967 | .ngpio = S5PV210_GPIO_G2_NR, | ||
1968 | .label = "GPG2", | ||
1969 | }, | ||
1970 | }, { | ||
1971 | .chip = { | ||
1972 | .base = S5PV210_GPG3(0), | ||
1973 | .ngpio = S5PV210_GPIO_G3_NR, | ||
1974 | .label = "GPG3", | ||
1975 | }, | ||
1976 | }, { | ||
1977 | .chip = { | ||
1978 | .base = S5PV210_GPI(0), | ||
1979 | .ngpio = S5PV210_GPIO_I_NR, | ||
1980 | .label = "GPI", | ||
1981 | }, | ||
1982 | }, { | ||
1983 | .chip = { | ||
1984 | .base = S5PV210_GPJ0(0), | ||
1985 | .ngpio = S5PV210_GPIO_J0_NR, | ||
1986 | .label = "GPJ0", | ||
1987 | }, | ||
1988 | }, { | ||
1989 | .chip = { | ||
1990 | .base = S5PV210_GPJ1(0), | ||
1991 | .ngpio = S5PV210_GPIO_J1_NR, | ||
1992 | .label = "GPJ1", | ||
1993 | }, | ||
1994 | }, { | ||
1995 | .chip = { | ||
1996 | .base = S5PV210_GPJ2(0), | ||
1997 | .ngpio = S5PV210_GPIO_J2_NR, | ||
1998 | .label = "GPJ2", | ||
1999 | }, | ||
2000 | }, { | ||
2001 | .chip = { | ||
2002 | .base = S5PV210_GPJ3(0), | ||
2003 | .ngpio = S5PV210_GPIO_J3_NR, | ||
2004 | .label = "GPJ3", | ||
2005 | }, | ||
2006 | }, { | ||
2007 | .chip = { | ||
2008 | .base = S5PV210_GPJ4(0), | ||
2009 | .ngpio = S5PV210_GPIO_J4_NR, | ||
2010 | .label = "GPJ4", | ||
2011 | }, | ||
2012 | }, { | ||
2013 | .chip = { | ||
2014 | .base = S5PV210_MP01(0), | ||
2015 | .ngpio = S5PV210_GPIO_MP01_NR, | ||
2016 | .label = "MP01", | ||
2017 | }, | ||
2018 | }, { | ||
2019 | .chip = { | ||
2020 | .base = S5PV210_MP02(0), | ||
2021 | .ngpio = S5PV210_GPIO_MP02_NR, | ||
2022 | .label = "MP02", | ||
2023 | }, | ||
2024 | }, { | ||
2025 | .chip = { | ||
2026 | .base = S5PV210_MP03(0), | ||
2027 | .ngpio = S5PV210_GPIO_MP03_NR, | ||
2028 | .label = "MP03", | ||
2029 | }, | ||
2030 | }, { | ||
2031 | .chip = { | ||
2032 | .base = S5PV210_MP04(0), | ||
2033 | .ngpio = S5PV210_GPIO_MP04_NR, | ||
2034 | .label = "MP04", | ||
2035 | }, | ||
2036 | }, { | ||
2037 | .chip = { | ||
2038 | .base = S5PV210_MP05(0), | ||
2039 | .ngpio = S5PV210_GPIO_MP05_NR, | ||
2040 | .label = "MP05", | ||
2041 | }, | ||
2042 | }, { | ||
2043 | .base = (S5P_VA_GPIO + 0xC00), | ||
2044 | .irq_base = IRQ_EINT(0), | ||
2045 | .chip = { | ||
2046 | .base = S5PV210_GPH0(0), | ||
2047 | .ngpio = S5PV210_GPIO_H0_NR, | ||
2048 | .label = "GPH0", | ||
2049 | .to_irq = samsung_gpiolib_to_irq, | ||
2050 | }, | ||
2051 | }, { | ||
2052 | .base = (S5P_VA_GPIO + 0xC20), | ||
2053 | .irq_base = IRQ_EINT(8), | ||
2054 | .chip = { | ||
2055 | .base = S5PV210_GPH1(0), | ||
2056 | .ngpio = S5PV210_GPIO_H1_NR, | ||
2057 | .label = "GPH1", | ||
2058 | .to_irq = samsung_gpiolib_to_irq, | ||
2059 | }, | ||
2060 | }, { | ||
2061 | .base = (S5P_VA_GPIO + 0xC40), | ||
2062 | .irq_base = IRQ_EINT(16), | ||
2063 | .chip = { | ||
2064 | .base = S5PV210_GPH2(0), | ||
2065 | .ngpio = S5PV210_GPIO_H2_NR, | ||
2066 | .label = "GPH2", | ||
2067 | .to_irq = samsung_gpiolib_to_irq, | ||
2068 | }, | ||
2069 | }, { | ||
2070 | .base = (S5P_VA_GPIO + 0xC60), | ||
2071 | .irq_base = IRQ_EINT(24), | ||
2072 | .chip = { | ||
2073 | .base = S5PV210_GPH3(0), | ||
2074 | .ngpio = S5PV210_GPIO_H3_NR, | ||
2075 | .label = "GPH3", | ||
2076 | .to_irq = samsung_gpiolib_to_irq, | ||
2077 | }, | ||
2078 | }, | ||
2079 | #endif | ||
2080 | }; | ||
2081 | |||
2082 | /* | ||
2083 | * Followings are the gpio banks in EXYNOS4210 | ||
2084 | * | ||
2085 | * The 'config' member when left to NULL, is initialized to the default | ||
2086 | * structure samsung_gpio_cfgs[3] in the init function below. | ||
2087 | * | ||
2088 | * The 'base' member is also initialized in the init function below. | ||
2089 | * Note: The initialization of 'base' member of samsung_gpio_chip structure | ||
2090 | * uses the above macro and depends on the banks being listed in order here. | ||
2091 | */ | ||
2092 | |||
2093 | static struct samsung_gpio_chip exynos4_gpios_1[] = { | ||
2094 | #ifdef CONFIG_ARCH_EXYNOS4 | ||
2095 | { | ||
2096 | .chip = { | ||
2097 | .base = EXYNOS4_GPA0(0), | ||
2098 | .ngpio = EXYNOS4_GPIO_A0_NR, | ||
2099 | .label = "GPA0", | ||
2100 | }, | ||
2101 | }, { | ||
2102 | .chip = { | ||
2103 | .base = EXYNOS4_GPA1(0), | ||
2104 | .ngpio = EXYNOS4_GPIO_A1_NR, | ||
2105 | .label = "GPA1", | ||
2106 | }, | ||
2107 | }, { | ||
2108 | .chip = { | ||
2109 | .base = EXYNOS4_GPB(0), | ||
2110 | .ngpio = EXYNOS4_GPIO_B_NR, | ||
2111 | .label = "GPB", | ||
2112 | }, | ||
2113 | }, { | ||
2114 | .chip = { | ||
2115 | .base = EXYNOS4_GPC0(0), | ||
2116 | .ngpio = EXYNOS4_GPIO_C0_NR, | ||
2117 | .label = "GPC0", | ||
2118 | }, | ||
2119 | }, { | ||
2120 | .chip = { | ||
2121 | .base = EXYNOS4_GPC1(0), | ||
2122 | .ngpio = EXYNOS4_GPIO_C1_NR, | ||
2123 | .label = "GPC1", | ||
2124 | }, | ||
2125 | }, { | ||
2126 | .chip = { | ||
2127 | .base = EXYNOS4_GPD0(0), | ||
2128 | .ngpio = EXYNOS4_GPIO_D0_NR, | ||
2129 | .label = "GPD0", | ||
2130 | }, | ||
2131 | }, { | ||
2132 | .chip = { | ||
2133 | .base = EXYNOS4_GPD1(0), | ||
2134 | .ngpio = EXYNOS4_GPIO_D1_NR, | ||
2135 | .label = "GPD1", | ||
2136 | }, | ||
2137 | }, { | ||
2138 | .chip = { | ||
2139 | .base = EXYNOS4_GPE0(0), | ||
2140 | .ngpio = EXYNOS4_GPIO_E0_NR, | ||
2141 | .label = "GPE0", | ||
2142 | }, | ||
2143 | }, { | ||
2144 | .chip = { | ||
2145 | .base = EXYNOS4_GPE1(0), | ||
2146 | .ngpio = EXYNOS4_GPIO_E1_NR, | ||
2147 | .label = "GPE1", | ||
2148 | }, | ||
2149 | }, { | ||
2150 | .chip = { | ||
2151 | .base = EXYNOS4_GPE2(0), | ||
2152 | .ngpio = EXYNOS4_GPIO_E2_NR, | ||
2153 | .label = "GPE2", | ||
2154 | }, | ||
2155 | }, { | ||
2156 | .chip = { | ||
2157 | .base = EXYNOS4_GPE3(0), | ||
2158 | .ngpio = EXYNOS4_GPIO_E3_NR, | ||
2159 | .label = "GPE3", | ||
2160 | }, | ||
2161 | }, { | ||
2162 | .chip = { | ||
2163 | .base = EXYNOS4_GPE4(0), | ||
2164 | .ngpio = EXYNOS4_GPIO_E4_NR, | ||
2165 | .label = "GPE4", | ||
2166 | }, | ||
2167 | }, { | ||
2168 | .chip = { | ||
2169 | .base = EXYNOS4_GPF0(0), | ||
2170 | .ngpio = EXYNOS4_GPIO_F0_NR, | ||
2171 | .label = "GPF0", | ||
2172 | }, | ||
2173 | }, { | ||
2174 | .chip = { | ||
2175 | .base = EXYNOS4_GPF1(0), | ||
2176 | .ngpio = EXYNOS4_GPIO_F1_NR, | ||
2177 | .label = "GPF1", | ||
2178 | }, | ||
2179 | }, { | ||
2180 | .chip = { | ||
2181 | .base = EXYNOS4_GPF2(0), | ||
2182 | .ngpio = EXYNOS4_GPIO_F2_NR, | ||
2183 | .label = "GPF2", | ||
2184 | }, | ||
2185 | }, { | ||
2186 | .chip = { | ||
2187 | .base = EXYNOS4_GPF3(0), | ||
2188 | .ngpio = EXYNOS4_GPIO_F3_NR, | ||
2189 | .label = "GPF3", | ||
2190 | }, | ||
2191 | }, | ||
2192 | #endif | ||
2193 | }; | ||
2194 | |||
2195 | static struct samsung_gpio_chip exynos4_gpios_2[] = { | ||
2196 | #ifdef CONFIG_ARCH_EXYNOS4 | ||
2197 | { | ||
2198 | .chip = { | ||
2199 | .base = EXYNOS4_GPJ0(0), | ||
2200 | .ngpio = EXYNOS4_GPIO_J0_NR, | ||
2201 | .label = "GPJ0", | ||
2202 | }, | ||
2203 | }, { | ||
2204 | .chip = { | ||
2205 | .base = EXYNOS4_GPJ1(0), | ||
2206 | .ngpio = EXYNOS4_GPIO_J1_NR, | ||
2207 | .label = "GPJ1", | ||
2208 | }, | ||
2209 | }, { | ||
2210 | .chip = { | ||
2211 | .base = EXYNOS4_GPK0(0), | ||
2212 | .ngpio = EXYNOS4_GPIO_K0_NR, | ||
2213 | .label = "GPK0", | ||
2214 | }, | ||
2215 | }, { | ||
2216 | .chip = { | ||
2217 | .base = EXYNOS4_GPK1(0), | ||
2218 | .ngpio = EXYNOS4_GPIO_K1_NR, | ||
2219 | .label = "GPK1", | ||
2220 | }, | ||
2221 | }, { | ||
2222 | .chip = { | ||
2223 | .base = EXYNOS4_GPK2(0), | ||
2224 | .ngpio = EXYNOS4_GPIO_K2_NR, | ||
2225 | .label = "GPK2", | ||
2226 | }, | ||
2227 | }, { | ||
2228 | .chip = { | ||
2229 | .base = EXYNOS4_GPK3(0), | ||
2230 | .ngpio = EXYNOS4_GPIO_K3_NR, | ||
2231 | .label = "GPK3", | ||
2232 | }, | ||
2233 | }, { | ||
2234 | .chip = { | ||
2235 | .base = EXYNOS4_GPL0(0), | ||
2236 | .ngpio = EXYNOS4_GPIO_L0_NR, | ||
2237 | .label = "GPL0", | ||
2238 | }, | ||
2239 | }, { | ||
2240 | .chip = { | ||
2241 | .base = EXYNOS4_GPL1(0), | ||
2242 | .ngpio = EXYNOS4_GPIO_L1_NR, | ||
2243 | .label = "GPL1", | ||
2244 | }, | ||
2245 | }, { | ||
2246 | .chip = { | ||
2247 | .base = EXYNOS4_GPL2(0), | ||
2248 | .ngpio = EXYNOS4_GPIO_L2_NR, | ||
2249 | .label = "GPL2", | ||
2250 | }, | ||
2251 | }, { | ||
2252 | .config = &samsung_gpio_cfgs[0], | ||
2253 | .chip = { | ||
2254 | .base = EXYNOS4_GPY0(0), | ||
2255 | .ngpio = EXYNOS4_GPIO_Y0_NR, | ||
2256 | .label = "GPY0", | ||
2257 | }, | ||
2258 | }, { | ||
2259 | .config = &samsung_gpio_cfgs[0], | ||
2260 | .chip = { | ||
2261 | .base = EXYNOS4_GPY1(0), | ||
2262 | .ngpio = EXYNOS4_GPIO_Y1_NR, | ||
2263 | .label = "GPY1", | ||
2264 | }, | ||
2265 | }, { | ||
2266 | .config = &samsung_gpio_cfgs[0], | ||
2267 | .chip = { | ||
2268 | .base = EXYNOS4_GPY2(0), | ||
2269 | .ngpio = EXYNOS4_GPIO_Y2_NR, | ||
2270 | .label = "GPY2", | ||
2271 | }, | ||
2272 | }, { | ||
2273 | .config = &samsung_gpio_cfgs[0], | ||
2274 | .chip = { | ||
2275 | .base = EXYNOS4_GPY3(0), | ||
2276 | .ngpio = EXYNOS4_GPIO_Y3_NR, | ||
2277 | .label = "GPY3", | ||
2278 | }, | ||
2279 | }, { | ||
2280 | .config = &samsung_gpio_cfgs[0], | ||
2281 | .chip = { | ||
2282 | .base = EXYNOS4_GPY4(0), | ||
2283 | .ngpio = EXYNOS4_GPIO_Y4_NR, | ||
2284 | .label = "GPY4", | ||
2285 | }, | ||
2286 | }, { | ||
2287 | .config = &samsung_gpio_cfgs[0], | ||
2288 | .chip = { | ||
2289 | .base = EXYNOS4_GPY5(0), | ||
2290 | .ngpio = EXYNOS4_GPIO_Y5_NR, | ||
2291 | .label = "GPY5", | ||
2292 | }, | ||
2293 | }, { | ||
2294 | .config = &samsung_gpio_cfgs[0], | ||
2295 | .chip = { | ||
2296 | .base = EXYNOS4_GPY6(0), | ||
2297 | .ngpio = EXYNOS4_GPIO_Y6_NR, | ||
2298 | .label = "GPY6", | ||
2299 | }, | ||
2300 | }, { | ||
2301 | .base = (S5P_VA_GPIO2 + 0xC00), | ||
2302 | .config = &samsung_gpio_cfgs[3], | ||
2303 | .irq_base = IRQ_EINT(0), | ||
2304 | .chip = { | ||
2305 | .base = EXYNOS4_GPX0(0), | ||
2306 | .ngpio = EXYNOS4_GPIO_X0_NR, | ||
2307 | .label = "GPX0", | ||
2308 | .to_irq = samsung_gpiolib_to_irq, | ||
2309 | }, | ||
2310 | }, { | ||
2311 | .base = (S5P_VA_GPIO2 + 0xC20), | ||
2312 | .config = &samsung_gpio_cfgs[3], | ||
2313 | .irq_base = IRQ_EINT(8), | ||
2314 | .chip = { | ||
2315 | .base = EXYNOS4_GPX1(0), | ||
2316 | .ngpio = EXYNOS4_GPIO_X1_NR, | ||
2317 | .label = "GPX1", | ||
2318 | .to_irq = samsung_gpiolib_to_irq, | ||
2319 | }, | ||
2320 | }, { | ||
2321 | .base = (S5P_VA_GPIO2 + 0xC40), | ||
2322 | .config = &samsung_gpio_cfgs[3], | ||
2323 | .irq_base = IRQ_EINT(16), | ||
2324 | .chip = { | ||
2325 | .base = EXYNOS4_GPX2(0), | ||
2326 | .ngpio = EXYNOS4_GPIO_X2_NR, | ||
2327 | .label = "GPX2", | ||
2328 | .to_irq = samsung_gpiolib_to_irq, | ||
2329 | }, | ||
2330 | }, { | ||
2331 | .base = (S5P_VA_GPIO2 + 0xC60), | ||
2332 | .config = &samsung_gpio_cfgs[3], | ||
2333 | .irq_base = IRQ_EINT(24), | ||
2334 | .chip = { | ||
2335 | .base = EXYNOS4_GPX3(0), | ||
2336 | .ngpio = EXYNOS4_GPIO_X3_NR, | ||
2337 | .label = "GPX3", | ||
2338 | .to_irq = samsung_gpiolib_to_irq, | ||
2339 | }, | ||
2340 | }, | ||
2341 | #endif | ||
2342 | }; | ||
2343 | |||
2344 | static struct samsung_gpio_chip exynos4_gpios_3[] = { | ||
2345 | #ifdef CONFIG_ARCH_EXYNOS4 | ||
2346 | { | ||
2347 | .chip = { | ||
2348 | .base = EXYNOS4_GPZ(0), | ||
2349 | .ngpio = EXYNOS4_GPIO_Z_NR, | ||
2350 | .label = "GPZ", | ||
2351 | }, | ||
2352 | }, | ||
2353 | #endif | ||
2354 | }; | ||
2355 | |||
2356 | /* TODO: cleanup soc_is_* */ | ||
2357 | static __init int samsung_gpiolib_init(void) | ||
2358 | { | ||
2359 | struct samsung_gpio_chip *chip; | ||
2360 | int i, nr_chips; | ||
2361 | int group = 0; | ||
2362 | |||
2363 | samsung_gpiolib_set_cfg(samsung_gpio_cfgs, ARRAY_SIZE(samsung_gpio_cfgs)); | ||
2364 | |||
2365 | if (soc_is_s3c24xx()) { | ||
2366 | s3c24xx_gpiolib_add_chips(s3c24xx_gpios, | ||
2367 | ARRAY_SIZE(s3c24xx_gpios), S3C24XX_VA_GPIO); | ||
2368 | } else if (soc_is_s3c64xx()) { | ||
2369 | samsung_gpiolib_add_2bit_chips(s3c64xx_gpios_2bit, | ||
2370 | ARRAY_SIZE(s3c64xx_gpios_2bit), | ||
2371 | S3C64XX_VA_GPIO + 0xE0, 0x20); | ||
2372 | samsung_gpiolib_add_4bit_chips(s3c64xx_gpios_4bit, | ||
2373 | ARRAY_SIZE(s3c64xx_gpios_4bit), | ||
2374 | S3C64XX_VA_GPIO); | ||
2375 | samsung_gpiolib_add_4bit2_chips(s3c64xx_gpios_4bit2, | ||
2376 | ARRAY_SIZE(s3c64xx_gpios_4bit2)); | ||
2377 | } else if (soc_is_s5p6440()) { | ||
2378 | samsung_gpiolib_add_2bit_chips(s5p6440_gpios_2bit, | ||
2379 | ARRAY_SIZE(s5p6440_gpios_2bit), NULL, 0x0); | ||
2380 | samsung_gpiolib_add_4bit_chips(s5p6440_gpios_4bit, | ||
2381 | ARRAY_SIZE(s5p6440_gpios_4bit), S5P_VA_GPIO); | ||
2382 | samsung_gpiolib_add_4bit2_chips(s5p6440_gpios_4bit2, | ||
2383 | ARRAY_SIZE(s5p6440_gpios_4bit2)); | ||
2384 | s5p64x0_gpiolib_add_rbank(s5p6440_gpios_rbank, | ||
2385 | ARRAY_SIZE(s5p6440_gpios_rbank)); | ||
2386 | } else if (soc_is_s5p6450()) { | ||
2387 | samsung_gpiolib_add_2bit_chips(s5p6450_gpios_2bit, | ||
2388 | ARRAY_SIZE(s5p6450_gpios_2bit), NULL, 0x0); | ||
2389 | samsung_gpiolib_add_4bit_chips(s5p6450_gpios_4bit, | ||
2390 | ARRAY_SIZE(s5p6450_gpios_4bit), S5P_VA_GPIO); | ||
2391 | samsung_gpiolib_add_4bit2_chips(s5p6450_gpios_4bit2, | ||
2392 | ARRAY_SIZE(s5p6450_gpios_4bit2)); | ||
2393 | s5p64x0_gpiolib_add_rbank(s5p6450_gpios_rbank, | ||
2394 | ARRAY_SIZE(s5p6450_gpios_rbank)); | ||
2395 | } else if (soc_is_s5pc100()) { | ||
2396 | group = 0; | ||
2397 | chip = s5pc100_gpios_4bit; | ||
2398 | nr_chips = ARRAY_SIZE(s5pc100_gpios_4bit); | ||
2399 | |||
2400 | for (i = 0; i < nr_chips; i++, chip++) { | ||
2401 | if (!chip->config) { | ||
2402 | chip->config = &samsung_gpio_cfgs[3]; | ||
2403 | chip->group = group++; | ||
2404 | } | ||
2405 | } | ||
2406 | samsung_gpiolib_add_4bit_chips(s5pc100_gpios_4bit, nr_chips, S5P_VA_GPIO); | ||
2407 | #if defined(CONFIG_CPU_S5PC100) && defined(CONFIG_S5P_GPIO_INT) | ||
2408 | s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR); | ||
2409 | #endif | ||
2410 | } else if (soc_is_s5pv210()) { | ||
2411 | group = 0; | ||
2412 | chip = s5pv210_gpios_4bit; | ||
2413 | nr_chips = ARRAY_SIZE(s5pv210_gpios_4bit); | ||
2414 | |||
2415 | for (i = 0; i < nr_chips; i++, chip++) { | ||
2416 | if (!chip->config) { | ||
2417 | chip->config = &samsung_gpio_cfgs[3]; | ||
2418 | chip->group = group++; | ||
2419 | } | ||
2420 | } | ||
2421 | samsung_gpiolib_add_4bit_chips(s5pv210_gpios_4bit, nr_chips, S5P_VA_GPIO); | ||
2422 | #if defined(CONFIG_CPU_S5PV210) && defined(CONFIG_S5P_GPIO_INT) | ||
2423 | s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR); | ||
2424 | #endif | ||
2425 | } else if (soc_is_exynos4210()) { | ||
2426 | group = 0; | ||
2427 | |||
2428 | /* gpio part1 */ | ||
2429 | chip = exynos4_gpios_1; | ||
2430 | nr_chips = ARRAY_SIZE(exynos4_gpios_1); | ||
2431 | |||
2432 | for (i = 0; i < nr_chips; i++, chip++) { | ||
2433 | if (!chip->config) { | ||
2434 | chip->config = &exynos4_gpio_cfg; | ||
2435 | chip->group = group++; | ||
2436 | } | ||
2437 | } | ||
2438 | samsung_gpiolib_add_4bit_chips(exynos4_gpios_1, nr_chips, S5P_VA_GPIO1); | ||
2439 | |||
2440 | /* gpio part2 */ | ||
2441 | chip = exynos4_gpios_2; | ||
2442 | nr_chips = ARRAY_SIZE(exynos4_gpios_2); | ||
2443 | |||
2444 | for (i = 0; i < nr_chips; i++, chip++) { | ||
2445 | if (!chip->config) { | ||
2446 | chip->config = &exynos4_gpio_cfg; | ||
2447 | chip->group = group++; | ||
2448 | } | ||
2449 | } | ||
2450 | samsung_gpiolib_add_4bit_chips(exynos4_gpios_2, nr_chips, S5P_VA_GPIO2); | ||
2451 | |||
2452 | /* gpio part3 */ | ||
2453 | chip = exynos4_gpios_3; | ||
2454 | nr_chips = ARRAY_SIZE(exynos4_gpios_3); | ||
2455 | |||
2456 | for (i = 0; i < nr_chips; i++, chip++) { | ||
2457 | if (!chip->config) { | ||
2458 | chip->config = &exynos4_gpio_cfg; | ||
2459 | chip->group = group++; | ||
2460 | } | ||
2461 | } | ||
2462 | samsung_gpiolib_add_4bit_chips(exynos4_gpios_3, nr_chips, S5P_VA_GPIO3); | ||
2463 | |||
2464 | #if defined(CONFIG_CPU_EXYNOS4210) && defined(CONFIG_S5P_GPIO_INT) | ||
2465 | s5p_register_gpioint_bank(IRQ_GPIO_XA, 0, IRQ_GPIO1_NR_GROUPS); | ||
2466 | s5p_register_gpioint_bank(IRQ_GPIO_XB, IRQ_GPIO1_NR_GROUPS, IRQ_GPIO2_NR_GROUPS); | ||
2467 | #endif | ||
2468 | } | ||
2469 | |||
2470 | return 0; | ||
2471 | } | ||
2472 | core_initcall(samsung_gpiolib_init); | ||
2473 | |||
2474 | int s3c_gpio_cfgpin(unsigned int pin, unsigned int config) | ||
2475 | { | ||
2476 | struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin); | ||
2477 | unsigned long flags; | ||
2478 | int offset; | ||
2479 | int ret; | ||
2480 | |||
2481 | if (!chip) | ||
2482 | return -EINVAL; | ||
2483 | |||
2484 | offset = pin - chip->chip.base; | ||
2485 | |||
2486 | samsung_gpio_lock(chip, flags); | ||
2487 | ret = samsung_gpio_do_setcfg(chip, offset, config); | ||
2488 | samsung_gpio_unlock(chip, flags); | ||
2489 | |||
2490 | return ret; | ||
2491 | } | ||
2492 | EXPORT_SYMBOL(s3c_gpio_cfgpin); | ||
2493 | |||
2494 | int s3c_gpio_cfgpin_range(unsigned int start, unsigned int nr, | ||
2495 | unsigned int cfg) | ||
2496 | { | ||
2497 | int ret; | ||
2498 | |||
2499 | for (; nr > 0; nr--, start++) { | ||
2500 | ret = s3c_gpio_cfgpin(start, cfg); | ||
2501 | if (ret != 0) | ||
2502 | return ret; | ||
2503 | } | ||
2504 | |||
2505 | return 0; | ||
2506 | } | ||
2507 | EXPORT_SYMBOL_GPL(s3c_gpio_cfgpin_range); | ||
2508 | |||
2509 | int s3c_gpio_cfgall_range(unsigned int start, unsigned int nr, | ||
2510 | unsigned int cfg, samsung_gpio_pull_t pull) | ||
2511 | { | ||
2512 | int ret; | ||
2513 | |||
2514 | for (; nr > 0; nr--, start++) { | ||
2515 | s3c_gpio_setpull(start, pull); | ||
2516 | ret = s3c_gpio_cfgpin(start, cfg); | ||
2517 | if (ret != 0) | ||
2518 | return ret; | ||
2519 | } | ||
2520 | |||
2521 | return 0; | ||
2522 | } | ||
2523 | EXPORT_SYMBOL_GPL(s3c_gpio_cfgall_range); | ||
2524 | |||
2525 | unsigned s3c_gpio_getcfg(unsigned int pin) | ||
2526 | { | ||
2527 | struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin); | ||
2528 | unsigned long flags; | ||
2529 | unsigned ret = 0; | ||
2530 | int offset; | ||
2531 | |||
2532 | if (chip) { | ||
2533 | offset = pin - chip->chip.base; | ||
2534 | |||
2535 | samsung_gpio_lock(chip, flags); | ||
2536 | ret = samsung_gpio_do_getcfg(chip, offset); | ||
2537 | samsung_gpio_unlock(chip, flags); | ||
2538 | } | ||
2539 | |||
2540 | return ret; | ||
2541 | } | ||
2542 | EXPORT_SYMBOL(s3c_gpio_getcfg); | ||
2543 | |||
2544 | int s3c_gpio_setpull(unsigned int pin, samsung_gpio_pull_t pull) | ||
2545 | { | ||
2546 | struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin); | ||
2547 | unsigned long flags; | ||
2548 | int offset, ret; | ||
2549 | |||
2550 | if (!chip) | ||
2551 | return -EINVAL; | ||
2552 | |||
2553 | offset = pin - chip->chip.base; | ||
2554 | |||
2555 | samsung_gpio_lock(chip, flags); | ||
2556 | ret = samsung_gpio_do_setpull(chip, offset, pull); | ||
2557 | samsung_gpio_unlock(chip, flags); | ||
2558 | |||
2559 | return ret; | ||
2560 | } | ||
2561 | EXPORT_SYMBOL(s3c_gpio_setpull); | ||
2562 | |||
2563 | samsung_gpio_pull_t s3c_gpio_getpull(unsigned int pin) | ||
2564 | { | ||
2565 | struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin); | ||
2566 | unsigned long flags; | ||
2567 | int offset; | ||
2568 | u32 pup = 0; | ||
2569 | |||
2570 | if (chip) { | ||
2571 | offset = pin - chip->chip.base; | ||
2572 | |||
2573 | samsung_gpio_lock(chip, flags); | ||
2574 | pup = samsung_gpio_do_getpull(chip, offset); | ||
2575 | samsung_gpio_unlock(chip, flags); | ||
2576 | } | ||
2577 | |||
2578 | return (__force samsung_gpio_pull_t)pup; | ||
2579 | } | ||
2580 | EXPORT_SYMBOL(s3c_gpio_getpull); | ||
2581 | |||
2582 | /* gpiolib wrappers until these are totally eliminated */ | ||
2583 | |||
2584 | void s3c2410_gpio_pullup(unsigned int pin, unsigned int to) | ||
2585 | { | ||
2586 | int ret; | ||
2587 | |||
2588 | WARN_ON(to); /* should be none of these left */ | ||
2589 | |||
2590 | if (!to) { | ||
2591 | /* if pull is enabled, try first with up, and if that | ||
2592 | * fails, try using down */ | ||
2593 | |||
2594 | ret = s3c_gpio_setpull(pin, S3C_GPIO_PULL_UP); | ||
2595 | if (ret) | ||
2596 | s3c_gpio_setpull(pin, S3C_GPIO_PULL_DOWN); | ||
2597 | } else { | ||
2598 | s3c_gpio_setpull(pin, S3C_GPIO_PULL_NONE); | ||
2599 | } | ||
2600 | } | ||
2601 | EXPORT_SYMBOL(s3c2410_gpio_pullup); | ||
2602 | |||
2603 | void s3c2410_gpio_setpin(unsigned int pin, unsigned int to) | ||
2604 | { | ||
2605 | /* do this via gpiolib until all users removed */ | ||
2606 | |||
2607 | gpio_request(pin, "temporary"); | ||
2608 | gpio_set_value(pin, to); | ||
2609 | gpio_free(pin); | ||
2610 | } | ||
2611 | EXPORT_SYMBOL(s3c2410_gpio_setpin); | ||
2612 | |||
2613 | unsigned int s3c2410_gpio_getpin(unsigned int pin) | ||
2614 | { | ||
2615 | struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin); | ||
2616 | unsigned long offs = pin - chip->chip.base; | ||
2617 | |||
2618 | return __raw_readl(chip->base + 0x04) & (1 << offs); | ||
2619 | } | ||
2620 | EXPORT_SYMBOL(s3c2410_gpio_getpin); | ||
2621 | |||
2622 | #ifdef CONFIG_S5P_GPIO_DRVSTR | ||
2623 | s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin) | ||
2624 | { | ||
2625 | struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin); | ||
2626 | unsigned int off; | ||
2627 | void __iomem *reg; | ||
2628 | int shift; | ||
2629 | u32 drvstr; | ||
2630 | |||
2631 | if (!chip) | ||
2632 | return -EINVAL; | ||
2633 | |||
2634 | off = pin - chip->chip.base; | ||
2635 | shift = off * 2; | ||
2636 | reg = chip->base + 0x0C; | ||
2637 | |||
2638 | drvstr = __raw_readl(reg); | ||
2639 | drvstr = drvstr >> shift; | ||
2640 | drvstr &= 0x3; | ||
2641 | |||
2642 | return (__force s5p_gpio_drvstr_t)drvstr; | ||
2643 | } | ||
2644 | EXPORT_SYMBOL(s5p_gpio_get_drvstr); | ||
2645 | |||
2646 | int s5p_gpio_set_drvstr(unsigned int pin, s5p_gpio_drvstr_t drvstr) | ||
2647 | { | ||
2648 | struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin); | ||
2649 | unsigned int off; | ||
2650 | void __iomem *reg; | ||
2651 | int shift; | ||
2652 | u32 tmp; | ||
2653 | |||
2654 | if (!chip) | ||
2655 | return -EINVAL; | ||
2656 | |||
2657 | off = pin - chip->chip.base; | ||
2658 | shift = off * 2; | ||
2659 | reg = chip->base + 0x0C; | ||
2660 | |||
2661 | tmp = __raw_readl(reg); | ||
2662 | tmp &= ~(0x3 << shift); | ||
2663 | tmp |= drvstr << shift; | ||
2664 | |||
2665 | __raw_writel(tmp, reg); | ||
2666 | |||
2667 | return 0; | ||
2668 | } | ||
2669 | EXPORT_SYMBOL(s5p_gpio_set_drvstr); | ||
2670 | #endif /* CONFIG_S5P_GPIO_DRVSTR */ | ||
2671 | |||
2672 | #ifdef CONFIG_PLAT_S3C24XX | ||
2673 | unsigned int s3c2410_modify_misccr(unsigned int clear, unsigned int change) | ||
2674 | { | ||
2675 | unsigned long flags; | ||
2676 | unsigned long misccr; | ||
2677 | |||
2678 | local_irq_save(flags); | ||
2679 | misccr = __raw_readl(S3C24XX_MISCCR); | ||
2680 | misccr &= ~clear; | ||
2681 | misccr ^= change; | ||
2682 | __raw_writel(misccr, S3C24XX_MISCCR); | ||
2683 | local_irq_restore(flags); | ||
2684 | |||
2685 | return misccr; | ||
2686 | } | ||
2687 | EXPORT_SYMBOL(s3c2410_modify_misccr); | ||
2688 | #endif | ||