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authorTarun Kanti DebBarma <tarun.kanti@ti.com>2011-09-13 05:42:05 -0400
committerTarun Kanti DebBarma <tarun.kanti@ti.com>2012-02-06 03:43:42 -0500
commitab985f0f7c2c0ef90b7c832f0c04f470dda0593d (patch)
tree6a65b11d802d12787147d6cfab49758101f5389f /drivers/gpio/gpio-omap.c
parent5e571f38f6a44ef541fac0821631509d787ef0cd (diff)
gpio/omap: cleanup omap_gpio_mod_init function
With register offsets now defined for respective OMAP versions we can get rid of cpu_class_* checks. This function now has common initialization code for all OMAP versions. Initialization specific to OMAP16xx has been moved within omap16xx_gpio_init(). Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com> Signed-off-by: Charulatha V <charu@ti.com> Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Reviewed-by: Kevin Hilman <khilman@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
Diffstat (limited to 'drivers/gpio/gpio-omap.c')
-rw-r--r--drivers/gpio/gpio-omap.c77
1 files changed, 23 insertions, 54 deletions
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index f39d9e4967b2..a948351ad6c4 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -610,7 +610,6 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
610 if (!(isr & 1)) 610 if (!(isr & 1))
611 continue; 611 continue;
612 612
613#ifdef CONFIG_ARCH_OMAP1
614 /* 613 /*
615 * Some chips can't respond to both rising and falling 614 * Some chips can't respond to both rising and falling
616 * at the same time. If this irq was requested with 615 * at the same time. If this irq was requested with
@@ -620,7 +619,6 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
620 */ 619 */
621 if (bank->toggle_mask & (1 << gpio_index)) 620 if (bank->toggle_mask & (1 << gpio_index))
622 _toggle_gpio_edge_triggering(bank, gpio_index); 621 _toggle_gpio_edge_triggering(bank, gpio_index);
623#endif
624 622
625 generic_handle_irq(gpio_irq); 623 generic_handle_irq(gpio_irq);
626 } 624 }
@@ -898,62 +896,30 @@ static void __init omap_gpio_show_rev(struct gpio_bank *bank)
898 */ 896 */
899static struct lock_class_key gpio_lock_class; 897static struct lock_class_key gpio_lock_class;
900 898
901/* TODO: Cleanup cpu_is_* checks */
902static void omap_gpio_mod_init(struct gpio_bank *bank) 899static void omap_gpio_mod_init(struct gpio_bank *bank)
903{ 900{
904 if (cpu_class_is_omap2()) { 901 void __iomem *base = bank->base;
905 if (cpu_is_omap44xx()) { 902 u32 l = 0xffffffff;
906 __raw_writel(0xffffffff, bank->base +
907 OMAP4_GPIO_IRQSTATUSCLR0);
908 __raw_writel(0x00000000, bank->base +
909 OMAP4_GPIO_DEBOUNCENABLE);
910 /* Initialize interface clk ungated, module enabled */
911 __raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
912 } else if (cpu_is_omap34xx()) {
913 __raw_writel(0x00000000, bank->base +
914 OMAP24XX_GPIO_IRQENABLE1);
915 __raw_writel(0xffffffff, bank->base +
916 OMAP24XX_GPIO_IRQSTATUS1);
917 __raw_writel(0x00000000, bank->base +
918 OMAP24XX_GPIO_DEBOUNCE_EN);
919
920 /* Initialize interface clk ungated, module enabled */
921 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
922 }
923 } else if (cpu_class_is_omap1()) {
924 if (bank_is_mpuio(bank)) {
925 __raw_writew(0xffff, bank->base +
926 OMAP_MPUIO_GPIO_MASKIT / bank->stride);
927 mpuio_init(bank);
928 }
929 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
930 __raw_writew(0xffff, bank->base
931 + OMAP1510_GPIO_INT_MASK);
932 __raw_writew(0x0000, bank->base
933 + OMAP1510_GPIO_INT_STATUS);
934 }
935 if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
936 __raw_writew(0x0000, bank->base
937 + OMAP1610_GPIO_IRQENABLE1);
938 __raw_writew(0xffff, bank->base
939 + OMAP1610_GPIO_IRQSTATUS1);
940 __raw_writew(0x0014, bank->base
941 + OMAP1610_GPIO_SYSCONFIG);
942 903
943 /* 904 if (bank->width == 16)
944 * Enable system clock for GPIO module. 905 l = 0xffff;
945 * The CAM_CLK_CTRL *is* really the right place. 906
946 */ 907 if (bank_is_mpuio(bank)) {
947 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, 908 __raw_writel(l, bank->base + bank->regs->irqenable);
948 ULPD_CAM_CLK_CTRL); 909 return;
949 }
950 if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) {
951 __raw_writel(0xffffffff, bank->base
952 + OMAP7XX_GPIO_INT_MASK);
953 __raw_writel(0x00000000, bank->base
954 + OMAP7XX_GPIO_INT_STATUS);
955 }
956 } 910 }
911
912 _gpio_rmw(base, bank->regs->irqenable, l, bank->regs->irqenable_inv);
913 _gpio_rmw(base, bank->regs->irqstatus, l,
914 bank->regs->irqenable_inv == false);
915 _gpio_rmw(base, bank->regs->irqenable, l, bank->regs->debounce_en != 0);
916 _gpio_rmw(base, bank->regs->irqenable, l, bank->regs->ctrl != 0);
917 if (bank->regs->debounce_en)
918 _gpio_rmw(base, bank->regs->debounce_en, 0, 1);
919
920 /* Initialize interface clk ungated, module enabled */
921 if (bank->regs->ctrl)
922 _gpio_rmw(base, bank->regs->ctrl, 0, 1);
957} 923}
958 924
959static __init void 925static __init void
@@ -1104,6 +1070,9 @@ static int __devinit omap_gpio_probe(struct platform_device *pdev)
1104 pm_runtime_enable(bank->dev); 1070 pm_runtime_enable(bank->dev);
1105 pm_runtime_get_sync(bank->dev); 1071 pm_runtime_get_sync(bank->dev);
1106 1072
1073 if (bank_is_mpuio(bank))
1074 mpuio_init(bank);
1075
1107 omap_gpio_mod_init(bank); 1076 omap_gpio_mod_init(bank);
1108 omap_gpio_chip_init(bank); 1077 omap_gpio_chip_init(bank);
1109 omap_gpio_show_rev(bank); 1078 omap_gpio_show_rev(bank);