diff options
author | Kevin Hilman <khilman@ti.com> | 2011-04-21 12:53:06 -0400 |
---|---|---|
committer | Kevin Hilman <khilman@ti.com> | 2011-06-16 14:13:51 -0400 |
commit | 28f3b5a073b6dbafbb78cae65b22ea90547d7a87 (patch) | |
tree | 7e4f1ce8067c39d50c84081a26dec08143edff8c /drivers/gpio/gpio-omap.c | |
parent | eef4bec7bf2fa9953f6b8f371d5914d014f45d40 (diff) |
gpio/omap: conslidate enable/disable of GPIO IRQs, remove ifdefs
Cleanup GPIO IRQ enable/disable handling by removing SoC-specific
Also split enable/disable IRQ into separate functions for better
readability and also facilitate potentially moving to generic irq_chip
in the future.
Signed-off-by: Kevin Hilman <khilman@ti.com>
Diffstat (limited to 'drivers/gpio/gpio-omap.c')
-rw-r--r-- | drivers/gpio/gpio-omap.c | 129 |
1 files changed, 30 insertions, 99 deletions
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c index bdf0132b70ec..6afca28a8c67 100644 --- a/drivers/gpio/gpio-omap.c +++ b/drivers/gpio/gpio-omap.c | |||
@@ -502,129 +502,60 @@ static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio) | |||
502 | static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank) | 502 | static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank) |
503 | { | 503 | { |
504 | void __iomem *reg = bank->base; | 504 | void __iomem *reg = bank->base; |
505 | int inv = 0; | ||
506 | u32 l; | 505 | u32 l; |
507 | u32 mask = (1 << bank->width) - 1; | 506 | u32 mask = (1 << bank->width) - 1; |
508 | 507 | ||
509 | switch (bank->method) { | 508 | reg += bank->regs->irqenable; |
510 | #ifdef CONFIG_ARCH_OMAP1 | ||
511 | case METHOD_MPUIO: | ||
512 | reg += OMAP_MPUIO_GPIO_MASKIT / bank->stride; | ||
513 | inv = 1; | ||
514 | break; | ||
515 | #endif | ||
516 | #ifdef CONFIG_ARCH_OMAP15XX | ||
517 | case METHOD_GPIO_1510: | ||
518 | reg += OMAP1510_GPIO_INT_MASK; | ||
519 | inv = 1; | ||
520 | break; | ||
521 | #endif | ||
522 | #ifdef CONFIG_ARCH_OMAP16XX | ||
523 | case METHOD_GPIO_1610: | ||
524 | reg += OMAP1610_GPIO_IRQENABLE1; | ||
525 | break; | ||
526 | #endif | ||
527 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) | ||
528 | case METHOD_GPIO_7XX: | ||
529 | reg += OMAP7XX_GPIO_INT_MASK; | ||
530 | inv = 1; | ||
531 | break; | ||
532 | #endif | ||
533 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) | ||
534 | case METHOD_GPIO_24XX: | ||
535 | reg += OMAP24XX_GPIO_IRQENABLE1; | ||
536 | break; | ||
537 | #endif | ||
538 | #if defined(CONFIG_ARCH_OMAP4) | ||
539 | case METHOD_GPIO_44XX: | ||
540 | reg += OMAP4_GPIO_IRQSTATUSSET0; | ||
541 | break; | ||
542 | #endif | ||
543 | default: | ||
544 | WARN_ON(1); | ||
545 | return 0; | ||
546 | } | ||
547 | |||
548 | l = __raw_readl(reg); | 509 | l = __raw_readl(reg); |
549 | if (inv) | 510 | if (bank->regs->irqenable_inv) |
550 | l = ~l; | 511 | l = ~l; |
551 | l &= mask; | 512 | l &= mask; |
552 | return l; | 513 | return l; |
553 | } | 514 | } |
554 | 515 | ||
555 | static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable) | 516 | static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) |
556 | { | 517 | { |
557 | void __iomem *reg = bank->base; | 518 | void __iomem *reg = bank->base; |
558 | u32 l; | 519 | u32 l; |
559 | 520 | ||
560 | switch (bank->method) { | 521 | if (bank->regs->set_irqenable) { |
561 | #ifdef CONFIG_ARCH_OMAP1 | 522 | reg += bank->regs->set_irqenable; |
562 | case METHOD_MPUIO: | 523 | l = gpio_mask; |
563 | reg += OMAP_MPUIO_GPIO_MASKIT / bank->stride; | 524 | } else { |
564 | l = __raw_readl(reg); | 525 | reg += bank->regs->irqenable; |
565 | if (enable) | ||
566 | l &= ~(gpio_mask); | ||
567 | else | ||
568 | l |= gpio_mask; | ||
569 | break; | ||
570 | #endif | ||
571 | #ifdef CONFIG_ARCH_OMAP15XX | ||
572 | case METHOD_GPIO_1510: | ||
573 | reg += OMAP1510_GPIO_INT_MASK; | ||
574 | l = __raw_readl(reg); | 526 | l = __raw_readl(reg); |
575 | if (enable) | 527 | if (bank->regs->irqenable_inv) |
576 | l &= ~(gpio_mask); | 528 | l &= ~gpio_mask; |
577 | else | 529 | else |
578 | l |= gpio_mask; | 530 | l |= gpio_mask; |
579 | break; | 531 | } |
580 | #endif | 532 | |
581 | #ifdef CONFIG_ARCH_OMAP16XX | 533 | __raw_writel(l, reg); |
582 | case METHOD_GPIO_1610: | 534 | } |
583 | if (enable) | 535 | |
584 | reg += OMAP1610_GPIO_SET_IRQENABLE1; | 536 | static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) |
585 | else | 537 | { |
586 | reg += OMAP1610_GPIO_CLEAR_IRQENABLE1; | 538 | void __iomem *reg = bank->base; |
539 | u32 l; | ||
540 | |||
541 | if (bank->regs->clr_irqenable) { | ||
542 | reg += bank->regs->clr_irqenable; | ||
587 | l = gpio_mask; | 543 | l = gpio_mask; |
588 | break; | 544 | } else { |
589 | #endif | 545 | reg += bank->regs->irqenable; |
590 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) | ||
591 | case METHOD_GPIO_7XX: | ||
592 | reg += OMAP7XX_GPIO_INT_MASK; | ||
593 | l = __raw_readl(reg); | 546 | l = __raw_readl(reg); |
594 | if (enable) | 547 | if (bank->regs->irqenable_inv) |
595 | l &= ~(gpio_mask); | ||
596 | else | ||
597 | l |= gpio_mask; | 548 | l |= gpio_mask; |
598 | break; | ||
599 | #endif | ||
600 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) | ||
601 | case METHOD_GPIO_24XX: | ||
602 | if (enable) | ||
603 | reg += OMAP24XX_GPIO_SETIRQENABLE1; | ||
604 | else | ||
605 | reg += OMAP24XX_GPIO_CLEARIRQENABLE1; | ||
606 | l = gpio_mask; | ||
607 | break; | ||
608 | #endif | ||
609 | #ifdef CONFIG_ARCH_OMAP4 | ||
610 | case METHOD_GPIO_44XX: | ||
611 | if (enable) | ||
612 | reg += OMAP4_GPIO_IRQSTATUSSET0; | ||
613 | else | 549 | else |
614 | reg += OMAP4_GPIO_IRQSTATUSCLR0; | 550 | l &= ~gpio_mask; |
615 | l = gpio_mask; | ||
616 | break; | ||
617 | #endif | ||
618 | default: | ||
619 | WARN_ON(1); | ||
620 | return; | ||
621 | } | 551 | } |
552 | |||
622 | __raw_writel(l, reg); | 553 | __raw_writel(l, reg); |
623 | } | 554 | } |
624 | 555 | ||
625 | static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable) | 556 | static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable) |
626 | { | 557 | { |
627 | _enable_gpio_irqbank(bank, GPIO_BIT(bank, gpio), enable); | 558 | _enable_gpio_irqbank(bank, GPIO_BIT(bank, gpio)); |
628 | } | 559 | } |
629 | 560 | ||
630 | /* | 561 | /* |
@@ -831,9 +762,9 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) | |||
831 | /* clear edge sensitive interrupts before handler(s) are | 762 | /* clear edge sensitive interrupts before handler(s) are |
832 | called so that we don't miss any interrupt occurred while | 763 | called so that we don't miss any interrupt occurred while |
833 | executing them */ | 764 | executing them */ |
834 | _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0); | 765 | _disable_gpio_irqbank(bank, isr_saved & ~level_mask); |
835 | _clear_gpio_irqbank(bank, isr_saved & ~level_mask); | 766 | _clear_gpio_irqbank(bank, isr_saved & ~level_mask); |
836 | _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1); | 767 | _enable_gpio_irqbank(bank, isr_saved & ~level_mask); |
837 | 768 | ||
838 | /* if there is only edge sensitive GPIO pin interrupts | 769 | /* if there is only edge sensitive GPIO pin interrupts |
839 | configured, we could unmask GPIO bank interrupt immediately */ | 770 | configured, we could unmask GPIO bank interrupt immediately */ |