Merge branch 'mpi-master' into wip-k-fmlpwip-k-fmlp

Conflicts:
	litmus/sched_cedf.c

1 files changed, 108 insertions, 64 deletions

diff --git a/drivers/gpio/cs5535-gpio.c b/drivers/gpio/cs5535-gpio.c
index e23c06893d19..6e16cba56ad2 100644
--- a/drivers/gpio/cs5535-gpio.c
+++ b/drivers/gpio/cs5535-gpio.c
@@ -11,13 +11,13 @@
 #include <linux/kernel.h>
 #include <linux/spinlock.h>
 #include <linux/module.h>
-#include <linux/pci.h>
+#include <linux/platform_device.h>
 #include <linux/gpio.h>
 #include <linux/io.h>
 #include <linux/cs5535.h>
+#include <asm/msr.h>
 
 #define DRV_NAME "cs5535-gpio"
-#define GPIO_BAR 1
 
 /*
  * Some GPIO pins
@@ -46,7 +46,7 @@ static struct cs5535_gpio_chip {
         struct gpio_chip chip;
         resource_size_t base;
 
-        struct pci_dev *pdev;
+        struct platform_device *pdev;
         spinlock_t lock;
 } cs5535_gpio_chip;
 
@@ -56,6 +56,29 @@ static struct cs5535_gpio_chip {
  * registers, see include/linux/cs5535.h.
  */
 
+static void errata_outl(struct cs5535_gpio_chip *chip, u32 val,
+                unsigned int reg)
+{
+        unsigned long addr = chip->base + 0x80 + reg;
+
+        /*
+         * According to the CS5536 errata (#36), after suspend
+         * a write to the high bank GPIO register will clear all
+         * non-selected bits; the recommended workaround is a
+         * read-modify-write operation.
+         *
+         * Don't apply this errata to the edge status GPIOs, as writing
+         * to their lower bits will clear them.
+         */
+        if (reg != GPIO_POSITIVE_EDGE_STS && reg != GPIO_NEGATIVE_EDGE_STS) {
+                if (val & 0xffff)
+                        val |= (inl(addr) & 0xffff); /* ignore the high bits */
+                else
+                        val |= (inl(addr) ^ (val >> 16));
+        }
+        outl(val, addr);
+}
+
 static void __cs5535_gpio_set(struct cs5535_gpio_chip *chip, unsigned offset,
                 unsigned int reg)
 {
@@ -64,7 +87,7 @@ static void __cs5535_gpio_set(struct cs5535_gpio_chip *chip, unsigned offset,
                 outl(1 << offset, chip->base + reg);
         else
                 /* high bank register */
-                outl(1 << (offset - 16), chip->base + 0x80 + reg);
+                errata_outl(chip, 1 << (offset - 16), reg);
 }
 
 void cs5535_gpio_set(unsigned offset, unsigned int reg)
@@ -86,7 +109,7 @@ static void __cs5535_gpio_clear(struct cs5535_gpio_chip *chip, unsigned offset,
                 outl(1 << (offset + 16), chip->base + reg);
         else
                 /* high bank register */
-                outl(1 << offset, chip->base + 0x80 + reg);
+                errata_outl(chip, 1 << offset, reg);
 }
 
 void cs5535_gpio_clear(unsigned offset, unsigned int reg)
@@ -121,6 +144,57 @@ int cs5535_gpio_isset(unsigned offset, unsigned int reg)
 }
 EXPORT_SYMBOL_GPL(cs5535_gpio_isset);
 
+int cs5535_gpio_set_irq(unsigned group, unsigned irq)
+{
+        uint32_t lo, hi;
+
+        if (group > 7 || irq > 15)
+                return -EINVAL;
+
+        rdmsr(MSR_PIC_ZSEL_HIGH, lo, hi);
+
+        lo &= ~(0xF << (group * 4));
+        lo |= (irq & 0xF) << (group * 4);
+
+        wrmsr(MSR_PIC_ZSEL_HIGH, lo, hi);
+        return 0;
+}
+EXPORT_SYMBOL_GPL(cs5535_gpio_set_irq);
+
+void cs5535_gpio_setup_event(unsigned offset, int pair, int pme)
+{
+        struct cs5535_gpio_chip *chip = &cs5535_gpio_chip;
+        uint32_t shift = (offset % 8) * 4;
+        unsigned long flags;
+        uint32_t val;
+
+        if (offset >= 24)
+                offset = GPIO_MAP_W;
+        else if (offset >= 16)
+                offset = GPIO_MAP_Z;
+        else if (offset >= 8)
+                offset = GPIO_MAP_Y;
+        else
+                offset = GPIO_MAP_X;
+
+        spin_lock_irqsave(&chip->lock, flags);
+        val = inl(chip->base + offset);
+
+        /* Clear whatever was there before */
+        val &= ~(0xF << shift);
+
+        /* Set the new value */
+        val |= ((pair & 7) << shift);
+
+        /* Set the PME bit if this is a PME event */
+        if (pme)
+                val |= (1 << (shift + 3));
+
+        outl(val, chip->base + offset);
+        spin_unlock_irqrestore(&chip->lock, flags);
+}
+EXPORT_SYMBOL_GPL(cs5535_gpio_setup_event);
+
 /*
  * Generic gpio_chip API support.
  */
@@ -226,10 +300,10 @@ static struct cs5535_gpio_chip cs5535_gpio_chip = {
         },
 };
 
-static int __init cs5535_gpio_probe(struct pci_dev *pdev,
-                const struct pci_device_id *pci_id)
+static int __devinit cs5535_gpio_probe(struct platform_device *pdev)
 {
-        int err;
+        struct resource *res;
+        int err = -EIO;
         ulong mask_orig = mask;
 
         /* There are two ways to get the GPIO base address; one is by
@@ -239,25 +313,23 @@ static int __init cs5535_gpio_probe(struct pci_dev *pdev,
          * it turns out to be unreliable in the face of crappy BIOSes, we
          * can always go back to using MSRs.. */
 
-        err = pci_enable_device_io(pdev);
-        if (err) {
-                dev_err(&pdev->dev, "can't enable device IO\n");
+        res = platform_get_resource(pdev, IORESOURCE_IO, 0);
+        if (!res) {
+                dev_err(&pdev->dev, "can't fetch device resource info\n");
                 goto done;
         }
 
-        err = pci_request_region(pdev, GPIO_BAR, DRV_NAME);
-        if (err) {
-                dev_err(&pdev->dev, "can't alloc PCI BAR #%d\n", GPIO_BAR);
+        if (!request_region(res->start, resource_size(res), pdev->name)) {
+                dev_err(&pdev->dev, "can't request region\n");
                 goto done;
         }
 
         /* set up the driver-specific struct */
-        cs5535_gpio_chip.base = pci_resource_start(pdev, GPIO_BAR);
+        cs5535_gpio_chip.base = res->start;
         cs5535_gpio_chip.pdev = pdev;
         spin_lock_init(&cs5535_gpio_chip.lock);
 
-        dev_info(&pdev->dev, "allocated PCI BAR #%d: base 0x%llx\n", GPIO_BAR,
-                        (unsigned long long) cs5535_gpio_chip.base);
+        dev_info(&pdev->dev, "reserved resource region %pR\n", res);
 
         /* mask out reserved pins */
         mask &= 0x1F7FFFFF;
@@ -275,78 +347,49 @@ static int __init cs5535_gpio_probe(struct pci_dev *pdev,
         if (err)
                 goto release_region;
 
-        dev_info(&pdev->dev, DRV_NAME ": GPIO support successfully loaded.\n");
+        dev_info(&pdev->dev, "GPIO support successfully loaded.\n");
         return 0;
 
 release_region:
-        pci_release_region(pdev, GPIO_BAR);
+        release_region(res->start, resource_size(res));
 done:
         return err;
 }
 
-static void __exit cs5535_gpio_remove(struct pci_dev *pdev)
+static int __devexit cs5535_gpio_remove(struct platform_device *pdev)
 {
+        struct resource *r;
         int err;
 
         err = gpiochip_remove(&cs5535_gpio_chip.chip);
         if (err) {
                 /* uhh? */
                 dev_err(&pdev->dev, "unable to remove gpio_chip?\n");
+                return err;
         }
-        pci_release_region(pdev, GPIO_BAR);
-}
-
-static struct pci_device_id cs5535_gpio_pci_tbl[] = {
-        { PCI_DEVICE(PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_CS5535_ISA) },
-        { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA) },
-        { 0, },
-};
-MODULE_DEVICE_TABLE(pci, cs5535_gpio_pci_tbl);
 
-/*
- * We can't use the standard PCI driver registration stuff here, since
- * that allows only one driver to bind to each PCI device (and we want
- * multiple drivers to be able to bind to the device).  Instead, manually
- * scan for the PCI device, request a single region, and keep track of the
- * devices that we're using.
- */
-
-static int __init cs5535_gpio_scan_pci(void)
-{
-        struct pci_dev *pdev;
-        int err = -ENODEV;
-        int i;
-
-        for (i = 0; i < ARRAY_SIZE(cs5535_gpio_pci_tbl); i++) {
-                pdev = pci_get_device(cs5535_gpio_pci_tbl[i].vendor,
-                                cs5535_gpio_pci_tbl[i].device, NULL);
-                if (pdev) {
-                        err = cs5535_gpio_probe(pdev, &cs5535_gpio_pci_tbl[i]);
-                        if (err)
-                                pci_dev_put(pdev);
-
-                        /* we only support a single CS5535/6 southbridge */
-                        break;
-                }
-        }
-
-        return err;
+        r = platform_get_resource(pdev, IORESOURCE_IO, 0);
+        release_region(r->start, resource_size(r));
+        return 0;
 }
 
-static void __exit cs5535_gpio_free_pci(void)
-{
-        cs5535_gpio_remove(cs5535_gpio_chip.pdev);
-        pci_dev_put(cs5535_gpio_chip.pdev);
-}
+static struct platform_driver cs5535_gpio_driver = {
+        .driver = {
+                .name = DRV_NAME,
+                .owner = THIS_MODULE,
+        },
+        .probe = cs5535_gpio_probe,
+        .remove = __devexit_p(cs5535_gpio_remove),
+};
 
 static int __init cs5535_gpio_init(void)
 {
-        return cs5535_gpio_scan_pci();
+        return platform_driver_register(&cs5535_gpio_driver);
 }
 
 static void __exit cs5535_gpio_exit(void)
 {
-        cs5535_gpio_free_pci();
+        platform_driver_unregister(&cs5535_gpio_driver);
 }
 
 module_init(cs5535_gpio_init);
@@ -355,3 +398,4 @@ module_exit(cs5535_gpio_exit);
 MODULE_AUTHOR("Andres Salomon <dilinger@queued.net>");
 MODULE_DESCRIPTION("AMD CS5535/CS5536 GPIO driver");
 MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:" DRV_NAME);