Merge branch 'next' into for-linus

27 files changed, 215 insertions, 241 deletions

diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
index 5948a2194f50..fdffa1beca17 100644
--- a/drivers/edac/Kconfig
+++ b/drivers/edac/Kconfig
@@ -215,7 +215,7 @@ config EDAC_I7300
 config EDAC_SBRIDGE
         tristate "Intel Sandy-Bridge Integrated MC"
         depends on EDAC_MM_EDAC && PCI && X86_64 && X86_MCE_INTEL
-        depends on EXPERIMENTAL
+        depends on PCI_MMCONFIG && EXPERIMENTAL
         help
           Support for error detection and correction the Intel
           Sandy Bridge Integrated Memory Controller.
diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index c9eee6d33e9a..7ef73c919c5d 100644
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -1132,12 +1132,36 @@ static int k8_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct,
                 return ddr2_cs_size(cs_mode, dclr & WIDTH_128);
         }
         else if (pvt->ext_model >= K8_REV_D) {
+                unsigned diff;
                 WARN_ON(cs_mode > 10);
 
-                if (cs_mode == 3 || cs_mode == 8)
-                        return 32 << (cs_mode - 1);
-                else
-                        return 32 << cs_mode;
+                /*
+                 * the below calculation, besides trying to win an obfuscated C
+                 * contest, maps cs_mode values to DIMM chip select sizes. The
+                 * mappings are:
+                 *
+                 * cs_mode      CS size (mb)
+                 * =======      ============
+                 * 0            32
+                 * 1            64
+                 * 2            128
+                 * 3            128
+                 * 4            256
+                 * 5            512
+                 * 6            256
+                 * 7            512
+                 * 8            1024
+                 * 9            1024
+                 * 10           2048
+                 *
+                 * Basically, it calculates a value with which to shift the
+                 * smallest CS size of 32MB.
+                 *
+                 * ddr[23]_cs_size have a similar purpose.
+                 */
+                diff = cs_mode/3 + (unsigned)(cs_mode > 5);
+
+                return 32 << (cs_mode - diff);
         }
         else {
                 WARN_ON(cs_mode > 6);
@@ -2133,6 +2157,7 @@ static void read_mc_regs(struct amd64_pvt *pvt)
 static u32 amd64_csrow_nr_pages(struct amd64_pvt *pvt, u8 dct, int csrow_nr)
 {
         u32 cs_mode, nr_pages;
+        u32 dbam = dct ? pvt->dbam1 : pvt->dbam0;
 
         /*
          * The math on this doesn't look right on the surface because x/2*4 can
@@ -2141,16 +2166,10 @@ static u32 amd64_csrow_nr_pages(struct amd64_pvt *pvt, u8 dct, int csrow_nr)
          * number of bits to shift the DBAM register to extract the proper CSROW
          * field.
          */
-        cs_mode = (pvt->dbam0 >> ((csrow_nr / 2) * 4)) & 0xF;
+        cs_mode =  (dbam >> ((csrow_nr / 2) * 4)) & 0xF;
 
         nr_pages = pvt->ops->dbam_to_cs(pvt, dct, cs_mode) << (20 - PAGE_SHIFT);
 
-        /*
-         * If dual channel then double the memory size of single channel.
-         * Channel count is 1 or 2
-         */
-        nr_pages <<= (pvt->channel_count - 1);
-
         debugf0("  (csrow=%d) DBAM map index= %d\n", csrow_nr, cs_mode);
         debugf0("    nr_pages= %u  channel-count = %d\n",
                 nr_pages, pvt->channel_count);
@@ -2181,7 +2200,7 @@ static int init_csrows(struct mem_ctl_info *mci)
         for_each_chip_select(i, 0, pvt) {
                 csrow = &mci->csrows[i];
 
-                if (!csrow_enabled(i, 0, pvt)) {
+                if (!csrow_enabled(i, 0, pvt) && !csrow_enabled(i, 1, pvt)) {
                         debugf1("----CSROW %d EMPTY for node %d\n", i,
                                 pvt->mc_node_id);
                         continue;
@@ -2191,7 +2210,10 @@ static int init_csrows(struct mem_ctl_info *mci)
                         i, pvt->mc_node_id);
 
                 empty = 0;
-                csrow->nr_pages = amd64_csrow_nr_pages(pvt, 0, i);
+                if (csrow_enabled(i, 0, pvt))
+                        csrow->nr_pages = amd64_csrow_nr_pages(pvt, 0, i);
+                if (csrow_enabled(i, 1, pvt))
+                        csrow->nr_pages += amd64_csrow_nr_pages(pvt, 1, i);
                 find_csrow_limits(mci, i, &input_addr_min, &input_addr_max);
                 sys_addr = input_addr_to_sys_addr(mci, input_addr_min);
                 csrow->first_page = (u32) (sys_addr >> PAGE_SHIFT);
@@ -2685,7 +2707,7 @@ static void __devexit amd64_remove_one_instance(struct pci_dev *pdev)
  * PCI core identifies what devices are on a system during boot, and then
  * inquiry this table to see if this driver is for a given device found.
  */
-static const struct pci_device_id amd64_pci_table[] __devinitdata = {
+static DEFINE_PCI_DEVICE_TABLE(amd64_pci_table) = {
         {
                 .vendor         = PCI_VENDOR_ID_AMD,
                 .device         = PCI_DEVICE_ID_AMD_K8_NB_MEMCTL,
diff --git a/drivers/edac/amd76x_edac.c b/drivers/edac/amd76x_edac.c
index e47e73bbbcc5..f8fd3c807bde 100644
--- a/drivers/edac/amd76x_edac.c
+++ b/drivers/edac/amd76x_edac.c
@@ -321,7 +321,7 @@ static void __devexit amd76x_remove_one(struct pci_dev *pdev)
         edac_mc_free(mci);
 }
 
-static const struct pci_device_id amd76x_pci_tbl[] __devinitdata = {
+static DEFINE_PCI_DEVICE_TABLE(amd76x_pci_tbl) = {
         {
          PCI_VEND_DEV(AMD, FE_GATE_700C), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
          AMD762},
diff --git a/drivers/edac/e752x_edac.c b/drivers/edac/e752x_edac.c
index 1af531a11d21..41223261ede9 100644
--- a/drivers/edac/e752x_edac.c
+++ b/drivers/edac/e752x_edac.c
@@ -1380,7 +1380,7 @@ static void __devexit e752x_remove_one(struct pci_dev *pdev)
         edac_mc_free(mci);
 }
 
-static const struct pci_device_id e752x_pci_tbl[] __devinitdata = {
+static DEFINE_PCI_DEVICE_TABLE(e752x_pci_tbl) = {
         {
          PCI_VEND_DEV(INTEL, 7520_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
          E7520},
diff --git a/drivers/edac/e7xxx_edac.c b/drivers/edac/e7xxx_edac.c
index 6ffb6d23281f..68dea87b72e6 100644
--- a/drivers/edac/e7xxx_edac.c
+++ b/drivers/edac/e7xxx_edac.c
@@ -525,7 +525,7 @@ static void __devexit e7xxx_remove_one(struct pci_dev *pdev)
         edac_mc_free(mci);
 }
 
-static const struct pci_device_id e7xxx_pci_tbl[] __devinitdata = {
+static DEFINE_PCI_DEVICE_TABLE(e7xxx_pci_tbl) = {
         {
          PCI_VEND_DEV(INTEL, 7205_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
          E7205},
diff --git a/drivers/edac/edac_mc.c b/drivers/edac/edac_mc.c
index ca6c04d350ee..feef7733fae7 100644
--- a/drivers/edac/edac_mc.c
+++ b/drivers/edac/edac_mc.c
@@ -39,7 +39,7 @@ static LIST_HEAD(mc_devices);
 
 #ifdef CONFIG_EDAC_DEBUG
 
-static void edac_mc_dump_channel(struct channel_info *chan)
+static void edac_mc_dump_channel(struct rank_info *chan)
 {
         debugf4("\tchannel = %p\n", chan);
         debugf4("\tchannel->chan_idx = %d\n", chan->chan_idx);
@@ -156,7 +156,7 @@ struct mem_ctl_info *edac_mc_alloc(unsigned sz_pvt, unsigned nr_csrows,
 {
         struct mem_ctl_info *mci;
         struct csrow_info *csi, *csrow;
-        struct channel_info *chi, *chp, *chan;
+        struct rank_info *chi, *chp, *chan;
         void *pvt;
         unsigned size;
         int row, chn;
@@ -181,7 +181,7 @@ struct mem_ctl_info *edac_mc_alloc(unsigned sz_pvt, unsigned nr_csrows,
          * rather than an imaginary chunk of memory located at address 0.
          */
         csi = (struct csrow_info *)(((char *)mci) + ((unsigned long)csi));
-        chi = (struct channel_info *)(((char *)mci) + ((unsigned long)chi));
+        chi = (struct rank_info *)(((char *)mci) + ((unsigned long)chi));
         pvt = sz_pvt ? (((char *)mci) + ((unsigned long)pvt)) : NULL;
 
         /* setup index and various internal pointers */
@@ -620,13 +620,13 @@ static void edac_mc_scrub_block(unsigned long page, unsigned long offset,
         if (PageHighMem(pg))
                 local_irq_save(flags);
 
-        virt_addr = kmap_atomic(pg, KM_BOUNCE_READ);
+        virt_addr = kmap_atomic(pg);
 
         /* Perform architecture specific atomic scrub operation */
         atomic_scrub(virt_addr + offset, size);
 
         /* Unmap and complete */
-        kunmap_atomic(virt_addr, KM_BOUNCE_READ);
+        kunmap_atomic(virt_addr);
 
         if (PageHighMem(pg))
                 local_irq_restore(flags);
diff --git a/drivers/edac/edac_mc_sysfs.c b/drivers/edac/edac_mc_sysfs.c
index d56e63477d5c..e9a28f576d14 100644
--- a/drivers/edac/edac_mc_sysfs.c
+++ b/drivers/edac/edac_mc_sysfs.c
@@ -452,7 +452,7 @@ static ssize_t mci_sdram_scrub_rate_store(struct mem_ctl_info *mci,
         int new_bw = 0;
 
         if (!mci->set_sdram_scrub_rate)
-                return -EINVAL;
+                return -ENODEV;
 
         if (strict_strtoul(data, 10, &bandwidth) < 0)
                 return -EINVAL;
@@ -475,7 +475,7 @@ static ssize_t mci_sdram_scrub_rate_show(struct mem_ctl_info *mci, char *data)
         int bandwidth = 0;
 
         if (!mci->get_sdram_scrub_rate)
-                return -EINVAL;
+                return -ENODEV;
 
         bandwidth = mci->get_sdram_scrub_rate(mci);
         if (bandwidth < 0) {
diff --git a/drivers/edac/edac_stub.c b/drivers/edac/edac_stub.c
index 670c4481453b..6c86f6e54558 100644
--- a/drivers/edac/edac_stub.c
+++ b/drivers/edac/edac_stub.c
@@ -15,6 +15,7 @@
 #include <linux/module.h>
 #include <linux/edac.h>
 #include <linux/atomic.h>
+#include <linux/device.h>
 #include <asm/edac.h>
 
 int edac_op_state = EDAC_OPSTATE_INVAL;
diff --git a/drivers/edac/i3000_edac.c b/drivers/edac/i3000_edac.c
index c0510b3d7035..277689a68841 100644
--- a/drivers/edac/i3000_edac.c
+++ b/drivers/edac/i3000_edac.c
@@ -470,7 +470,7 @@ static void __devexit i3000_remove_one(struct pci_dev *pdev)
         edac_mc_free(mci);
 }
 
-static const struct pci_device_id i3000_pci_tbl[] __devinitdata = {
+static DEFINE_PCI_DEVICE_TABLE(i3000_pci_tbl) = {
         {
          PCI_VEND_DEV(INTEL, 3000_HB), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
          I3000},
diff --git a/drivers/edac/i3200_edac.c b/drivers/edac/i3200_edac.c
index 73f55e2008c2..046808c6357d 100644
--- a/drivers/edac/i3200_edac.c
+++ b/drivers/edac/i3200_edac.c
@@ -445,7 +445,7 @@ static void __devexit i3200_remove_one(struct pci_dev *pdev)
         edac_mc_free(mci);
 }
 
-static const struct pci_device_id i3200_pci_tbl[] __devinitdata = {
+static DEFINE_PCI_DEVICE_TABLE(i3200_pci_tbl) = {
         {
                 PCI_VEND_DEV(INTEL, 3200_HB), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
                 I3200},
diff --git a/drivers/edac/i5000_edac.c b/drivers/edac/i5000_edac.c
index 4dc3ac25a422..a2680d8e744b 100644
--- a/drivers/edac/i5000_edac.c
+++ b/drivers/edac/i5000_edac.c
@@ -1516,7 +1516,7 @@ static void __devexit i5000_remove_one(struct pci_dev *pdev)
  *
  *      The "E500P" device is the first device supported.
  */
-static const struct pci_device_id i5000_pci_tbl[] __devinitdata = {
+static DEFINE_PCI_DEVICE_TABLE(i5000_pci_tbl) = {
         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000_DEV16),
          .driver_data = I5000P},
 
diff --git a/drivers/edac/i5100_edac.c b/drivers/edac/i5100_edac.c
index bcbdeeca48b8..d500749464ea 100644
--- a/drivers/edac/i5100_edac.c
+++ b/drivers/edac/i5100_edac.c
@@ -49,7 +49,7 @@
 #define         I5100_FERR_NF_MEM_M6ERR_MASK    (1 << 6)
 #define         I5100_FERR_NF_MEM_M5ERR_MASK    (1 << 5)
 #define         I5100_FERR_NF_MEM_M4ERR_MASK    (1 << 4)
-#define         I5100_FERR_NF_MEM_M1ERR_MASK    1
+#define         I5100_FERR_NF_MEM_M1ERR_MASK    (1 << 1)
 #define         I5100_FERR_NF_MEM_ANY_MASK      \
                         (I5100_FERR_NF_MEM_M16ERR_MASK | \
                         I5100_FERR_NF_MEM_M15ERR_MASK | \
@@ -535,23 +535,20 @@ static void i5100_read_log(struct mem_ctl_info *mci, int chan,
 static void i5100_check_error(struct mem_ctl_info *mci)
 {
         struct i5100_priv *priv = mci->pvt_info;
-        u32 dw;
-
+        u32 dw, dw2;
 
         pci_read_config_dword(priv->mc, I5100_FERR_NF_MEM, &dw);
         if (i5100_ferr_nf_mem_any(dw)) {
-                u32 dw2;
 
                 pci_read_config_dword(priv->mc, I5100_NERR_NF_MEM, &dw2);
-                if (dw2)
-                        pci_write_config_dword(priv->mc, I5100_NERR_NF_MEM,
-                                               dw2);
-                pci_write_config_dword(priv->mc, I5100_FERR_NF_MEM, dw);
 
                 i5100_read_log(mci, i5100_ferr_nf_mem_chan_indx(dw),
                                i5100_ferr_nf_mem_any(dw),
                                i5100_nerr_nf_mem_any(dw2));
+
+                pci_write_config_dword(priv->mc, I5100_NERR_NF_MEM, dw2);
         }
+        pci_write_config_dword(priv->mc, I5100_FERR_NF_MEM, dw);
 }
 
 /* The i5100 chipset will scrub the entire memory once, then
@@ -1051,7 +1048,7 @@ static void __devexit i5100_remove_one(struct pci_dev *pdev)
         edac_mc_free(mci);
 }
 
-static const struct pci_device_id i5100_pci_tbl[] __devinitdata = {
+static DEFINE_PCI_DEVICE_TABLE(i5100_pci_tbl) = {
         /* Device 16, Function 0, Channel 0 Memory Map, Error Flag/Mask, ... */
         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5100_16) },
         { 0, }
diff --git a/drivers/edac/i5400_edac.c b/drivers/edac/i5400_edac.c
index 74d6ec342afb..1869a1018fb5 100644
--- a/drivers/edac/i5400_edac.c
+++ b/drivers/edac/i5400_edac.c
@@ -735,7 +735,7 @@ static int i5400_get_devices(struct mem_ctl_info *mci, int dev_idx)
 
         /* Attempt to 'get' the MCH register we want */
         pdev = NULL;
-        while (!pvt->branchmap_werrors || !pvt->fsb_error_regs) {
+        while (1) {
                 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
                                       PCI_DEVICE_ID_INTEL_5400_ERR, pdev);
                 if (!pdev) {
@@ -743,23 +743,42 @@ static int i5400_get_devices(struct mem_ctl_info *mci, int dev_idx)
                         i5400_printk(KERN_ERR,
                                 "'system address,Process Bus' "
                                 "device not found:"
-                                "vendor 0x%x device 0x%x ERR funcs "
+                                "vendor 0x%x device 0x%x ERR func 1 "
                                 "(broken BIOS?)\n",
                                 PCI_VENDOR_ID_INTEL,
                                 PCI_DEVICE_ID_INTEL_5400_ERR);
-                        goto error;
+                        return -ENODEV;
                 }
 
-                /* Store device 16 funcs 1 and 2 */
-                switch (PCI_FUNC(pdev->devfn)) {
-                case 1:
-                        pvt->branchmap_werrors = pdev;
-                        break;
-                case 2:
-                        pvt->fsb_error_regs = pdev;
+                /* Store device 16 func 1 */
+                if (PCI_FUNC(pdev->devfn) == 1)
                         break;
+        }
+        pvt->branchmap_werrors = pdev;
+
+        pdev = NULL;
+        while (1) {
+                pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
+                                      PCI_DEVICE_ID_INTEL_5400_ERR, pdev);
+                if (!pdev) {
+                        /* End of list, leave */
+                        i5400_printk(KERN_ERR,
+                                "'system address,Process Bus' "
+                                "device not found:"
+                                "vendor 0x%x device 0x%x ERR func 2 "
+                                "(broken BIOS?)\n",
+                                PCI_VENDOR_ID_INTEL,
+                                PCI_DEVICE_ID_INTEL_5400_ERR);
+
+                        pci_dev_put(pvt->branchmap_werrors);
+                        return -ENODEV;
                 }
+
+                /* Store device 16 func 2 */
+                if (PCI_FUNC(pdev->devfn) == 2)
+                        break;
         }
+        pvt->fsb_error_regs = pdev;
 
         debugf1("System Address, processor bus- PCI Bus ID: %s  %x:%x\n",
                 pci_name(pvt->system_address),
@@ -778,7 +797,10 @@ static int i5400_get_devices(struct mem_ctl_info *mci, int dev_idx)
                         "MC: 'BRANCH 0' device not found:"
                         "vendor 0x%x device 0x%x Func 0 (broken BIOS?)\n",
                         PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5400_FBD0);
-                goto error;
+
+                pci_dev_put(pvt->fsb_error_regs);
+                pci_dev_put(pvt->branchmap_werrors);
+                return -ENODEV;
         }
 
         /* If this device claims to have more than 2 channels then
@@ -796,14 +818,14 @@ static int i5400_get_devices(struct mem_ctl_info *mci, int dev_idx)
                         "(broken BIOS?)\n",
                         PCI_VENDOR_ID_INTEL,
                         PCI_DEVICE_ID_INTEL_5400_FBD1);
-                goto error;
+
+                pci_dev_put(pvt->branch_0);
+                pci_dev_put(pvt->fsb_error_regs);
+                pci_dev_put(pvt->branchmap_werrors);
+                return -ENODEV;
         }
 
         return 0;
-
-error:
-        i5400_put_devices(mci);
-        return -ENODEV;
 }
 
 /*
@@ -1383,7 +1405,7 @@ static void __devexit i5400_remove_one(struct pci_dev *pdev)
  *
  *      The "E500P" device is the first device supported.
  */
-static const struct pci_device_id i5400_pci_tbl[] __devinitdata = {
+static DEFINE_PCI_DEVICE_TABLE(i5400_pci_tbl) = {
         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5400_ERR)},
         {0,}                    /* 0 terminated list. */
 };
diff --git a/drivers/edac/i7300_edac.c b/drivers/edac/i7300_edac.c
index 6104dba380b6..3bafa3bca148 100644
--- a/drivers/edac/i7300_edac.c
+++ b/drivers/edac/i7300_edac.c
@@ -1192,7 +1192,7 @@ static void __devexit i7300_remove_one(struct pci_dev *pdev)
  *
  * Has only 8086:360c PCI ID
  */
-static const struct pci_device_id i7300_pci_tbl[] __devinitdata = {
+static DEFINE_PCI_DEVICE_TABLE(i7300_pci_tbl) = {
         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I7300_MCH_ERR)},
         {0,}                    /* 0 terminated list. */
 };
diff --git a/drivers/edac/i7core_edac.c b/drivers/edac/i7core_edac.c
index 8568d9b61875..85226ccf5290 100644
--- a/drivers/edac/i7core_edac.c
+++ b/drivers/edac/i7core_edac.c
@@ -391,7 +391,7 @@ static const struct pci_id_table pci_dev_table[] = {
 /*
  *      pci_device_id   table for which devices we are looking for
  */
-static const struct pci_device_id i7core_pci_tbl[] __devinitdata = {
+static DEFINE_PCI_DEVICE_TABLE(i7core_pci_tbl) = {
         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_X58_HUB_MGMT)},
         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNNFIELD_QPI_LINK0)},
         {0,}                    /* 0 terminated list. */
diff --git a/drivers/edac/i82443bxgx_edac.c b/drivers/edac/i82443bxgx_edac.c
index 4329d39f902c..3bf2b2f490e7 100644
--- a/drivers/edac/i82443bxgx_edac.c
+++ b/drivers/edac/i82443bxgx_edac.c
@@ -380,7 +380,7 @@ static void __devexit i82443bxgx_edacmc_remove_one(struct pci_dev *pdev)
 
 EXPORT_SYMBOL_GPL(i82443bxgx_edacmc_remove_one);
 
-static const struct pci_device_id i82443bxgx_pci_tbl[] __devinitdata = {
+static DEFINE_PCI_DEVICE_TABLE(i82443bxgx_pci_tbl) = {
         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0)},
         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2)},
         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_0)},
diff --git a/drivers/edac/i82860_edac.c b/drivers/edac/i82860_edac.c
index 931a05775049..c779092d18d1 100644
--- a/drivers/edac/i82860_edac.c
+++ b/drivers/edac/i82860_edac.c
@@ -270,7 +270,7 @@ static void __devexit i82860_remove_one(struct pci_dev *pdev)
         edac_mc_free(mci);
 }
 
-static const struct pci_device_id i82860_pci_tbl[] __devinitdata = {
+static DEFINE_PCI_DEVICE_TABLE(i82860_pci_tbl) = {
         {
          PCI_VEND_DEV(INTEL, 82860_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
          I82860},
diff --git a/drivers/edac/i82875p_edac.c b/drivers/edac/i82875p_edac.c
index 33864c63c684..10f15d85fb5e 100644
--- a/drivers/edac/i82875p_edac.c
+++ b/drivers/edac/i82875p_edac.c
@@ -511,7 +511,7 @@ static void __devexit i82875p_remove_one(struct pci_dev *pdev)
         edac_mc_free(mci);
 }
 
-static const struct pci_device_id i82875p_pci_tbl[] __devinitdata = {
+static DEFINE_PCI_DEVICE_TABLE(i82875p_pci_tbl) = {
         {
          PCI_VEND_DEV(INTEL, 82875_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
          I82875P},
diff --git a/drivers/edac/i82975x_edac.c b/drivers/edac/i82975x_edac.c
index 4184e0171f00..0cd8368f88f8 100644
--- a/drivers/edac/i82975x_edac.c
+++ b/drivers/edac/i82975x_edac.c
@@ -612,7 +612,7 @@ static void __devexit i82975x_remove_one(struct pci_dev *pdev)
         edac_mc_free(mci);
 }
 
-static const struct pci_device_id i82975x_pci_tbl[] __devinitdata = {
+static DEFINE_PCI_DEVICE_TABLE(i82975x_pci_tbl) = {
         {
                 PCI_VEND_DEV(INTEL, 82975_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
                 I82975X
diff --git a/drivers/edac/mce_amd.c b/drivers/edac/mce_amd.c
index bd926ea2e00c..d0c372e30de4 100644
--- a/drivers/edac/mce_amd.c
+++ b/drivers/edac/mce_amd.c
@@ -39,42 +39,31 @@ EXPORT_SYMBOL_GPL(amd_unregister_ecc_decoder);
  */
 
 /* transaction type */
-const char *tt_msgs[] = { "INSN", "DATA", "GEN", "RESV" };
+const char * const tt_msgs[] = { "INSN", "DATA", "GEN", "RESV" };
 EXPORT_SYMBOL_GPL(tt_msgs);
 
 /* cache level */
-const char *ll_msgs[] = { "RESV", "L1", "L2", "L3/GEN" };
+const char * const ll_msgs[] = { "RESV", "L1", "L2", "L3/GEN" };
 EXPORT_SYMBOL_GPL(ll_msgs);
 
 /* memory transaction type */
-const char *rrrr_msgs[] = {
+const char * const rrrr_msgs[] = {
        "GEN", "RD", "WR", "DRD", "DWR", "IRD", "PRF", "EV", "SNP"
 };
 EXPORT_SYMBOL_GPL(rrrr_msgs);
 
 /* participating processor */
-const char *pp_msgs[] = { "SRC", "RES", "OBS", "GEN" };
+const char * const pp_msgs[] = { "SRC", "RES", "OBS", "GEN" };
 EXPORT_SYMBOL_GPL(pp_msgs);
 
 /* request timeout */
-const char *to_msgs[] = { "no timeout", "timed out" };
+const char * const to_msgs[] = { "no timeout", "timed out" };
 EXPORT_SYMBOL_GPL(to_msgs);
 
 /* memory or i/o */
-const char *ii_msgs[] = { "MEM", "RESV", "IO", "GEN" };
+const char * const ii_msgs[] = { "MEM", "RESV", "IO", "GEN" };
 EXPORT_SYMBOL_GPL(ii_msgs);
 
-static const char *f10h_nb_mce_desc[] = {
-        "HT link data error",
-        "Protocol error (link, L3, probe filter, etc.)",
-        "Parity error in NB-internal arrays",
-        "Link Retry due to IO link transmission error",
-        "L3 ECC data cache error",
-        "ECC error in L3 cache tag",
-        "L3 LRU parity bits error",
-        "ECC Error in the Probe Filter directory"
-};
-
 static const char * const f15h_ic_mce_desc[] = {
         "UC during a demand linefill from L2",
         "Parity error during data load from IC",
@@ -88,7 +77,7 @@ static const char * const f15h_ic_mce_desc[] = {
         "Parity error for IC probe tag valid bit",
         "PFB non-cacheable bit parity error",
         "PFB valid bit parity error",                   /* xec = 0xd */
-        "patch RAM",                                    /* xec = 010 */
+        "Microcode Patch Buffer",                       /* xec = 010 */
         "uop queue",
         "insn buffer",
         "predecode buffer",
@@ -104,7 +93,7 @@ static const char * const f15h_cu_mce_desc[] = {
         "WCC Tag ECC error",
         "WCC Data ECC error",
         "WCB Data parity error",
-        "VB Data/ECC error",
+        "VB Data ECC or parity error",
         "L2 Tag ECC error",                             /* xec = 0x10 */
         "Hard L2 Tag ECC error",
         "Multiple hits on L2 tag",
@@ -112,6 +101,28 @@ static const char * const f15h_cu_mce_desc[] = {
         "PRB address parity error"
 };
 
+static const char * const nb_mce_desc[] = {
+        "DRAM ECC error detected on the NB",
+        "CRC error detected on HT link",
+        "Link-defined sync error packets detected on HT link",
+        "HT Master abort",
+        "HT Target abort",
+        "Invalid GART PTE entry during GART table walk",
+        "Unsupported atomic RMW received from an IO link",
+        "Watchdog timeout due to lack of progress",
+        "DRAM ECC error detected on the NB",
+        "SVM DMA Exclusion Vector error",
+        "HT data error detected on link",
+        "Protocol error (link, L3, probe filter)",
+        "NB internal arrays parity error",
+        "DRAM addr/ctl signals parity error",
+        "IO link transmission error",
+        "L3 data cache ECC error",                      /* xec = 0x1c */
+        "L3 cache tag error",
+        "L3 LRU parity bits error",
+        "ECC Error in the Probe Filter directory"
+};
+
 static const char * const fr_ex_mce_desc[] = {
         "CPU Watchdog timer expire",
         "Wakeup array dest tag",
@@ -125,7 +136,7 @@ static const char * const fr_ex_mce_desc[] = {
         "Physical register file AG0 port",
         "Physical register file AG1 port",
         "Flag register file",
-        "DE correctable error could not be corrected"
+        "DE error occurred"
 };
 
 static bool f12h_dc_mce(u16 ec, u8 xec)
@@ -255,10 +266,9 @@ static bool f15h_dc_mce(u16 ec, u8 xec)
         } else if (BUS_ERROR(ec)) {
 
                 if (!xec)
-                        pr_cont("during system linefill.\n");
+                        pr_cont("System Read Data Error.\n");
                 else
-                        pr_cont(" Internal %s condition.\n",
-                                ((xec == 1) ? "livelock" : "deadlock"));
+                        pr_cont(" Internal error condition type %d.\n", xec);
         } else
                 ret = false;
 
@@ -355,7 +365,11 @@ static bool f15h_ic_mce(u16 ec, u8 xec)
                 pr_cont("%s.\n", f15h_ic_mce_desc[xec-2]);
                 break;
 
-        case 0x10 ... 0x14:
+        case 0x10:
+                pr_cont("%s.\n", f15h_ic_mce_desc[xec-4]);
+                break;
+
+        case 0x11 ... 0x14:
                 pr_cont("Decoder %s parity error.\n", f15h_ic_mce_desc[xec-4]);
                 break;
 
@@ -496,58 +510,31 @@ wrong_ls_mce:
         pr_emerg(HW_ERR "Corrupted LS MCE info?\n");
 }
 
-static bool k8_nb_mce(u16 ec, u8 xec)
+void amd_decode_nb_mce(struct mce *m)
 {
-        bool ret = true;
-
-        switch (xec) {
-        case 0x1:
-                pr_cont("CRC error detected on HT link.\n");
-                break;
-
-        case 0x5:
-                pr_cont("Invalid GART PTE entry during GART table walk.\n");
-                break;
-
-        case 0x6:
-                pr_cont("Unsupported atomic RMW received from an IO link.\n");
-                break;
-
-        case 0x0:
-        case 0x8:
-                if (boot_cpu_data.x86 == 0x11)
-                        return false;
-
-                pr_cont("DRAM ECC error detected on the NB.\n");
-                break;
-
-        case 0xd:
-                pr_cont("Parity error on the DRAM addr/ctl signals.\n");
-                break;
-
-        default:
-                ret = false;
-                break;
-        }
+        struct cpuinfo_x86 *c = &boot_cpu_data;
+        int node_id = amd_get_nb_id(m->extcpu);
+        u16 ec = EC(m->status);
+        u8 xec = XEC(m->status, 0x1f);
+        u8 offset = 0;
 
-        return ret;
-}
+        pr_emerg(HW_ERR "Northbridge Error (node %d): ", node_id);
 
-static bool f10h_nb_mce(u16 ec, u8 xec)
-{
-        bool ret = true;
-        u8 offset = 0;
+        switch (xec) {
+        case 0x0 ... 0xe:
 
-        if (k8_nb_mce(ec, xec))
-                return true;
+                /* special handling for DRAM ECCs */
+                if (xec == 0x0 || xec == 0x8) {
+                        /* no ECCs on F11h */
+                        if (c->x86 == 0x11)
+                                goto wrong_nb_mce;
 
-        switch(xec) {
-        case 0xa ... 0xc:
-                offset = 10;
-                break;
+                        pr_cont("%s.\n", nb_mce_desc[xec]);
 
-        case 0xe:
-                offset = 11;
+                        if (nb_bus_decoder)
+                                nb_bus_decoder(node_id, m);
+                        return;
+                }
                 break;
 
         case 0xf:
@@ -556,83 +543,25 @@ static bool f10h_nb_mce(u16 ec, u8 xec)
                 else if (BUS_ERROR(ec))
                         pr_cont("DMA Exclusion Vector Table Walk error.\n");
                 else
-                        ret = false;
-
-                goto out;
-                break;
+                        goto wrong_nb_mce;
+                return;
 
         case 0x19:
                 if (boot_cpu_data.x86 == 0x15)
                         pr_cont("Compute Unit Data Error.\n");
                 else
-                        ret = false;
-
-                goto out;
-                break;
+                        goto wrong_nb_mce;
+                return;
 
         case 0x1c ... 0x1f:
-                offset = 24;
+                offset = 13;
                 break;
 
         default:
-                ret = false;
-
-                goto out;
-                break;
-        }
-
-        pr_cont("%s.\n", f10h_nb_mce_desc[xec - offset]);
-
-out:
-        return ret;
-}
-
-static bool nb_noop_mce(u16 ec, u8 xec)
-{
-        return false;
-}
-
-void amd_decode_nb_mce(struct mce *m)
-{
-        struct cpuinfo_x86 *c = &boot_cpu_data;
-        int node_id = amd_get_nb_id(m->extcpu);
-        u16 ec = EC(m->status);
-        u8 xec = XEC(m->status, 0x1f);
-
-        pr_emerg(HW_ERR "Northbridge Error (node %d): ", node_id);
-
-        switch (xec) {
-        case 0x2:
-                pr_cont("Sync error (sync packets on HT link detected).\n");
-                return;
-
-        case 0x3:
-                pr_cont("HT Master abort.\n");
-                return;
-
-        case 0x4:
-                pr_cont("HT Target abort.\n");
-                return;
-
-        case 0x7:
-                pr_cont("NB Watchdog timeout.\n");
-                return;
-
-        case 0x9:
-                pr_cont("SVM DMA Exclusion Vector error.\n");
-                return;
-
-        default:
-                break;
-        }
-
-        if (!fam_ops->nb_mce(ec, xec))
                 goto wrong_nb_mce;
+        }
 
-        if (c->x86 == 0xf || c->x86 == 0x10 || c->x86 == 0x15)
-                if ((xec == 0x8 || xec == 0x0) && nb_bus_decoder)
-                        nb_bus_decoder(node_id, m);
-
+        pr_cont("%s.\n", nb_mce_desc[xec - offset]);
         return;
 
 wrong_nb_mce:
@@ -648,9 +577,6 @@ static void amd_decode_fr_mce(struct mce *m)
         if (c->x86 == 0xf || c->x86 == 0x11)
                 goto wrong_fr_mce;
 
-        if (c->x86 != 0x15 && xec != 0x0)
-                goto wrong_fr_mce;
-
         pr_emerg(HW_ERR "%s Error: ",
                  (c->x86 == 0x15 ? "Execution Unit" : "FIROB"));
 
@@ -828,9 +754,7 @@ static int __init mce_amd_init(void)
         if (c->x86_vendor != X86_VENDOR_AMD)
                 return 0;
 
-        if ((c->x86 < 0xf || c->x86 > 0x12) &&
-            (c->x86 != 0x14 || c->x86_model > 0xf) &&
-            (c->x86 != 0x15 || c->x86_model > 0xf))
+        if (c->x86 < 0xf || c->x86 > 0x15)
                 return 0;
 
         fam_ops = kzalloc(sizeof(struct amd_decoder_ops), GFP_KERNEL);
@@ -841,43 +765,37 @@ static int __init mce_amd_init(void)
         case 0xf:
                 fam_ops->dc_mce = k8_dc_mce;
                 fam_ops->ic_mce = k8_ic_mce;
-                fam_ops->nb_mce = k8_nb_mce;
                 break;
 
         case 0x10:
                 fam_ops->dc_mce = f10h_dc_mce;
                 fam_ops->ic_mce = k8_ic_mce;
-                fam_ops->nb_mce = f10h_nb_mce;
                 break;
 
         case 0x11:
                 fam_ops->dc_mce = k8_dc_mce;
                 fam_ops->ic_mce = k8_ic_mce;
-                fam_ops->nb_mce = f10h_nb_mce;
                 break;
 
         case 0x12:
                 fam_ops->dc_mce = f12h_dc_mce;
                 fam_ops->ic_mce = k8_ic_mce;
-                fam_ops->nb_mce = nb_noop_mce;
                 break;
 
         case 0x14:
                 nb_err_cpumask  = 0x3;
                 fam_ops->dc_mce = f14h_dc_mce;
                 fam_ops->ic_mce = f14h_ic_mce;
-                fam_ops->nb_mce = nb_noop_mce;
                 break;
 
         case 0x15:
                 xec_mask = 0x1f;
                 fam_ops->dc_mce = f15h_dc_mce;
                 fam_ops->ic_mce = f15h_ic_mce;
-                fam_ops->nb_mce = f10h_nb_mce;
                 break;
 
         default:
-                printk(KERN_WARNING "Huh? What family is that: %d?!\n", c->x86);
+                printk(KERN_WARNING "Huh? What family is it: 0x%x?!\n", c->x86);
                 kfree(fam_ops);
                 return -EINVAL;
         }
diff --git a/drivers/edac/mce_amd.h b/drivers/edac/mce_amd.h
index 0106747e240c..c6074c5cd1ef 100644
--- a/drivers/edac/mce_amd.h
+++ b/drivers/edac/mce_amd.h
@@ -69,12 +69,12 @@ enum rrrr_ids {
         R4_SNOOP,
 };
 
-extern const char *tt_msgs[];
-extern const char *ll_msgs[];
-extern const char *rrrr_msgs[];
-extern const char *pp_msgs[];
-extern const char *to_msgs[];
-extern const char *ii_msgs[];
+extern const char * const tt_msgs[];
+extern const char * const ll_msgs[];
+extern const char * const rrrr_msgs[];
+extern const char * const pp_msgs[];
+extern const char * const to_msgs[];
+extern const char * const ii_msgs[];
 
 /*
  * per-family decoder ops
@@ -82,7 +82,6 @@ extern const char *ii_msgs[];
 struct amd_decoder_ops {
         bool (*dc_mce)(u16, u8);
         bool (*ic_mce)(u16, u8);
-        bool (*nb_mce)(u16, u8);
 };
 
 void amd_report_gart_errors(bool);
diff --git a/drivers/edac/mce_amd_inj.c b/drivers/edac/mce_amd_inj.c
index 885e8ad8fdcf..66b5151c1080 100644
--- a/drivers/edac/mce_amd_inj.c
+++ b/drivers/edac/mce_amd_inj.c
@@ -11,6 +11,7 @@
  */
 
 #include <linux/kobject.h>
+#include <linux/device.h>
 #include <linux/edac.h>
 #include <linux/module.h>
 #include <asm/mce.h>
diff --git a/drivers/edac/ppc4xx_edac.c b/drivers/edac/ppc4xx_edac.c
index fc757069c6af..d427c69bb8b1 100644
--- a/drivers/edac/ppc4xx_edac.c
+++ b/drivers/edac/ppc4xx_edac.c
@@ -184,7 +184,7 @@ struct ppc4xx_ecc_status {
 
 /* Function Prototypes */
 
-static int ppc4xx_edac_probe(struct platform_device *device)
+static int ppc4xx_edac_probe(struct platform_device *device);
 static int ppc4xx_edac_remove(struct platform_device *device);
 
 /* Global Variables */
@@ -1068,7 +1068,7 @@ ppc4xx_edac_mc_init(struct mem_ctl_info *mci,
 
         mci->mod_name           = PPC4XX_EDAC_MODULE_NAME;
         mci->mod_ver            = PPC4XX_EDAC_MODULE_REVISION;
-        mci->ctl_name           = match->compatible,
+        mci->ctl_name           = ppc4xx_edac_match->compatible,
         mci->dev_name           = np->full_name;
 
         /* Initialize callbacks */
diff --git a/drivers/edac/r82600_edac.c b/drivers/edac/r82600_edac.c
index e294e1b3616c..6d908ad72d64 100644
--- a/drivers/edac/r82600_edac.c
+++ b/drivers/edac/r82600_edac.c
@@ -373,7 +373,7 @@ static void __devexit r82600_remove_one(struct pci_dev *pdev)
         edac_mc_free(mci);
 }
 
-static const struct pci_device_id r82600_pci_tbl[] __devinitdata = {
+static DEFINE_PCI_DEVICE_TABLE(r82600_pci_tbl) = {
         {
          PCI_DEVICE(PCI_VENDOR_ID_RADISYS, R82600_BRIDGE_ID)
          },
diff --git a/drivers/edac/sb_edac.c b/drivers/edac/sb_edac.c
index 1dc118d83cc6..a203536d90dd 100644
--- a/drivers/edac/sb_edac.c
+++ b/drivers/edac/sb_edac.c
@@ -20,6 +20,7 @@
 #include <linux/mmzone.h>
 #include <linux/smp.h>
 #include <linux/bitmap.h>
+#include <linux/math64.h>
 #include <asm/processor.h>
 #include <asm/mce.h>
 
@@ -367,7 +368,7 @@ static const struct pci_id_table pci_dev_descr_sbridge_table[] = {
 /*
  *      pci_device_id   table for which devices we are looking for
  */
-static const struct pci_device_id sbridge_pci_tbl[] __devinitdata = {
+static DEFINE_PCI_DEVICE_TABLE(sbridge_pci_tbl) = {
         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA)},
         {0,}                    /* 0 terminated list. */
 };
@@ -670,6 +671,7 @@ static void get_memory_layout(const struct mem_ctl_info *mci)
         u32 reg;
         u64 limit, prv = 0;
         u64 tmp_mb;
+        u32 mb, kb;
         u32 rir_way;
 
         /*
@@ -682,8 +684,9 @@ static void get_memory_layout(const struct mem_ctl_info *mci)
         pvt->tolm = GET_TOLM(reg);
         tmp_mb = (1 + pvt->tolm) >> 20;
 
-        debugf0("TOLM: %Lu.%03Lu GB (0x%016Lx)\n",
-                tmp_mb / 1000, tmp_mb % 1000, (u64)pvt->tolm);
+        mb = div_u64_rem(tmp_mb, 1000, &kb);
+        debugf0("TOLM: %u.%03u GB (0x%016Lx)\n",
+                mb, kb, (u64)pvt->tolm);
 
         /* Address range is already 45:25 */
         pci_read_config_dword(pvt->pci_sad1, TOHM,
@@ -691,8 +694,9 @@ static void get_memory_layout(const struct mem_ctl_info *mci)
         pvt->tohm = GET_TOHM(reg);
         tmp_mb = (1 + pvt->tohm) >> 20;
 
-        debugf0("TOHM: %Lu.%03Lu GB (0x%016Lx)",
-                tmp_mb / 1000, tmp_mb % 1000, (u64)pvt->tohm);
+        mb = div_u64_rem(tmp_mb, 1000, &kb);
+        debugf0("TOHM: %u.%03u GB (0x%016Lx)",
+                mb, kb, (u64)pvt->tohm);
 
         /*
          * Step 2) Get SAD range and SAD Interleave list
@@ -714,10 +718,11 @@ static void get_memory_layout(const struct mem_ctl_info *mci)
                         break;
 
                 tmp_mb = (limit + 1) >> 20;
-                debugf0("SAD#%d %s up to %Lu.%03Lu GB (0x%016Lx) %s reg=0x%08x\n",
+                mb = div_u64_rem(tmp_mb, 1000, &kb);
+                debugf0("SAD#%d %s up to %u.%03u GB (0x%016Lx) %s reg=0x%08x\n",
                         n_sads,
                         get_dram_attr(reg),
-                        tmp_mb / 1000, tmp_mb % 1000,
+                        mb, kb,
                         ((u64)tmp_mb) << 20L,
                         INTERLEAVE_MODE(reg) ? "Interleave: 8:6" : "Interleave: [8:6]XOR[18:16]",
                         reg);
@@ -747,8 +752,9 @@ static void get_memory_layout(const struct mem_ctl_info *mci)
                         break;
                 tmp_mb = (limit + 1) >> 20;
 
-                debugf0("TAD#%d: up to %Lu.%03Lu GB (0x%016Lx), socket interleave %d, memory interleave %d, TGT: %d, %d, %d, %d, reg=0x%08x\n",
-                        n_tads, tmp_mb / 1000, tmp_mb % 1000,
+                mb = div_u64_rem(tmp_mb, 1000, &kb);
+                debugf0("TAD#%d: up to %u.%03u GB (0x%016Lx), socket interleave %d, memory interleave %d, TGT: %d, %d, %d, %d, reg=0x%08x\n",
+                        n_tads, mb, kb,
                         ((u64)tmp_mb) << 20L,
                         (u32)TAD_SOCK(reg),
                         (u32)TAD_CH(reg),
@@ -757,7 +763,7 @@ static void get_memory_layout(const struct mem_ctl_info *mci)
                         (u32)TAD_TGT2(reg),
                         (u32)TAD_TGT3(reg),
                         reg);
-                prv = tmp_mb;
+                prv = limit;
         }
 
         /*
@@ -771,9 +777,10 @@ static void get_memory_layout(const struct mem_ctl_info *mci)
                                               tad_ch_nilv_offset[j],
                                               &reg);
                         tmp_mb = TAD_OFFSET(reg) >> 20;
-                        debugf0("TAD CH#%d, offset #%d: %Lu.%03Lu GB (0x%016Lx), reg=0x%08x\n",
+                        mb = div_u64_rem(tmp_mb, 1000, &kb);
+                        debugf0("TAD CH#%d, offset #%d: %u.%03u GB (0x%016Lx), reg=0x%08x\n",
                                 i, j,
-                                tmp_mb / 1000, tmp_mb % 1000,
+                                mb, kb,
                                 ((u64)tmp_mb) << 20L,
                                 reg);
                 }
@@ -795,9 +802,10 @@ static void get_memory_layout(const struct mem_ctl_info *mci)
 
                         tmp_mb = RIR_LIMIT(reg) >> 20;
                         rir_way = 1 << RIR_WAY(reg);
-                        debugf0("CH#%d RIR#%d, limit: %Lu.%03Lu GB (0x%016Lx), way: %d, reg=0x%08x\n",
+                        mb = div_u64_rem(tmp_mb, 1000, &kb);
+                        debugf0("CH#%d RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d, reg=0x%08x\n",
                                 i, j,
-                                tmp_mb / 1000, tmp_mb % 1000,
+                                mb, kb,
                                 ((u64)tmp_mb) << 20L,
                                 rir_way,
                                 reg);
@@ -808,9 +816,10 @@ static void get_memory_layout(const struct mem_ctl_info *mci)
                                                       &reg);
                                 tmp_mb = RIR_OFFSET(reg) << 6;
 
-                                debugf0("CH#%d RIR#%d INTL#%d, offset %Lu.%03Lu GB (0x%016Lx), tgt: %d, reg=0x%08x\n",
+                                mb = div_u64_rem(tmp_mb, 1000, &kb);
+                                debugf0("CH#%d RIR#%d INTL#%d, offset %u.%03u GB (0x%016Lx), tgt: %d, reg=0x%08x\n",
                                         i, j, k,
-                                        tmp_mb / 1000, tmp_mb % 1000,
+                                        mb, kb,
                                         ((u64)tmp_mb) << 20L,
                                         (u32)RIR_RNK_TGT(reg),
                                         reg);
@@ -848,6 +857,7 @@ static int get_memory_error_data(struct mem_ctl_info *mci,
         u8                      ch_way,sck_way;
         u32                     tad_offset;
         u32                     rir_way;
+        u32                     mb, kb;
         u64                     ch_addr, offset, limit, prv = 0;
 
 
@@ -858,7 +868,7 @@ static int get_memory_error_data(struct mem_ctl_info *mci,
          * range (e. g. VGA addresses). It is unlikely, however, that the
          * memory controller would generate an error on that range.
          */
-        if ((addr > (u64) pvt->tolm) && (addr < (1L << 32))) {
+        if ((addr > (u64) pvt->tolm) && (addr < (1LL << 32))) {
                 sprintf(msg, "Error at TOLM area, on addr 0x%08Lx", addr);
                 edac_mc_handle_ce_no_info(mci, msg);
                 return -EINVAL;
@@ -913,7 +923,7 @@ static int get_memory_error_data(struct mem_ctl_info *mci,
                 addr,
                 limit,
                 sad_way + 7,
-                INTERLEAVE_MODE(reg) ? "" : "XOR[18:16]");
+                interleave_mode ? "" : "XOR[18:16]");
         if (interleave_mode)
                 idx = ((addr >> 6) ^ (addr >> 16)) & 7;
         else
@@ -1053,7 +1063,7 @@ static int get_memory_error_data(struct mem_ctl_info *mci,
         ch_addr = addr & 0x7f;
         /* Remove socket wayness and remove 6 bits */
         addr >>= 6;
-        addr /= sck_xch;
+        addr = div_u64(addr, sck_xch);
 #if 0
         /* Divide by channel way */
         addr = addr / ch_way;
@@ -1073,10 +1083,10 @@ static int get_memory_error_data(struct mem_ctl_info *mci,
                         continue;
 
                 limit = RIR_LIMIT(reg);
-
-                debugf0("RIR#%d, limit: %Lu.%03Lu GB (0x%016Lx), way: %d\n",
+                mb = div_u64_rem(limit >> 20, 1000, &kb);
+                debugf0("RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d\n",
                         n_rir,
-                        (limit >> 20) / 1000, (limit >> 20) % 1000,
+                        mb, kb,
                         limit,
                         1 << RIR_WAY(reg));
                 if  (ch_addr <= limit)
diff --git a/drivers/edac/tile_edac.c b/drivers/edac/tile_edac.c
index 1d5cf06f6c6b..e99d00976189 100644
--- a/drivers/edac/tile_edac.c
+++ b/drivers/edac/tile_edac.c
@@ -145,7 +145,11 @@ static int __devinit tile_edac_mc_probe(struct platform_device *pdev)
         mci->edac_ctl_cap = EDAC_FLAG_SECDED;
 
         mci->mod_name = DRV_NAME;
+#ifdef __tilegx__
+        mci->ctl_name = "TILEGx_Memory_Controller";
+#else
         mci->ctl_name = "TILEPro_Memory_Controller";
+#endif
         mci->dev_name = dev_name(&pdev->dev);
         mci->edac_check = tile_edac_check;
 
diff --git a/drivers/edac/x38_edac.c b/drivers/edac/x38_edac.c
index b6f47de152f3..a438297389e5 100644
--- a/drivers/edac/x38_edac.c
+++ b/drivers/edac/x38_edac.c
@@ -440,7 +440,7 @@ static void __devexit x38_remove_one(struct pci_dev *pdev)
         edac_mc_free(mci);
 }
 
-static const struct pci_device_id x38_pci_tbl[] __devinitdata = {
+static DEFINE_PCI_DEVICE_TABLE(x38_pci_tbl) = {
         {
          PCI_VEND_DEV(INTEL, X38_HB), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
          X38},