edac: i5100: cleanup

Some code cleanliness issues found by Andrew Morton (thanks!) which should
not affect functionality, but which should help make the code more
maintainable.

In particular, we now:

* convert all #define's w/ a parameter to static inlines
* use 1UL rather than 1ULL when calculating an unsigned long
* use pci_disable_device

The resulting code is tested and seems to work fine...

Signed-off-by: Arthur Jones <ajones@riverbed.com>
Cc: Doug Thompson <dougthompson@xmission.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>

1 files changed, 261 insertions, 135 deletions

diff --git a/drivers/edac/i5100_edac.c b/drivers/edac/i5100_edac.c
index d85e7992eb6a..22db05a67bfb 100644
--- a/drivers/edac/i5100_edac.c
+++ b/drivers/edac/i5100_edac.c
@@ -21,36 +21,19 @@
 
 #include "edac_core.h"
 
-/* register addresses and bit field accessors... */
+/* register addresses */
 
 /* device 16, func 1 */
 #define I5100_MC                0x40    /* Memory Control Register */
-#define         I5100_MC_ERRDETEN(a)    ((a) >> 5 & 1)
 #define I5100_MS                0x44    /* Memory Status Register */
 #define I5100_SPDDATA           0x48    /* Serial Presence Detect Status Reg */
-#define         I5100_SPDDATA_RDO(a)    ((a) >> 15 & 1)
-#define         I5100_SPDDATA_SBE(a)    ((a) >> 13 & 1)
-#define         I5100_SPDDATA_BUSY(a)   ((a) >> 12 & 1)
-#define         I5100_SPDDATA_DATA(a)   ((a)       & ((1 << 8) - 1))
 #define I5100_SPDCMD            0x4c    /* Serial Presence Detect Command Reg */
-#define         I5100_SPDCMD_DTI(a)     (((a) & ((1 << 4) - 1)) << 28)
-#define         I5100_SPDCMD_CKOVRD(a)  (((a) & 1)              << 27)
-#define         I5100_SPDCMD_SA(a)      (((a) & ((1 << 3) - 1)) << 24)
-#define         I5100_SPDCMD_BA(a)      (((a) & ((1 << 8) - 1)) << 16)
-#define         I5100_SPDCMD_DATA(a)    (((a) & ((1 << 8) - 1)) <<  8)
-#define         I5100_SPDCMD_CMD(a)     ((a) & 1)
 #define I5100_TOLM              0x6c    /* Top of Low Memory */
-#define         I5100_TOLM_TOLM(a)      ((a) >> 12 & ((1 << 4) - 1))
 #define I5100_MIR0              0x80    /* Memory Interleave Range 0 */
 #define I5100_MIR1              0x84    /* Memory Interleave Range 1 */
 #define I5100_AMIR_0            0x8c    /* Adjusted Memory Interleave Range 0 */
 #define I5100_AMIR_1            0x90    /* Adjusted Memory Interleave Range 1 */
-#define         I5100_MIR_LIMIT(a)      ((a) >> 4 & ((1 << 12) - 1))
-#define         I5100_MIR_WAY1(a)       ((a) >> 1 & 1)
-#define         I5100_MIR_WAY0(a)       ((a)      & 1)
 #define I5100_FERR_NF_MEM       0xa0    /* MC First Non Fatal Errors */
-#define         I5100_FERR_NF_MEM_CHAN_INDX(a)  ((a) >> 28 & 1)
-#define         I5100_FERR_NF_MEM_SPD_MASK      (1 << 18)
 #define         I5100_FERR_NF_MEM_M16ERR_MASK   (1 << 16)
 #define         I5100_FERR_NF_MEM_M15ERR_MASK   (1 << 15)
 #define         I5100_FERR_NF_MEM_M14ERR_MASK   (1 << 14)
@@ -72,47 +55,214 @@
                         I5100_FERR_NF_MEM_M5ERR_MASK | \
                         I5100_FERR_NF_MEM_M4ERR_MASK | \
                         I5100_FERR_NF_MEM_M1ERR_MASK)
-#define         I5100_FERR_NF_MEM_ANY(a)  ((a) & I5100_FERR_NF_MEM_ANY_MASK)
 #define I5100_NERR_NF_MEM       0xa4    /* MC Next Non-Fatal Errors */
-#define         I5100_NERR_NF_MEM_ANY(a)  I5100_FERR_NF_MEM_ANY(a)
 #define I5100_EMASK_MEM         0xa8    /* MC Error Mask Register */
 
 /* device 21 and 22, func 0 */
 #define I5100_MTR_0     0x154   /* Memory Technology Registers 0-3 */
 #define I5100_DMIR      0x15c   /* DIMM Interleave Range */
-#define         I5100_DMIR_LIMIT(a)     ((a) >> 16 & ((1 << 11) - 1))
-#define         I5100_DMIR_RANK(a, i)   ((a) >> (4 * i) & ((1 <<  2) - 1))
-#define I5100_MTR_4     0x1b0   /* Memory Technology Registers 4,5 */
-#define         I5100_MTR_PRESENT(a)    ((a) >> 10 & 1)
-#define         I5100_MTR_ETHROTTLE(a)  ((a) >>  9 & 1)
-#define         I5100_MTR_WIDTH(a)      ((a) >>  8 & 1)
-#define         I5100_MTR_NUMBANK(a)    ((a) >>  6 & 1)
-#define         I5100_MTR_NUMROW(a)     ((a) >>  2 & ((1 << 2) - 1))
-#define         I5100_MTR_NUMCOL(a)     ((a)       & ((1 << 2) - 1))
 #define I5100_VALIDLOG  0x18c   /* Valid Log Markers */
-#define         I5100_VALIDLOG_REDMEMVALID(a)   ((a) >> 2 & 1)
-#define         I5100_VALIDLOG_RECMEMVALID(a)   ((a) >> 1 & 1)
-#define         I5100_VALIDLOG_NRECMEMVALID(a)  ((a)      & 1)
 #define I5100_NRECMEMA  0x190   /* Non-Recoverable Memory Error Log Reg A */
-#define         I5100_NRECMEMA_MERR(a)          ((a) >> 15 & ((1 << 5) - 1))
-#define         I5100_NRECMEMA_BANK(a)          ((a) >> 12 & ((1 << 3) - 1))
-#define         I5100_NRECMEMA_RANK(a)          ((a) >>  8 & ((1 << 3) - 1))
-#define         I5100_NRECMEMA_DM_BUF_ID(a)     ((a)       & ((1 << 8) - 1))
 #define I5100_NRECMEMB  0x194   /* Non-Recoverable Memory Error Log Reg B */
-#define         I5100_NRECMEMB_CAS(a)           ((a) >> 16 & ((1 << 13) - 1))
-#define         I5100_NRECMEMB_RAS(a)           ((a)       & ((1 << 16) - 1))
 #define I5100_REDMEMA   0x198   /* Recoverable Memory Data Error Log Reg A */
-#define         I5100_REDMEMA_SYNDROME(a)       (a)
 #define I5100_REDMEMB   0x19c   /* Recoverable Memory Data Error Log Reg B */
-#define         I5100_REDMEMB_ECC_LOCATOR(a)    ((a) & ((1 << 18) - 1))
 #define I5100_RECMEMA   0x1a0   /* Recoverable Memory Error Log Reg A */
-#define         I5100_RECMEMA_MERR(a)           I5100_NRECMEMA_MERR(a)
-#define         I5100_RECMEMA_BANK(a)           I5100_NRECMEMA_BANK(a)
-#define         I5100_RECMEMA_RANK(a)           I5100_NRECMEMA_RANK(a)
-#define         I5100_RECMEMA_DM_BUF_ID(a)      I5100_NRECMEMA_DM_BUF_ID(a)
 #define I5100_RECMEMB   0x1a4   /* Recoverable Memory Error Log Reg B */
-#define         I5100_RECMEMB_CAS(a)            I5100_NRECMEMB_CAS(a)
-#define         I5100_RECMEMB_RAS(a)            I5100_NRECMEMB_RAS(a)
+#define I5100_MTR_4     0x1b0   /* Memory Technology Registers 4,5 */
+
+/* bit field accessors */
+
+static inline u32 i5100_mc_errdeten(u32 mc)
+{
+        return mc >> 5 & 1;
+}
+
+static inline u16 i5100_spddata_rdo(u16 a)
+{
+        return a >> 15 & 1;
+}
+
+static inline u16 i5100_spddata_sbe(u16 a)
+{
+        return a >> 13 & 1;
+}
+
+static inline u16 i5100_spddata_busy(u16 a)
+{
+        return a >> 12 & 1;
+}
+
+static inline u16 i5100_spddata_data(u16 a)
+{
+        return a & ((1 << 8) - 1);
+}
+
+static inline u32 i5100_spdcmd_create(u32 dti, u32 ckovrd, u32 sa, u32 ba,
+                                      u32 data, u32 cmd)
+{
+        return  ((dti & ((1 << 4) - 1))  << 28) |
+                ((ckovrd & 1)            << 27) |
+                ((sa & ((1 << 3) - 1))   << 24) |
+                ((ba & ((1 << 8) - 1))   << 16) |
+                ((data & ((1 << 8) - 1)) <<  8) |
+                (cmd & 1);
+}
+
+static inline u16 i5100_tolm_tolm(u16 a)
+{
+        return a >> 12 & ((1 << 4) - 1);
+}
+
+static inline u16 i5100_mir_limit(u16 a)
+{
+        return a >> 4 & ((1 << 12) - 1);
+}
+
+static inline u16 i5100_mir_way1(u16 a)
+{
+        return a >> 1 & 1;
+}
+
+static inline u16 i5100_mir_way0(u16 a)
+{
+        return a & 1;
+}
+
+static inline u32 i5100_ferr_nf_mem_chan_indx(u32 a)
+{
+        return a >> 28 & 1;
+}
+
+static inline u32 i5100_ferr_nf_mem_any(u32 a)
+{
+        return a & I5100_FERR_NF_MEM_ANY_MASK;
+}
+
+static inline u32 i5100_nerr_nf_mem_any(u32 a)
+{
+        return i5100_ferr_nf_mem_any(a);
+}
+
+static inline u32 i5100_dmir_limit(u32 a)
+{
+        return a >> 16 & ((1 << 11) - 1);
+}
+
+static inline u32 i5100_dmir_rank(u32 a, u32 i)
+{
+        return a >> (4 * i) & ((1 << 2) - 1);