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authorArthur Jones <ajones@riverbed.com>2008-07-25 04:49:08 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2008-07-25 13:53:48 -0400
commitb238e57723a6fb2c365fc35de5d7c48ccf9300cd (patch)
tree5dd7fc42abedd6c5168b3f375b5a67de69305e9d /drivers/edac
parent178d5a742291976d13bff55fa2b130879d4510de (diff)
edac: i5100: cleanup
Some code cleanliness issues found by Andrew Morton (thanks!) which should not affect functionality, but which should help make the code more maintainable. In particular, we now: * convert all #define's w/ a parameter to static inlines * use 1UL rather than 1ULL when calculating an unsigned long * use pci_disable_device The resulting code is tested and seems to work fine... Signed-off-by: Arthur Jones <ajones@riverbed.com> Cc: Doug Thompson <dougthompson@xmission.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'drivers/edac')
-rw-r--r--drivers/edac/i5100_edac.c396
1 files changed, 261 insertions, 135 deletions
diff --git a/drivers/edac/i5100_edac.c b/drivers/edac/i5100_edac.c
index d85e7992eb6a..22db05a67bfb 100644
--- a/drivers/edac/i5100_edac.c
+++ b/drivers/edac/i5100_edac.c
@@ -21,36 +21,19 @@
21 21
22#include "edac_core.h" 22#include "edac_core.h"
23 23
24/* register addresses and bit field accessors... */ 24/* register addresses */
25 25
26/* device 16, func 1 */ 26/* device 16, func 1 */
27#define I5100_MC 0x40 /* Memory Control Register */ 27#define I5100_MC 0x40 /* Memory Control Register */
28#define I5100_MC_ERRDETEN(a) ((a) >> 5 & 1)
29#define I5100_MS 0x44 /* Memory Status Register */ 28#define I5100_MS 0x44 /* Memory Status Register */
30#define I5100_SPDDATA 0x48 /* Serial Presence Detect Status Reg */ 29#define I5100_SPDDATA 0x48 /* Serial Presence Detect Status Reg */
31#define I5100_SPDDATA_RDO(a) ((a) >> 15 & 1)
32#define I5100_SPDDATA_SBE(a) ((a) >> 13 & 1)
33#define I5100_SPDDATA_BUSY(a) ((a) >> 12 & 1)
34#define I5100_SPDDATA_DATA(a) ((a) & ((1 << 8) - 1))
35#define I5100_SPDCMD 0x4c /* Serial Presence Detect Command Reg */ 30#define I5100_SPDCMD 0x4c /* Serial Presence Detect Command Reg */
36#define I5100_SPDCMD_DTI(a) (((a) & ((1 << 4) - 1)) << 28)
37#define I5100_SPDCMD_CKOVRD(a) (((a) & 1) << 27)
38#define I5100_SPDCMD_SA(a) (((a) & ((1 << 3) - 1)) << 24)
39#define I5100_SPDCMD_BA(a) (((a) & ((1 << 8) - 1)) << 16)
40#define I5100_SPDCMD_DATA(a) (((a) & ((1 << 8) - 1)) << 8)
41#define I5100_SPDCMD_CMD(a) ((a) & 1)
42#define I5100_TOLM 0x6c /* Top of Low Memory */ 31#define I5100_TOLM 0x6c /* Top of Low Memory */
43#define I5100_TOLM_TOLM(a) ((a) >> 12 & ((1 << 4) - 1))
44#define I5100_MIR0 0x80 /* Memory Interleave Range 0 */ 32#define I5100_MIR0 0x80 /* Memory Interleave Range 0 */
45#define I5100_MIR1 0x84 /* Memory Interleave Range 1 */ 33#define I5100_MIR1 0x84 /* Memory Interleave Range 1 */
46#define I5100_AMIR_0 0x8c /* Adjusted Memory Interleave Range 0 */ 34#define I5100_AMIR_0 0x8c /* Adjusted Memory Interleave Range 0 */
47#define I5100_AMIR_1 0x90 /* Adjusted Memory Interleave Range 1 */ 35#define I5100_AMIR_1 0x90 /* Adjusted Memory Interleave Range 1 */
48#define I5100_MIR_LIMIT(a) ((a) >> 4 & ((1 << 12) - 1))
49#define I5100_MIR_WAY1(a) ((a) >> 1 & 1)
50#define I5100_MIR_WAY0(a) ((a) & 1)
51#define I5100_FERR_NF_MEM 0xa0 /* MC First Non Fatal Errors */ 36#define I5100_FERR_NF_MEM 0xa0 /* MC First Non Fatal Errors */
52#define I5100_FERR_NF_MEM_CHAN_INDX(a) ((a) >> 28 & 1)
53#define I5100_FERR_NF_MEM_SPD_MASK (1 << 18)
54#define I5100_FERR_NF_MEM_M16ERR_MASK (1 << 16) 37#define I5100_FERR_NF_MEM_M16ERR_MASK (1 << 16)
55#define I5100_FERR_NF_MEM_M15ERR_MASK (1 << 15) 38#define I5100_FERR_NF_MEM_M15ERR_MASK (1 << 15)
56#define I5100_FERR_NF_MEM_M14ERR_MASK (1 << 14) 39#define I5100_FERR_NF_MEM_M14ERR_MASK (1 << 14)
@@ -72,47 +55,214 @@
72 I5100_FERR_NF_MEM_M5ERR_MASK | \ 55 I5100_FERR_NF_MEM_M5ERR_MASK | \
73 I5100_FERR_NF_MEM_M4ERR_MASK | \ 56 I5100_FERR_NF_MEM_M4ERR_MASK | \
74 I5100_FERR_NF_MEM_M1ERR_MASK) 57 I5100_FERR_NF_MEM_M1ERR_MASK)
75#define I5100_FERR_NF_MEM_ANY(a) ((a) & I5100_FERR_NF_MEM_ANY_MASK)
76#define I5100_NERR_NF_MEM 0xa4 /* MC Next Non-Fatal Errors */ 58#define I5100_NERR_NF_MEM 0xa4 /* MC Next Non-Fatal Errors */
77#define I5100_NERR_NF_MEM_ANY(a) I5100_FERR_NF_MEM_ANY(a)
78#define I5100_EMASK_MEM 0xa8 /* MC Error Mask Register */ 59#define I5100_EMASK_MEM 0xa8 /* MC Error Mask Register */
79 60
80/* device 21 and 22, func 0 */ 61/* device 21 and 22, func 0 */
81#define I5100_MTR_0 0x154 /* Memory Technology Registers 0-3 */ 62#define I5100_MTR_0 0x154 /* Memory Technology Registers 0-3 */
82#define I5100_DMIR 0x15c /* DIMM Interleave Range */ 63#define I5100_DMIR 0x15c /* DIMM Interleave Range */
83#define I5100_DMIR_LIMIT(a) ((a) >> 16 & ((1 << 11) - 1))
84#define I5100_DMIR_RANK(a, i) ((a) >> (4 * i) & ((1 << 2) - 1))
85#define I5100_MTR_4 0x1b0 /* Memory Technology Registers 4,5 */
86#define I5100_MTR_PRESENT(a) ((a) >> 10 & 1)
87#define I5100_MTR_ETHROTTLE(a) ((a) >> 9 & 1)
88#define I5100_MTR_WIDTH(a) ((a) >> 8 & 1)
89#define I5100_MTR_NUMBANK(a) ((a) >> 6 & 1)
90#define I5100_MTR_NUMROW(a) ((a) >> 2 & ((1 << 2) - 1))
91#define I5100_MTR_NUMCOL(a) ((a) & ((1 << 2) - 1))
92#define I5100_VALIDLOG 0x18c /* Valid Log Markers */ 64#define I5100_VALIDLOG 0x18c /* Valid Log Markers */
93#define I5100_VALIDLOG_REDMEMVALID(a) ((a) >> 2 & 1)
94#define I5100_VALIDLOG_RECMEMVALID(a) ((a) >> 1 & 1)
95#define I5100_VALIDLOG_NRECMEMVALID(a) ((a) & 1)
96#define I5100_NRECMEMA 0x190 /* Non-Recoverable Memory Error Log Reg A */ 65#define I5100_NRECMEMA 0x190 /* Non-Recoverable Memory Error Log Reg A */
97#define I5100_NRECMEMA_MERR(a) ((a) >> 15 & ((1 << 5) - 1))
98#define I5100_NRECMEMA_BANK(a) ((a) >> 12 & ((1 << 3) - 1))
99#define I5100_NRECMEMA_RANK(a) ((a) >> 8 & ((1 << 3) - 1))
100#define I5100_NRECMEMA_DM_BUF_ID(a) ((a) & ((1 << 8) - 1))
101#define I5100_NRECMEMB 0x194 /* Non-Recoverable Memory Error Log Reg B */ 66#define I5100_NRECMEMB 0x194 /* Non-Recoverable Memory Error Log Reg B */
102#define I5100_NRECMEMB_CAS(a) ((a) >> 16 & ((1 << 13) - 1))
103#define I5100_NRECMEMB_RAS(a) ((a) & ((1 << 16) - 1))
104#define I5100_REDMEMA 0x198 /* Recoverable Memory Data Error Log Reg A */ 67#define I5100_REDMEMA 0x198 /* Recoverable Memory Data Error Log Reg A */
105#define I5100_REDMEMA_SYNDROME(a) (a)
106#define I5100_REDMEMB 0x19c /* Recoverable Memory Data Error Log Reg B */ 68#define I5100_REDMEMB 0x19c /* Recoverable Memory Data Error Log Reg B */
107#define I5100_REDMEMB_ECC_LOCATOR(a) ((a) & ((1 << 18) - 1))
108#define I5100_RECMEMA 0x1a0 /* Recoverable Memory Error Log Reg A */ 69#define I5100_RECMEMA 0x1a0 /* Recoverable Memory Error Log Reg A */
109#define I5100_RECMEMA_MERR(a) I5100_NRECMEMA_MERR(a)
110#define I5100_RECMEMA_BANK(a) I5100_NRECMEMA_BANK(a)
111#define I5100_RECMEMA_RANK(a) I5100_NRECMEMA_RANK(a)
112#define I5100_RECMEMA_DM_BUF_ID(a) I5100_NRECMEMA_DM_BUF_ID(a)
113#define I5100_RECMEMB 0x1a4 /* Recoverable Memory Error Log Reg B */ 70#define I5100_RECMEMB 0x1a4 /* Recoverable Memory Error Log Reg B */
114#define I5100_RECMEMB_CAS(a) I5100_NRECMEMB_CAS(a) 71#define I5100_MTR_4 0x1b0 /* Memory Technology Registers 4,5 */
115#define I5100_RECMEMB_RAS(a) I5100_NRECMEMB_RAS(a) 72
73/* bit field accessors */
74
75static inline u32 i5100_mc_errdeten(u32 mc)
76{
77 return mc >> 5 & 1;
78}
79
80static inline u16 i5100_spddata_rdo(u16 a)
81{
82 return a >> 15 & 1;
83}
84
85static inline u16 i5100_spddata_sbe(u16 a)
86{
87 return a >> 13 & 1;
88}
89
90static inline u16 i5100_spddata_busy(u16 a)
91{
92 return a >> 12 & 1;
93}
94
95static inline u16 i5100_spddata_data(u16 a)
96{
97 return a & ((1 << 8) - 1);
98}
99
100static inline u32 i5100_spdcmd_create(u32 dti, u32 ckovrd, u32 sa, u32 ba,
101 u32 data, u32 cmd)
102{
103 return ((dti & ((1 << 4) - 1)) << 28) |
104 ((ckovrd & 1) << 27) |
105 ((sa & ((1 << 3) - 1)) << 24) |
106 ((ba & ((1 << 8) - 1)) << 16) |
107 ((data & ((1 << 8) - 1)) << 8) |
108 (cmd & 1);
109}
110
111static inline u16 i5100_tolm_tolm(u16 a)
112{
113 return a >> 12 & ((1 << 4) - 1);
114}
115
116static inline u16 i5100_mir_limit(u16 a)
117{
118 return a >> 4 & ((1 << 12) - 1);
119}
120
121static inline u16 i5100_mir_way1(u16 a)
122{
123 return a >> 1 & 1;
124}
125
126static inline u16 i5100_mir_way0(u16 a)
127{
128 return a & 1;
129}
130
131static inline u32 i5100_ferr_nf_mem_chan_indx(u32 a)
132{
133 return a >> 28 & 1;
134}
135
136static inline u32 i5100_ferr_nf_mem_any(u32 a)
137{
138 return a & I5100_FERR_NF_MEM_ANY_MASK;
139}
140
141static inline u32 i5100_nerr_nf_mem_any(u32 a)
142{
143 return i5100_ferr_nf_mem_any(a);
144}
145
146static inline u32 i5100_dmir_limit(u32 a)
147{
148 return a >> 16 & ((1 << 11) - 1);
149}
150
151static inline u32 i5100_dmir_rank(u32 a, u32 i)
152{
153 return a >> (4 * i) & ((1 << 2) - 1);
154}
155
156static inline u16 i5100_mtr_present(u16 a)
157{
158 return a >> 10 & 1;
159}
160
161static inline u16 i5100_mtr_ethrottle(u16 a)
162{
163 return a >> 9 & 1;
164}
165
166static inline u16 i5100_mtr_width(u16 a)
167{
168 return a >> 8 & 1;
169}
170
171static inline u16 i5100_mtr_numbank(u16 a)
172{
173 return a >> 6 & 1;
174}
175
176static inline u16 i5100_mtr_numrow(u16 a)
177{
178 return a >> 2 & ((1 << 2) - 1);
179}
180
181static inline u16 i5100_mtr_numcol(u16 a)
182{
183 return a & ((1 << 2) - 1);
184}
185
186
187static inline u32 i5100_validlog_redmemvalid(u32 a)
188{
189 return a >> 2 & 1;
190}
191
192static inline u32 i5100_validlog_recmemvalid(u32 a)
193{
194 return a >> 1 & 1;
195}
196
197static inline u32 i5100_validlog_nrecmemvalid(u32 a)
198{
199 return a & 1;
200}
201
202static inline u32 i5100_nrecmema_merr(u32 a)
203{
204 return a >> 15 & ((1 << 5) - 1);
205}
206
207static inline u32 i5100_nrecmema_bank(u32 a)
208{
209 return a >> 12 & ((1 << 3) - 1);
210}
211
212static inline u32 i5100_nrecmema_rank(u32 a)
213{
214 return a >> 8 & ((1 << 3) - 1);
215}
216
217static inline u32 i5100_nrecmema_dm_buf_id(u32 a)
218{
219 return a & ((1 << 8) - 1);
220}
221
222static inline u32 i5100_nrecmemb_cas(u32 a)
223{
224 return a >> 16 & ((1 << 13) - 1);
225}
226
227static inline u32 i5100_nrecmemb_ras(u32 a)
228{
229 return a & ((1 << 16) - 1);
230}
231
232static inline u32 i5100_redmemb_ecc_locator(u32 a)
233{
234 return a & ((1 << 18) - 1);
235}
236
237static inline u32 i5100_recmema_merr(u32 a)
238{
239 return i5100_nrecmema_merr(a);
240}
241
242static inline u32 i5100_recmema_bank(u32 a)
243{
244 return i5100_nrecmema_bank(a);
245}
246
247static inline u32 i5100_recmema_rank(u32 a)
248{
249 return i5100_nrecmema_rank(a);
250}
251
252static inline u32 i5100_recmema_dm_buf_id(u32 a)
253{
254 return i5100_nrecmema_dm_buf_id(a);
255}
256
257static inline u32 i5100_recmemb_cas(u32 a)
258{
259 return i5100_nrecmemb_cas(a);
260}
261
262static inline u32 i5100_recmemb_ras(u32 a)
263{
264 return i5100_nrecmemb_ras(a);
265}
116 266
117/* some generic limits */ 267/* some generic limits */
118#define I5100_MAX_RANKS_PER_CTLR 6 268#define I5100_MAX_RANKS_PER_CTLR 6
@@ -189,42 +339,9 @@ static int i5100_rank_to_slot(const struct mem_ctl_info *mci,
189 return -1; 339 return -1;
190} 340}
191 341
192/*
193 * The processor bus memory addresses are broken into three
194 * pieces, whereas the controller addresses are contiguous.
195 *
196 * here we map from the controller address space to the
197 * processor address space:
198 *
199 * Processor Address Space
200 * +-----------------------------+
201 * | |
202 * | "high" memory addresses |
203 * | |
204 * +-----------------------------+ <- 4GB on the i5100
205 * | |
206 * | other non-memory addresses |
207 * | |
208 * +-----------------------------+ <- top of low memory
209 * | |
210 * | "low" memory addresses |
211 * | |
212 * +-----------------------------+
213 */
214static unsigned long i5100_ctl_page_to_phys(struct mem_ctl_info *mci,
215 unsigned long cntlr_addr)
216{
217 const struct i5100_priv *priv = mci->pvt_info;
218
219 if (cntlr_addr < priv->tolm)
220 return cntlr_addr;
221
222 return (1ULL << 32) + (cntlr_addr - priv->tolm);
223}
224
225static const char *i5100_err_msg(unsigned err) 342static const char *i5100_err_msg(unsigned err)
226{ 343{
227 const char *merrs[] = { 344 static const char *merrs[] = {
228 "unknown", /* 0 */ 345 "unknown", /* 0 */
229 "uncorrectable data ECC on replay", /* 1 */ 346 "uncorrectable data ECC on replay", /* 1 */
230 "unknown", /* 2 */ 347 "unknown", /* 2 */
@@ -341,24 +458,24 @@ static void i5100_read_log(struct mem_ctl_info *mci, int ctlr,
341 458
342 pci_read_config_dword(pdev, I5100_VALIDLOG, &dw); 459 pci_read_config_dword(pdev, I5100_VALIDLOG, &dw);
343 460
344 if (I5100_VALIDLOG_REDMEMVALID(dw)) { 461 if (i5100_validlog_redmemvalid(dw)) {
345 pci_read_config_dword(pdev, I5100_REDMEMA, &dw2); 462 pci_read_config_dword(pdev, I5100_REDMEMA, &dw2);
346 syndrome = I5100_REDMEMA_SYNDROME(dw2); 463 syndrome = dw2;
347 pci_read_config_dword(pdev, I5100_REDMEMB, &dw2); 464 pci_read_config_dword(pdev, I5100_REDMEMB, &dw2);
348 ecc_loc = I5100_REDMEMB_ECC_LOCATOR(dw2); 465 ecc_loc = i5100_redmemb_ecc_locator(dw2);
349 } 466 }
350 467
351 if (I5100_VALIDLOG_RECMEMVALID(dw)) { 468 if (i5100_validlog_recmemvalid(dw)) {
352 const char *msg; 469 const char *msg;
353 470
354 pci_read_config_dword(pdev, I5100_RECMEMA, &dw2); 471 pci_read_config_dword(pdev, I5100_RECMEMA, &dw2);
355 merr = I5100_RECMEMA_MERR(dw2); 472 merr = i5100_recmema_merr(dw2);
356 bank = I5100_RECMEMA_BANK(dw2); 473 bank = i5100_recmema_bank(dw2);
357 rank = I5100_RECMEMA_RANK(dw2); 474 rank = i5100_recmema_rank(dw2);
358 475
359 pci_read_config_dword(pdev, I5100_RECMEMB, &dw2); 476 pci_read_config_dword(pdev, I5100_RECMEMB, &dw2);
360 cas = I5100_RECMEMB_CAS(dw2); 477 cas = i5100_recmemb_cas(dw2);
361 ras = I5100_RECMEMB_RAS(dw2); 478 ras = i5100_recmemb_ras(dw2);
362 479
363 /* FIXME: not really sure if this is what merr is... 480 /* FIXME: not really sure if this is what merr is...
364 */ 481 */
@@ -370,17 +487,17 @@ static void i5100_read_log(struct mem_ctl_info *mci, int ctlr,
370 i5100_handle_ce(mci, ctlr, bank, rank, syndrome, cas, ras, msg); 487 i5100_handle_ce(mci, ctlr, bank, rank, syndrome, cas, ras, msg);
371 } 488 }
372 489
373 if (I5100_VALIDLOG_NRECMEMVALID(dw)) { 490 if (i5100_validlog_nrecmemvalid(dw)) {
374 const char *msg; 491 const char *msg;
375 492
376 pci_read_config_dword(pdev, I5100_NRECMEMA, &dw2); 493 pci_read_config_dword(pdev, I5100_NRECMEMA, &dw2);
377 merr = I5100_NRECMEMA_MERR(dw2); 494 merr = i5100_nrecmema_merr(dw2);
378 bank = I5100_NRECMEMA_BANK(dw2); 495 bank = i5100_nrecmema_bank(dw2);
379 rank = I5100_NRECMEMA_RANK(dw2); 496 rank = i5100_nrecmema_rank(dw2);
380 497
381 pci_read_config_dword(pdev, I5100_NRECMEMB, &dw2); 498 pci_read_config_dword(pdev, I5100_NRECMEMB, &dw2);
382 cas = I5100_NRECMEMB_CAS(dw2); 499 cas = i5100_nrecmemb_cas(dw2);
383 ras = I5100_NRECMEMB_RAS(dw2); 500 ras = i5100_nrecmemb_ras(dw2);
384 501
385 /* FIXME: not really sure if this is what merr is... 502 /* FIXME: not really sure if this is what merr is...
386 */ 503 */
@@ -402,7 +519,7 @@ static void i5100_check_error(struct mem_ctl_info *mci)
402 519
403 520
404 pci_read_config_dword(priv->mc, I5100_FERR_NF_MEM, &dw); 521 pci_read_config_dword(priv->mc, I5100_FERR_NF_MEM, &dw);
405 if (I5100_FERR_NF_MEM_ANY(dw)) { 522 if (i5100_ferr_nf_mem_any(dw)) {
406 u32 dw2; 523 u32 dw2;
407 524
408 pci_read_config_dword(priv->mc, I5100_NERR_NF_MEM, &dw2); 525 pci_read_config_dword(priv->mc, I5100_NERR_NF_MEM, &dw2);
@@ -411,9 +528,9 @@ static void i5100_check_error(struct mem_ctl_info *mci)
411 dw2); 528 dw2);
412 pci_write_config_dword(priv->mc, I5100_FERR_NF_MEM, dw); 529 pci_write_config_dword(priv->mc, I5100_FERR_NF_MEM, dw);
413 530
414 i5100_read_log(mci, I5100_FERR_NF_MEM_CHAN_INDX(dw), 531 i5100_read_log(mci, i5100_ferr_nf_mem_chan_indx(dw),
415 I5100_FERR_NF_MEM_ANY(dw), 532 i5100_ferr_nf_mem_any(dw),
416 I5100_NERR_NF_MEM_ANY(dw2)); 533 i5100_nerr_nf_mem_any(dw2));
417 } 534 }
418} 535}
419 536
@@ -476,12 +593,12 @@ static void __devinit i5100_init_mtr(struct mem_ctl_info *mci)
476 593
477 pci_read_config_word(pdev, addr, &w); 594 pci_read_config_word(pdev, addr, &w);
478 595
479 priv->mtr[i][j].present = I5100_MTR_PRESENT(w); 596 priv->mtr[i][j].present = i5100_mtr_present(w);
480 priv->mtr[i][j].ethrottle = I5100_MTR_ETHROTTLE(w); 597 priv->mtr[i][j].ethrottle = i5100_mtr_ethrottle(w);
481 priv->mtr[i][j].width = 4 + 4 * I5100_MTR_WIDTH(w); 598 priv->mtr[i][j].width = 4 + 4 * i5100_mtr_width(w);
482 priv->mtr[i][j].numbank = 2 + I5100_MTR_NUMBANK(w); 599 priv->mtr[i][j].numbank = 2 + i5100_mtr_numbank(w);
483 priv->mtr[i][j].numrow = 13 + I5100_MTR_NUMROW(w); 600 priv->mtr[i][j].numrow = 13 + i5100_mtr_numrow(w);
484 priv->mtr[i][j].numcol = 10 + I5100_MTR_NUMCOL(w); 601 priv->mtr[i][j].numcol = 10 + i5100_mtr_numcol(w);
485 } 602 }
486 } 603 }
487} 604}
@@ -495,35 +612,30 @@ static int i5100_read_spd_byte(const struct mem_ctl_info *mci,
495{ 612{
496 struct i5100_priv *priv = mci->pvt_info; 613 struct i5100_priv *priv = mci->pvt_info;
497 u16 w; 614 u16 w;
498 u32 dw;
499 unsigned long et; 615 unsigned long et;
500 616
501 pci_read_config_word(priv->mc, I5100_SPDDATA, &w); 617 pci_read_config_word(priv->mc, I5100_SPDDATA, &w);
502 if (I5100_SPDDATA_BUSY(w)) 618 if (i5100_spddata_busy(w))
503 return -1; 619 return -1;
504 620
505 dw = I5100_SPDCMD_DTI(0xa) | 621 pci_write_config_dword(priv->mc, I5100_SPDCMD,
506 I5100_SPDCMD_CKOVRD(1) | 622 i5100_spdcmd_create(0xa, 1, ch * 4 + slot, addr,
507 I5100_SPDCMD_SA(ch * 4 + slot) | 623 0, 0));
508 I5100_SPDCMD_BA(addr) |
509 I5100_SPDCMD_DATA(0) |
510 I5100_SPDCMD_CMD(0);
511 pci_write_config_dword(priv->mc, I5100_SPDCMD, dw);
512 624
513 /* wait up to 100ms */ 625 /* wait up to 100ms */
514 et = jiffies + HZ / 10; 626 et = jiffies + HZ / 10;
515 udelay(100); 627 udelay(100);
516 while (1) { 628 while (1) {
517 pci_read_config_word(priv->mc, I5100_SPDDATA, &w); 629 pci_read_config_word(priv->mc, I5100_SPDDATA, &w);
518 if (!I5100_SPDDATA_BUSY(w)) 630 if (!i5100_spddata_busy(w))
519 break; 631 break;
520 udelay(100); 632 udelay(100);
521 } 633 }
522 634
523 if (!I5100_SPDDATA_RDO(w) || I5100_SPDDATA_SBE(w)) 635 if (!i5100_spddata_rdo(w) || i5100_spddata_sbe(w))
524 return -1; 636 return -1;
525 637
526 *byte = I5100_SPDDATA_DATA(w); 638 *byte = i5100_spddata_data(w);
527 639
528 return 0; 640 return 0;
529} 641}
@@ -591,17 +703,17 @@ static void __devinit i5100_init_interleaving(struct pci_dev *pdev,
591 int i; 703 int i;
592 704
593 pci_read_config_word(pdev, I5100_TOLM, &w); 705 pci_read_config_word(pdev, I5100_TOLM, &w);
594 priv->tolm = (u64) I5100_TOLM_TOLM(w) * 256 * 1024 * 1024; 706 priv->tolm = (u64) i5100_tolm_tolm(w) * 256 * 1024 * 1024;
595 707
596 pci_read_config_word(pdev, I5100_MIR0, &w); 708 pci_read_config_word(pdev, I5100_MIR0, &w);
597 priv->mir[0].limit = (u64) I5100_MIR_LIMIT(w) << 28; 709 priv->mir[0].limit = (u64) i5100_mir_limit(w) << 28;
598 priv->mir[0].way[1] = I5100_MIR_WAY1(w); 710 priv->mir[0].way[1] = i5100_mir_way1(w);
599 priv->mir[0].way[0] = I5100_MIR_WAY0(w); 711 priv->mir[0].way[0] = i5100_mir_way0(w);
600 712
601 pci_read_config_word(pdev, I5100_MIR1, &w); 713 pci_read_config_word(pdev, I5100_MIR1, &w);
602 priv->mir[1].limit = (u64) I5100_MIR_LIMIT(w) << 28; 714 priv->mir[1].limit = (u64) i5100_mir_limit(w) << 28;
603 priv->mir[1].way[1] = I5100_MIR_WAY1(w); 715 priv->mir[1].way[1] = i5100_mir_way1(w);
604 priv->mir[1].way[0] = I5100_MIR_WAY0(w); 716 priv->mir[1].way[0] = i5100_mir_way0(w);
605 717
606 pci_read_config_word(pdev, I5100_AMIR_0, &w); 718 pci_read_config_word(pdev, I5100_AMIR_0, &w);
607 priv->amir[0] = w; 719 priv->amir[0] = w;
@@ -617,10 +729,10 @@ static void __devinit i5100_init_interleaving(struct pci_dev *pdev,
617 pci_read_config_dword(mms[i], I5100_DMIR + j * 4, &dw); 729 pci_read_config_dword(mms[i], I5100_DMIR + j * 4, &dw);
618 730
619 priv->dmir[i][j].limit = 731 priv->dmir[i][j].limit =
620 (u64) I5100_DMIR_LIMIT(dw) << 28; 732 (u64) i5100_dmir_limit(dw) << 28;
621 for (k = 0; k < I5100_MAX_RANKS_PER_DIMM; k++) 733 for (k = 0; k < I5100_MAX_RANKS_PER_DIMM; k++)
622 priv->dmir[i][j].rank[k] = 734 priv->dmir[i][j].rank[k] =
623 I5100_DMIR_RANK(dw, k); 735 i5100_dmir_rank(dw, k);
624 } 736 }
625 } 737 }
626 738
@@ -693,10 +805,10 @@ static int __devinit i5100_init_one(struct pci_dev *pdev,
693 805
694 /* ECC enabled? */ 806 /* ECC enabled? */
695 pci_read_config_dword(pdev, I5100_MC, &dw); 807 pci_read_config_dword(pdev, I5100_MC, &dw);
696 if (!I5100_MC_ERRDETEN(dw)) { 808 if (!i5100_mc_errdeten(dw)) {
697 printk(KERN_INFO "i5100_edac: ECC not enabled.\n"); 809 printk(KERN_INFO "i5100_edac: ECC not enabled.\n");
698 ret = -ENODEV; 810 ret = -ENODEV;
699 goto bail; 811 goto bail_pdev;
700 } 812 }
701 813
702 /* figure out how many ranks, from strapped state of 48GB_Mode input */ 814 /* figure out how many ranks, from strapped state of 48GB_Mode input */
@@ -707,7 +819,7 @@ static int __devinit i5100_init_one(struct pci_dev *pdev,
707 /* FIXME: get 6 ranks / controller to work - need hw... */ 819 /* FIXME: get 6 ranks / controller to work - need hw... */
708 printk(KERN_INFO "i5100_edac: unsupported configuration.\n"); 820 printk(KERN_INFO "i5100_edac: unsupported configuration.\n");
709 ret = -ENODEV; 821 ret = -ENODEV;
710 goto bail; 822 goto bail_pdev;
711 } 823 }
712 824
713 /* enable error reporting... */ 825 /* enable error reporting... */
@@ -718,8 +830,10 @@ static int __devinit i5100_init_one(struct pci_dev *pdev,
718 /* device 21, func 0, Channel 0 Memory Map, Error Flag/Mask, etc... */ 830 /* device 21, func 0, Channel 0 Memory Map, Error Flag/Mask, etc... */
719 ch0mm = pci_get_device_func(PCI_VENDOR_ID_INTEL, 831 ch0mm = pci_get_device_func(PCI_VENDOR_ID_INTEL,
720 PCI_DEVICE_ID_INTEL_5100_21, 0); 832 PCI_DEVICE_ID_INTEL_5100_21, 0);
721 if (!ch0mm) 833 if (!ch0mm) {
722 return -ENODEV; 834 ret = -ENODEV;
835 goto bail_pdev;
836 }
723 837
724 rc = pci_enable_device(ch0mm); 838 rc = pci_enable_device(ch0mm);
725 if (rc < 0) { 839 if (rc < 0) {
@@ -732,7 +846,7 @@ static int __devinit i5100_init_one(struct pci_dev *pdev,
732 PCI_DEVICE_ID_INTEL_5100_22, 0); 846 PCI_DEVICE_ID_INTEL_5100_22, 0);
733 if (!ch1mm) { 847 if (!ch1mm) {
734 ret = -ENODEV; 848 ret = -ENODEV;
735 goto bail_ch0; 849 goto bail_disable_ch0;
736 } 850 }
737 851
738 rc = pci_enable_device(ch1mm); 852 rc = pci_enable_device(ch1mm);
@@ -744,7 +858,7 @@ static int __devinit i5100_init_one(struct pci_dev *pdev,
744 mci = edac_mc_alloc(sizeof(*priv), ranksperch * 2, 1, 0); 858 mci = edac_mc_alloc(sizeof(*priv), ranksperch * 2, 1, 0);
745 if (!mci) { 859 if (!mci) {
746 ret = -ENOMEM; 860 ret = -ENOMEM;
747 goto bail_ch1; 861 goto bail_disable_ch1;
748 } 862 }
749 863
750 mci->dev = &pdev->dev; 864 mci->dev = &pdev->dev;
@@ -765,7 +879,7 @@ static int __devinit i5100_init_one(struct pci_dev *pdev,
765 mci->mod_ver = "not versioned"; 879 mci->mod_ver = "not versioned";
766 mci->ctl_name = "i5100"; 880 mci->ctl_name = "i5100";
767 mci->dev_name = pci_name(pdev); 881 mci->dev_name = pci_name(pdev);
768 mci->ctl_page_to_phys = i5100_ctl_page_to_phys; 882 mci->ctl_page_to_phys = NULL;
769 883
770 mci->edac_check = i5100_check_error; 884 mci->edac_check = i5100_check_error;
771 885
@@ -786,17 +900,26 @@ static int __devinit i5100_init_one(struct pci_dev *pdev,
786 goto bail_mc; 900 goto bail_mc;
787 } 901 }
788 902
789 goto bail; 903 return ret;
790 904
791bail_mc: 905bail_mc:
792 edac_mc_free(mci); 906 edac_mc_free(mci);
793 907
908bail_disable_ch1:
909 pci_disable_device(ch1mm);
910
794bail_ch1: 911bail_ch1:
795 pci_dev_put(ch1mm); 912 pci_dev_put(ch1mm);
796 913
914bail_disable_ch0:
915 pci_disable_device(ch0mm);
916
797bail_ch0: 917bail_ch0:
798 pci_dev_put(ch0mm); 918 pci_dev_put(ch0mm);
799 919
920bail_pdev:
921 pci_disable_device(pdev);
922
800bail: 923bail:
801 return ret; 924 return ret;
802} 925}
@@ -812,6 +935,9 @@ static void __devexit i5100_remove_one(struct pci_dev *pdev)
812 return; 935 return;
813 936
814 priv = mci->pvt_info; 937 priv = mci->pvt_info;
938 pci_disable_device(pdev);
939 pci_disable_device(priv->ch0mm);
940 pci_disable_device(priv->ch1mm);
815 pci_dev_put(priv->ch0mm); 941 pci_dev_put(priv->ch0mm);
816 pci_dev_put(priv->ch1mm); 942 pci_dev_put(priv->ch1mm);
817 943