Merge branch 'mpi-master' into wip-k-fmlpwip-k-fmlp

Conflicts:
	litmus/sched_cedf.c

45 files changed, 4541 insertions, 2746 deletions

diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
index 70bb350de996..af1a17d42bd7 100644
--- a/drivers/edac/Kconfig
+++ b/drivers/edac/Kconfig
@@ -7,7 +7,7 @@
 menuconfig EDAC
         bool "EDAC (Error Detection And Correction) reporting"
         depends on HAS_IOMEM
-        depends on X86 || PPC
+        depends on X86 || PPC || TILE
         help
           EDAC is designed to report errors in the core system.
           These are low-level errors that are reported in the CPU or
@@ -39,18 +39,28 @@ config EDAC_DEBUG
           there're four debug levels (x=0,1,2,3 from low to high).
           Usually you should select 'N'.
 
- config EDAC_DECODE_MCE
+config EDAC_DECODE_MCE
         tristate "Decode MCEs in human-readable form (only on AMD for now)"
         depends on CPU_SUP_AMD && X86_MCE
         default y
         ---help---
           Enable this option if you want to decode Machine Check Exceptions
-          occuring on your machine in human-readable form.
+          occurring on your machine in human-readable form.
 
           You should definitely say Y here in case you want to decode MCEs
           which occur really early upon boot, before the module infrastructure
           has been initialized.
 
+config EDAC_MCE_INJ
+        tristate "Simple MCE injection interface over /sysfs"
+        depends on EDAC_DECODE_MCE
+        default n
+        help
+          This is a simple interface to inject MCEs over /sysfs and test
+          the MCE decoding code in EDAC.
+
+          This is currently AMD-only.
+
 config EDAC_MM_EDAC
         tristate "Main Memory EDAC (Error Detection And Correction) reporting"
         help
@@ -65,14 +75,14 @@ config EDAC_MCE
         bool
 
 config EDAC_AMD64
-        tristate "AMD64 (Opteron, Athlon64) K8, F10h, F11h"
-        depends on EDAC_MM_EDAC && K8_NB && X86_64 && PCI && EDAC_DECODE_MCE
+        tristate "AMD64 (Opteron, Athlon64) K8, F10h"
+        depends on EDAC_MM_EDAC && AMD_NB && X86_64 && EDAC_DECODE_MCE
         help
-          Support for error detection and correction on the AMD 64
-          Families of Memory Controllers (K8, F10h and F11h)
+          Support for error detection and correction of DRAM ECC errors on
+          the AMD64 families of memory controllers (K8 and F10h)
 
 config EDAC_AMD64_ERROR_INJECTION
-        bool "Sysfs Error Injection facilities"
+        bool "Sysfs HW Error injection facilities"
         depends on EDAC_AMD64
         help
           Recent Opterons (Family 10h and later) provide for Memory Error
@@ -199,6 +209,13 @@ config EDAC_I5100
           Support for error detection and correction the Intel
           San Clemente MCH.
 
+config EDAC_I7300
+        tristate "Intel Clarksboro MCH"
+        depends on EDAC_MM_EDAC && X86 && PCI
+        help
+          Support for error detection and correction the Intel
+          Clarksboro MCH (Intel 7300 chipset).
+
 config EDAC_MPC85XX
         tristate "Freescale MPC83xx / MPC85xx"
         depends on EDAC_MM_EDAC && FSL_SOC && (PPC_83xx || PPC_85xx)
@@ -265,4 +282,12 @@ config EDAC_CPC925
           a companion chip to the PowerPC 970 family of
           processors.
 
+config EDAC_TILE
+        tristate "Tilera Memory Controller"
+        depends on EDAC_MM_EDAC && TILE
+        default y
+        help
+          Support for error detection and correction on the
+          Tilera memory controller.
+
 endif # EDAC
diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile
index ca6b1bb24ccc..3e239133e29e 100644
--- a/drivers/edac/Makefile
+++ b/drivers/edac/Makefile
@@ -10,13 +10,16 @@ obj-$(CONFIG_EDAC)			:= edac_stub.o
 obj-$(CONFIG_EDAC_MM_EDAC)              += edac_core.o
 obj-$(CONFIG_EDAC_MCE)                  += edac_mce.o
 
-edac_core-objs  := edac_mc.o edac_device.o edac_mc_sysfs.o edac_pci_sysfs.o
-edac_core-objs  += edac_module.o edac_device_sysfs.o
+edac_core-y     := edac_mc.o edac_device.o edac_mc_sysfs.o edac_pci_sysfs.o
+edac_core-y     += edac_module.o edac_device_sysfs.o
 
 ifdef CONFIG_PCI
-edac_core-objs  += edac_pci.o edac_pci_sysfs.o
+edac_core-y     += edac_pci.o edac_pci_sysfs.o
 endif
 
+obj-$(CONFIG_EDAC_MCE_INJ)              += mce_amd_inj.o
+
+edac_mce_amd-y                          := mce_amd.o
 obj-$(CONFIG_EDAC_DECODE_MCE)           += edac_mce_amd.o
 
 obj-$(CONFIG_EDAC_AMD76X)               += amd76x_edac.o
@@ -24,6 +27,7 @@ obj-$(CONFIG_EDAC_CPC925)		+= cpc925_edac.o
 obj-$(CONFIG_EDAC_I5000)                += i5000_edac.o
 obj-$(CONFIG_EDAC_I5100)                += i5100_edac.o
 obj-$(CONFIG_EDAC_I5400)                += i5400_edac.o
+obj-$(CONFIG_EDAC_I7300)                += i7300_edac.o
 obj-$(CONFIG_EDAC_I7CORE)               += i7core_edac.o
 obj-$(CONFIG_EDAC_E7XXX)                += e7xxx_edac.o
 obj-$(CONFIG_EDAC_E752X)                += e752x_edac.o
@@ -50,3 +54,4 @@ obj-$(CONFIG_EDAC_PPC4XX)		+= ppc4xx_edac.o
 obj-$(CONFIG_EDAC_AMD8111)              += amd8111_edac.o
 obj-$(CONFIG_EDAC_AMD8131)              += amd8131_edac.o
 
+obj-$(CONFIG_EDAC_TILE)                 += tile_edac.o
diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index e7d5d6b5dcf6..9a8bebcf6b17 100644
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -1,5 +1,5 @@
 #include "amd64_edac.h"
-#include <asm/k8.h>
+#include <asm/amd_nb.h>
 
 static struct edac_pci_ctl_info *amd64_ctl_pci;
 
@@ -15,55 +15,14 @@ module_param(ecc_enable_override, int, 0644);
 
 static struct msr __percpu *msrs;
 
-/* Lookup table for all possible MC control instances */
-struct amd64_pvt;
-static struct mem_ctl_info *mci_lookup[EDAC_MAX_NUMNODES];
-static struct amd64_pvt *pvt_lookup[EDAC_MAX_NUMNODES];
-
 /*
- * Address to DRAM bank mapping: see F2x80 for K8 and F2x[1,0]80 for Fam10 and
- * later.
+ * count successfully initialized driver instances for setup_pci_device()
  */
-static int ddr2_dbam_revCG[] = {
-                           [0]          = 32,
-                           [1]          = 64,
-                           [2]          = 128,
-                           [3]          = 256,
-                           [4]          = 512,
-                           [5]          = 1024,
-                           [6]          = 2048,
-};
-
-static int ddr2_dbam_revD[] = {
-                           [0]          = 32,
-                           [1]          = 64,
-                           [2 ... 3]    = 128,
-                           [4]          = 256,
-                           [5]          = 512,
-                           [6]          = 256,
-                           [7]          = 512,
-                           [8 ... 9]    = 1024,
-                           [10]         = 2048,
-};
+static atomic_t drv_instances = ATOMIC_INIT(0);
 
-static int ddr2_dbam[] = { [0]          = 128,
-                           [1]          = 256,
-                           [2 ... 4]    = 512,
-                           [5 ... 6]    = 1024,
-                           [7 ... 8]    = 2048,
-                           [9 ... 10]   = 4096,
-                           [11]         = 8192,
-};
-
-static int ddr3_dbam[] = { [0]          = -1,
-                           [1]          = 256,
-                           [2]          = 512,
-                           [3 ... 4]    = -1,
-                           [5 ... 6]    = 1024,
-                           [7 ... 8]    = 2048,
-                           [9 ... 10]   = 4096,
-                           [11] = 8192,
-};
+/* Per-node driver instances */
+static struct mem_ctl_info **mcis;
+static struct ecc_settings **ecc_stngs;
 
 /*
  * Valid scrub rates for the K8 hardware memory scrubber. We map the scrubbing
@@ -72,8 +31,10 @@ static int ddr3_dbam[] = { [0]		= -1,
  *
  *FIXME: Produce a better mapping/linearisation.
  */
-
-struct scrubrate scrubrates[] = {
+struct scrubrate {
+       u32 scrubval;           /* bit pattern for scrub rate */
+       u32 bandwidth;          /* bandwidth consumed (bytes/sec) */
+} scrubrates[] = {
         { 0x01, 1600000000UL},
         { 0x02, 800000000UL},
         { 0x03, 400000000UL},
@@ -99,6 +60,79 @@ struct scrubrate scrubrates[] = {
         { 0x00, 0UL},        /* scrubbing off */
 };
 
+static int __amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset,
+                                      u32 *val, const char *func)
+{
+        int err = 0;
+
+        err = pci_read_config_dword(pdev, offset, val);
+        if (err)
+                amd64_warn("%s: error reading F%dx%03x.\n",
+                           func, PCI_FUNC(pdev->devfn), offset);
+
+        return err;
+}
+
+int __amd64_write_pci_cfg_dword(struct pci_dev *pdev, int offset,
+                                u32 val, const char *func)
+{
+        int err = 0;
+
+        err = pci_write_config_dword(pdev, offset, val);
+        if (err)
+                amd64_warn("%s: error writing to F%dx%03x.\n",
+                           func, PCI_FUNC(pdev->devfn), offset);
+
+        return err;
+}
+
+/*
+ *
+ * Depending on the family, F2 DCT reads need special handling:
+ *
+ * K8: has a single DCT only
+ *
+ * F10h: each DCT has its own set of regs
+ *      DCT0 -> F2x040..
+ *      DCT1 -> F2x140..
+ *
+ * F15h: we select which DCT we access using F1x10C[DctCfgSel]
+ *
+ */
+static int k8_read_dct_pci_cfg(struct amd64_pvt *pvt, int addr, u32 *val,
+                               const char *func)
+{
+        if (addr >= 0x100)
+                return -EINVAL;
+
+        return __amd64_read_pci_cfg_dword(pvt->F2, addr, val, func);
+}
+
+static int f10_read_dct_pci_cfg(struct amd64_pvt *pvt, int addr, u32 *val,
+                                 const char *func)
+{
+        return __amd64_read_pci_cfg_dword(pvt->F2, addr, val, func);
+}
+
+static int f15_read_dct_pci_cfg(struct amd64_pvt *pvt, int addr, u32 *val,
+                                 const char *func)
+{
+        u32 reg = 0;
+        u8 dct  = 0;
+
+        if (addr >= 0x140 && addr <= 0x1a0) {
+                dct   = 1;
+                addr -= 0x100;
+        }
+
+        amd64_read_pci_cfg(pvt->F1, DCT_CFG_SEL, &reg);
+        reg &= 0xfffffffe;
+        reg |= dct;
+        amd64_write_pci_cfg(pvt->F1, DCT_CFG_SEL, reg);
+
+        return __amd64_read_pci_cfg_dword(pvt->F2, addr, val, func);
+}
+
 /*
  * Memory scrubber control interface. For K8, memory scrubbing is handled by
  * hardware and can involve L2 cache, dcache as well as the main memory. With
@@ -117,8 +151,7 @@ struct scrubrate scrubrates[] = {
  * scan the scrub rate mapping table for a close or matching bandwidth value to
  * issue. If requested is too big, then use last maximum value found.
  */
-static int amd64_search_set_scrub_rate(struct pci_dev *ctl, u32 new_bw,
-                                       u32 min_scrubrate)
+static int __amd64_set_scrub_rate(struct pci_dev *ctl, u32 new_bw, u32 min_rate)
 {
         u32 scrubval;
         int i;
@@ -134,7 +167,7 @@ static int amd64_search_set_scrub_rate(struct pci_dev *ctl, u32 new_bw,
                  * skip scrub rates which aren't recommended
                  * (see F10 BKDG, F3x58)
                  */
-                if (scrubrates[i].scrubval < min_scrubrate)
+                if (scrubrates[i].scrubval < min_rate)
                         continue;
 
                 if (scrubrates[i].bandwidth <= new_bw)
@@ -148,123 +181,53 @@ static int amd64_search_set_scrub_rate(struct pci_dev *ctl, u32 new_bw,
         }
 
         scrubval = scrubrates[i].scrubval;
-        if (scrubval)
-                edac_printk(KERN_DEBUG, EDAC_MC,
-                            "Setting scrub rate bandwidth: %u\n",
-                            scrubrates[i].bandwidth);
-        else
-                edac_printk(KERN_DEBUG, EDAC_MC, "Turning scrubbing off.\n");
 
-        pci_write_bits32(ctl, K8_SCRCTRL, scrubval, 0x001F);
+        pci_write_bits32(ctl, SCRCTRL, scrubval, 0x001F);
+
+        if (scrubval)
+                return scrubrates[i].bandwidth;
 
         return 0;
 }
 
-static int amd64_set_scrub_rate(struct mem_ctl_info *mci, u32 bandwidth)
+static int amd64_set_scrub_rate(struct mem_ctl_info *mci, u32 bw)
 {
         struct amd64_pvt *pvt = mci->pvt_info;
-        u32 min_scrubrate = 0x0;
+        u32 min_scrubrate = 0x5;
 
-        switch (boot_cpu_data.x86) {
-        case 0xf:
-                min_scrubrate = K8_MIN_SCRUB_RATE_BITS;
-                break;
-        case 0x10:
-                min_scrubrate = F10_MIN_SCRUB_RATE_BITS;
-                break;
-        case 0x11:
-                min_scrubrate = F11_MIN_SCRUB_RATE_BITS;
-                break;
+        if (boot_cpu_data.x86 == 0xf)
+                min_scrubrate = 0x0;
 
-        default:
-                amd64_printk(KERN_ERR, "Unsupported family!\n");
-                return -EINVAL;
-        }
-        return amd64_search_set_scrub_rate(pvt->misc_f3_ctl, bandwidth,
-                                           min_scrubrate);
+        return __amd64_set_scrub_rate(pvt->F3, bw, min_scrubrate);
 }
 
-static int amd64_get_scrub_rate(struct mem_ctl_info *mci, u32 *bw)
+static int amd64_get_scrub_rate(struct mem_ctl_info *mci)
 {
         struct amd64_pvt *pvt = mci->pvt_info;
         u32 scrubval = 0;
-        int status = -1, i;
+        int i, retval = -EINVAL;
 
-        amd64_read_pci_cfg(pvt->misc_f3_ctl, K8_SCRCTRL, &scrubval);
+        amd64_read_pci_cfg(pvt->F3, SCRCTRL, &scrubval);
 
         scrubval = scrubval & 0x001F;
 
-        edac_printk(KERN_DEBUG, EDAC_MC,
-                    "pci-read, sdram scrub control value: %d \n", scrubval);
-
         for (i = 0; i < ARRAY_SIZE(scrubrates); i++) {
                 if (scrubrates[i].scrubval == scrubval) {
-                        *bw = scrubrates[i].bandwidth;
-                        status = 0;
+                        retval = scrubrates[i].bandwidth;
                         break;
                 }
         }
-
-        return status;
-}
-
-/* Map from a CSROW entry to the mask entry that operates on it */
-static inline u32 amd64_map_to_dcs_mask(struct amd64_pvt *pvt, int csrow)
-{
-        if (boot_cpu_data.x86 == 0xf && pvt->ext_model < K8_REV_F)
-                return csrow;
-        else
-                return csrow >> 1;
-}
-
-/* return the 'base' address the i'th CS entry of the 'dct' DRAM controller */
-static u32 amd64_get_dct_base(struct amd64_pvt *pvt, int dct, int csrow)
-{
-        if (dct == 0)
-                return pvt->dcsb0[csrow];
-        else
-                return pvt->dcsb1[csrow];
+        return retval;
 }
 
 /*
- * Return the 'mask' address the i'th CS entry. This function is needed because
- * there number of DCSM registers on Rev E and prior vs Rev F and later is
- * different.
+ * returns true if the SysAddr given by sys_addr matches the
+ * DRAM base/limit associated with node_id
  */
-static u32 amd64_get_dct_mask(struct amd64_pvt *pvt, int dct, int csrow)
+static bool amd64_base_limit_match(struct amd64_pvt *pvt, u64 sys_addr,
+                                   unsigned nid)
 {
-        if (dct == 0)
-                return pvt->dcsm0[amd64_map_to_dcs_mask(pvt, csrow)];
-        else
-                return pvt->dcsm1[amd64_map_to_dcs_mask(pvt, csrow)];
-}
-
-
-/*
- * In *base and *limit, pass back the full 40-bit base and limit physical
- * addresses for the node given by node_id.  This information is obtained from
- * DRAM Base (section 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers. The
- * base and limit addresses are of type SysAddr, as defined at the start of
- * section 3.4.4 (p. 70).  They are the lowest and highest physical addresses
- * in the address range they represent.
- */
-static void amd64_get_base_and_limit(struct amd64_pvt *pvt, int node_id,
-                               u64 *base, u64 *limit)
-{
-        *base = pvt->dram_base[node_id];
-        *limit = pvt->dram_limit[node_id];
-}
-
-/*
- * Return 1 if the SysAddr given by sys_addr matches the base/limit associated
- * with node_id
- */
-static int amd64_base_limit_match(struct amd64_pvt *pvt,
-                                        u64 sys_addr, int node_id)
-{
-        u64 base, limit, addr;
-
-        amd64_get_base_and_limit(pvt, node_id, &base, &limit);
+        u64 addr;
 
         /* The K8 treats this as a 40-bit value.  However, bits 63-40 will be
          * all ones if the most significant implemented address bit is 1.
@@ -274,7 +237,8 @@ static int amd64_base_limit_match(struct amd64_pvt *pvt,
          */
         addr = sys_addr & 0x000000ffffffffffull;
 
-        return (addr >= base) && (addr <= limit);
+        return ((addr >= get_dram_base(pvt, nid)) &&
+                (addr <= get_dram_limit(pvt, nid)));
 }
 
 /*
@@ -287,7 +251,7 @@ static struct mem_ctl_info *find_mc_by_sys_addr(struct mem_ctl_info *mci,
                                                 u64 sys_addr)
 {
         struct amd64_pvt *pvt;
-        int node_id;
+        unsigned node_id;
         u32 intlv_en, bits;
 
         /*
@@ -301,10 +265,10 @@ static struct mem_ctl_info *find_mc_by_sys_addr(struct mem_ctl_info *mci,
          * registers.  Therefore we arbitrarily choose to read it from the
          * register for node 0.
          */
-        intlv_en = pvt->dram_IntlvEn[0];
+        intlv_en = dram_intlv_en(pvt, 0);
 
         if (intlv_en == 0) {
-                for (node_id = 0; node_id < DRAM_REG_COUNT; node_id++) {
+                for (node_id = 0; node_id < DRAM_RANGES; node_id++) {
                         if (amd64_base_limit_match(pvt, sys_addr, node_id))
                                 goto found;
                 }
@@ -314,34 +278,30 @@ static struct mem_ctl_info *find_mc_by_sys_addr(struct mem_ctl_info *mci,
         if (unlikely((intlv_en != 0x01) &&
                      (intlv_en != 0x03) &&
                      (intlv_en != 0x07))) {
-                amd64_printk(KERN_WARNING, "junk value of 0x%x extracted from "
-                             "IntlvEn field of DRAM Base Register for node 0: "
-                             "this probably indicates a BIOS bug.\n", intlv_en);
+                amd64_warn("DRAM Base[IntlvEn] junk value: 0x%x, BIOS bug?\n", intlv_en);
                 return NULL;
         }
 
         bits = (((u32) sys_addr) >> 12) & intlv_en;
 
         for (node_id = 0; ; ) {
-                if ((pvt->dram_IntlvSel[node_id] & intlv_en) == bits)
+                if ((dram_intlv_sel(pvt, node_id) & intlv_en) == bits)
                         break;  /* intlv_sel field matches */
 
-                if (++node_id >= DRAM_REG_COUNT)
+                if (++node_id >= DRAM_RANGES)
                         goto err_no_match;
         }
 
         /* sanity test for sys_addr */
         if (unlikely(!amd64_base_limit_match(pvt, sys_addr, node_id))) {
-                amd64_printk(KERN_WARNING,
-                             "%s(): sys_addr 0x%llx falls outside base/limit "
-                             "address range for node %d with node interleaving "
-                             "enabled.\n",
-                             __func__, sys_addr, node_id);
+                amd64_warn("%s: sys_addr 0x%llx falls outside base/limit address"
+                           "range for node %d with node interleaving enabled.\n",
+                           __func__, sys_addr, node_id);
                 return NULL;
         }
 
 found:
-        return edac_mc_find(node_id);
+        return edac_mc_find((int)node_id);
 
 err_no_match:
         debugf2("sys_addr 0x%lx doesn't match any node\n",
@@ -351,37 +311,50 @@ err_no_match:
 }
 
 /*
- * Extract the DRAM CS base address from selected csrow register.
- */
-static u64 base_from_dct_base(struct amd64_pvt *pvt, int csrow)
-{
-        return ((u64) (amd64_get_dct_base(pvt, 0, csrow) & pvt->dcsb_base)) <<
-                                pvt->dcs_shift;
-}
-
-/*
- * Extract the mask from the dcsb0[csrow] entry in a CPU revision-specific way.
+ * compute the CS base address of the @csrow on the DRAM controller @dct.
+ * For details see F2x[5C:40] in the processor's BKDG
  */
-static u64 mask_from_dct_mask(struct amd64_pvt *pvt, int csrow)
+static void get_cs_base_and_mask(struct amd64_pvt *pvt, int csrow, u8 dct,
+                                 u64 *base, u64 *mask)
 {
-        u64 dcsm_bits, other_bits;
-        u64 mask;
+        u64 csbase, csmask, base_bits, mask_bits;
+        u8 addr_shift;
 
-        /* Extract bits from DRAM CS Mask. */
-        dcsm_bits = amd64_get_dct_mask(pvt, 0, csrow) & pvt->dcsm_mask;
+        if (boot_cpu_data.x86 == 0xf && pvt->ext_model < K8_REV_F) {
+                csbase          = pvt->csels[dct].csbases[csrow];
+                csmask          = pvt->csels[dct].csmasks[csrow];
+                base_bits       = GENMASK(21, 31) | GENMASK(9, 15);
+                mask_bits       = GENMASK(21, 29) | GENMASK(9, 15);
+                addr_shift      = 4;
+        } else {
+                csbase          = pvt->csels[dct].csbases[csrow];
+                csmask          = pvt->csels[dct].csmasks[csrow >> 1];
+                addr_shift      = 8;
 
-        other_bits = pvt->dcsm_mask;
-        other_bits = ~(other_bits << pvt->dcs_shift);
+                if (boot_cpu_data.x86 == 0x15)
+                        base_bits = mask_bits = GENMASK(19,30) | GENMASK(5,13);
+                else
+                        base_bits = mask_bits = GENMASK(19,28) | GENMASK(5,13);
+        }
 
-        /*
-         * The extracted bits from DCSM belong in the spaces represented by
-         * the cleared bits in other_bits.
-         */
-        mask = (dcsm_bits << pvt->dcs_shift) | other_bits;
+        *base  = (csbase & base_bits) << addr_shift;
 
-        return mask;
+        *mask  = ~0ULL;
+        /* poke holes for the csmask */
+        *mask &= ~(mask_bits << addr_shift);
+        /* OR them in */
+        *mask |= (csmask & mask_bits) << addr_shift;
 }
 
+#define for_each_chip_select(i, dct, pvt) \
+        for (i = 0; i < pvt->csels[dct].b_cnt; i++)
+
+#define chip_select_base(i, dct, pvt) \
+        pvt->csels[dct].csbases[i]
+
+#define for_each_chip_select_mask(i, dct, pvt) \
+        for (i = 0; i < pvt->csels[dct].m_cnt; i++)
+
 /*
  * @input_addr is an InputAddr associated with the node given by mci. Return the
  * csrow that input_addr maps to, or -1 on failure (no csrow claims input_addr).
@@ -394,19 +367,13 @@ static int input_addr_to_csrow(struct mem_ctl_info *mci, u64 input_addr)
 
         pvt = mci->pvt_info;
 
-        /*
-         * Here we use the DRAM CS Base and DRAM CS Mask registers. For each CS
-         * base/mask register pair, test the condition shown near the start of
-         * section 3.5.4 (p. 84, BKDG #26094, K8, revA-E).
-         */
-        for (csrow = 0; csrow < pvt->cs_count; csrow++) {
-
-                /* This DRAM chip select is disabled on this node */
-                if ((pvt->dcsb0[csrow] & K8_DCSB_CS_ENABLE) == 0)
+        for_each_chip_select(csrow, 0, pvt) {
+                if (!csrow_enabled(csrow, 0, pvt))
                         continue;
 
-                base = base_from_dct_base(pvt, csrow);
-                mask = ~mask_from_dct_mask(pvt, csrow);
+                get_cs_base_and_mask(pvt, csrow, 0, &base, &mask);
+
+                mask = ~mask;
 
                 if ((input_addr & mask) == (base & mask)) {
                         debugf2("InputAddr 0x%lx matches csrow %d (node %d)\n",
@@ -416,7 +383,6 @@ static int input_addr_to_csrow(struct mem_ctl_info *mci, u64 input_addr)
                         return csrow;
                 }
         }
-
         debugf2("no matching csrow for InputAddr 0x%lx (MC node %d)\n",
                 (unsigned long)input_addr, pvt->mc_node_id);
 
@@ -424,19 +390,6 @@ static int input_addr_to_csrow(struct mem_ctl_info *mci, u64 input_addr)
 }
 
 /*
- * Return the base value defined by the DRAM Base register for the node
- * represented by mci.  This function returns the full 40-bit value despite the
- * fact that the register only stores bits 39-24 of the value. See section
- * 3.4.4.1 (BKDG #26094, K8, revA-E)
- */
-static inline u64 get_dram_base(struct mem_ctl_info *mci)
-{
-        struct amd64_pvt *pvt = mci->pvt_info;
-
-        return pvt->dram_base[pvt->mc_node_id];
-}
-
-/*
  * Obtain info from the DRAM Hole Address Register (section 3.4.8, pub #26094)
  * for the node represented by mci. Info is passed back in *hole_base,
  * *hole_offset, and *hole_size.  Function returns 0 if info is valid or 1 if
@@ -465,14 +418,13 @@ int amd64_get_dram_hole_info(struct mem_ctl_info *mci, u64 *hole_base,
                 return 1;
         }
 
-        /* only valid for Fam10h */
-        if (boot_cpu_data.x86 == 0x10 &&
-            (pvt->dhar & F10_DRAM_MEM_HOIST_VALID) == 0) {
+        /* valid for Fam10h and above */
+        if (boot_cpu_data.x86 >= 0x10 && !dhar_mem_hoist_valid(pvt)) {
                 debugf1("  Dram Memory Hoisting is DISABLED on this system\n");
                 return 1;
         }
 
-        if ((pvt->dhar & DHAR_VALID) == 0) {
+        if (!dhar_valid(pvt)) {
                 debugf1("  Dram Memory Hoisting is DISABLED on this node %d\n",
                         pvt->mc_node_id);
                 return 1;
@@ -496,15 +448,15 @@ int amd64_get_dram_hole_info(struct mem_ctl_info *mci, u64 *hole_base,
          * addresses in the hole so that they start at 0x100000000.
          */
 
-        base = dhar_base(pvt->dhar);
+        base = dhar_base(pvt);
 
         *hole_base = base;
         *hole_size = (0x1ull << 32) - base;
 
         if (boot_cpu_data.x86 > 0xf)
-                *hole_offset = f10_dhar_offset(pvt->dhar);
+                *hole_offset = f10_dhar_offset(pvt);
         else
-                *hole_offset = k8_dhar_offset(pvt->dhar);
+                *hole_offset = k8_dhar_offset(pvt);
 
         debugf1("  DHAR info for node %d base 0x%lx offset 0x%lx size 0x%lx\n",
                 pvt->mc_node_id, (unsigned long)*hole_base,
@@ -545,10 +497,11 @@ EXPORT_SYMBOL_GPL(amd64_get_dram_hole_info);
  */
 static u64 sys_addr_to_dram_addr(struct mem_ctl_info *mci, u64 sys_addr)
 {
+        struct amd64_pvt *pvt = mci->pvt_info;
         u64 dram_base, hole_base, hole_offset, hole_size, dram_addr;
         int ret = 0;
 
-        dram_base = get_dram_base(mci);
+        dram_base = get_dram_base(pvt, pvt->mc_node_id);
 
         ret = amd64_get_dram_hole_info(mci, &hole_base, &hole_offset,
                                       &hole_size);
@@ -576,7 +529,7 @@ static u64 sys_addr_to_dram_addr(struct mem_ctl_info *mci, u64 sys_addr)
          * section 3.4.2 of AMD publication 24592: AMD x86-64 Architecture
          * Programmer's Manual Volume 1 Application Programming.
          */
-        dram_addr = (sys_addr & 0xffffffffffull) - dram_base;
+        dram_addr = (sys_addr & GENMASK(0, 39)) - dram_base;
 
         debugf2("using DRAM Base register to translate SysAddr 0x%lx to "
                 "DramAddr 0x%lx\n", (unsigned long)sys_addr,
@@ -612,9 +565,9 @@ static u64 dram_addr_to_input_addr(struct mem_ctl_info *mci, u64 dram_addr)
          * See the start of section 3.4.4 (p. 70, BKDG #26094, K8, revA-E)
          * concerning translating a DramAddr to an InputAddr.
          */
-        intlv_shift = num_node_interleave_bits(pvt->dram_IntlvEn[0]);
-        input_addr = ((dram_addr >> intlv_shift) & 0xffffff000ull) +
-            (dram_addr & 0xfff);
+        intlv_shift = num_node_interleave_bits(dram_intlv_en(pvt, 0));
+        input_addr = ((dram_addr >> intlv_shift) & GENMASK(12, 35)) +
+                      (dram_addr & 0xfff);
 
         debugf2("  Intlv Shift=%d DramAddr=0x%lx maps to InputAddr=0x%lx\n",
                 intlv_shift, (unsigned long)dram_addr,
@@ -648,7 +601,7 @@ static u64 sys_addr_to_input_addr(struct mem_ctl_info *mci, u64 sys_addr)
 static u64 input_addr_to_dram_addr(struct mem_ctl_info *mci, u64 input_addr)
 {
         struct amd64_pvt *pvt;
-        int node_id, intlv_shift;
+        unsigned node_id, intlv_shift;
         u64 bits, dram_addr;
         u32 intlv_sel;
 
@@ -662,10 +615,10 @@ static u64 input_addr_to_dram_addr(struct mem_ctl_info *mci, u64 input_addr)
          */
         pvt = mci->pvt_info;
         node_id = pvt->mc_node_id;
-        BUG_ON((node_id < 0) || (node_id > 7));
 
-        intlv_shift = num_node_interleave_bits(pvt->dram_IntlvEn[0]);
+        BUG_ON(node_id > 7);
 
+        intlv_shift = num_node_interleave_bits(dram_intlv_en(pvt, 0));
         if (intlv_shift == 0) {
                 debugf1("    InputAddr 0x%lx translates to DramAddr of "
                         "same value\n", (unsigned long)input_addr);
@@ -673,10 +626,10 @@ static u64 input_addr_to_dram_addr(struct mem_ctl_info *mci, u64 input_addr)
                 return input_addr;
         }
 
-        bits = ((input_addr & 0xffffff000ull) << intlv_shift) +
-            (input_addr & 0xfff);
+        bits = ((input_addr & GENMASK(12, 35)) << intlv_shift) +
+                (input_addr & 0xfff);
 
-        intlv_sel = pvt->dram_IntlvSel[node_id] & ((1 << intlv_shift) - 1);
+        intlv_sel = dram_intlv_sel(pvt, node_id) & ((1 << intlv_shift) - 1);
         dram_addr = bits + (intlv_sel << 12);
 
         debugf1("InputAddr 0x%lx translates to DramAddr 0x%lx "
@@ -693,7 +646,7 @@ static u64 input_addr_to_dram_addr(struct mem_ctl_info *mci, u64 input_addr)
 static u64 dram_addr_to_sys_addr(struct mem_ctl_info *mci, u64 dram_addr)
 {
         struct amd64_pvt *pvt = mci->pvt_info;
-        u64 hole_base, hole_offset, hole_size, base, limit, sys_addr;
+        u64 hole_base, hole_offset, hole_size, base, sys_addr;
         int ret = 0;
 
         ret = amd64_get_dram_hole_info(mci, &hole_base, &hole_offset,
@@ -711,7 +664,7 @@ static u64 dram_addr_to_sys_addr(struct mem_ctl_info *mci, u64 dram_addr)
                 }
         }
 
-        amd64_get_base_and_limit(pvt, pvt->mc_node_id, &base, &limit);
+        base     = get_dram_base(pvt, pvt->mc_node_id);
         sys_addr = dram_addr + base;
 
         /*
@@ -756,13 +709,12 @@ static void find_csrow_limits(struct mem_ctl_info *mci, int csrow,
         u64 base, mask;
 
         pvt = mci->pvt_info;
-        BUG_ON((csrow < 0) || (csrow >= pvt->cs_count));
+        BUG_ON((csrow < 0) || (csrow >= pvt->csels[0].b_cnt));
 
-        base = base_from_dct_base(pvt, csrow);
-        mask = mask_from_dct_mask(pvt, csrow);
+        get_cs_base_and_mask(pvt, csrow, 0, &base, &mask);
 
         *input_addr_min = base & ~mask;
-        *input_addr_max = base | mask | pvt->dcs_mask_notused;
+        *input_addr_max = base | mask;
 }
 
 /* Map the Error address to a PAGE and PAGE OFFSET. */
@@ -788,41 +740,20 @@ static int sys_addr_to_csrow(struct mem_ctl_info *mci, u64 sys_addr)
         csrow = input_addr_to_csrow(mci, sys_addr_to_input_addr(mci, sys_addr));
 
         if (csrow == -1)
-                amd64_mc_printk(mci, KERN_ERR,
-                             "Failed to translate InputAddr to csrow for "
-                             "address 0x%lx\n", (unsigned long)sys_addr);
+                amd64_mc_err(mci, "Failed to translate InputAddr to csrow for "
+                                  "address 0x%lx\n", (unsigned long)sys_addr);
         return csrow;
 }
 
 static int get_channel_from_ecc_syndrome(struct mem_ctl_info *, u16);
 
-static u16 extract_syndrome(struct err_regs *err)
-{
-        return ((err->nbsh >> 15) & 0xff) | ((err->nbsl >> 16) & 0xff00);
-}
-
-static void amd64_cpu_display_info(struct amd64_pvt *pvt)
-{
-        if (boot_cpu_data.x86 == 0x11)
-                edac_printk(KERN_DEBUG, EDAC_MC, "F11h CPU detected\n");
-        else if (boot_cpu_data.x86 == 0x10)
-                edac_printk(KERN_DEBUG, EDAC_MC, "F10h CPU detected\n");
-        else if (boot_cpu_data.x86 == 0xf)
-                edac_printk(KERN_DEBUG, EDAC_MC, "%s detected\n",
-                        (pvt->ext_model >= K8_REV_F) ?
-                        "Rev F or later" : "Rev E or earlier");
-        else
-                /* we'll hardly ever ever get here */
-                edac_printk(KERN_ERR, EDAC_MC, "Unknown cpu!\n");
-}
-
 /*
  * Determine if the DIMMs have ECC enabled. ECC is enabled ONLY if all the DIMMs
  * are ECC capable.
  */
 static enum edac_type amd64_determine_edac_cap(struct amd64_pvt *pvt)
 {
-        int bit;
+        u8 bit;
         enum dev_type edac_cap = EDAC_FLAG_NONE;
 
         bit = (boot_cpu_data.x86 > 0xf || pvt->ext_model >= K8_REV_F)
@@ -835,8 +766,7 @@ static enum edac_type amd64_determine_edac_cap(struct amd64_pvt *pvt)
         return edac_cap;
 }
 
-
-static void amd64_debug_display_dimm_sizes(int ctrl, struct amd64_pvt *pvt);
+static void amd64_debug_display_dimm_sizes(struct amd64_pvt *, u8);
 
 static void amd64_dump_dramcfg_low(u32 dclr, int chan)
 {
@@ -849,8 +779,9 @@ static void amd64_dump_dramcfg_low(u32 dclr, int chan)
         debugf1("  PAR/ERR parity: %s\n",
                 (dclr & BIT(8)) ?  "enabled" : "disabled");
 
-        debugf1("  DCT 128bit mode width: %s\n",
-                (dclr & BIT(11)) ?  "128b" : "64b");
+        if (boot_cpu_data.x86 == 0x10)
+                debugf1("  DCT 128bit mode width: %s\n",
+                        (dclr & BIT(11)) ?  "128b" : "64b");
 
         debugf1("  x4 logical DIMMs present: L0: %s L1: %s L2: %s L3: %s\n",
                 (dclr & BIT(12)) ?  "yes" : "no",
@@ -860,18 +791,16 @@ static void amd64_dump_dramcfg_low(u32 dclr, int chan)
 }
 
 /* Display and decode various NB registers for debug purposes. */
-static void amd64_dump_misc_regs(struct amd64_pvt *pvt)
+static void dump_misc_regs(struct amd64_pvt *pvt)
 {
-        int ganged;
-
         debugf1("F3xE8 (NB Cap): 0x%08x\n", pvt->nbcap);
 
         debugf1("  NB two channel DRAM capable: %s\n",
-                (pvt->nbcap & K8_NBCAP_DCT_DUAL) ? "yes" : "no");
+                (pvt->nbcap & NBCAP_DCT_DUAL) ? "yes" : "no");
 
         debugf1("  ECC capable: %s, ChipKill ECC capable: %s\n",
-                (pvt->nbcap & K8_NBCAP_SECDED) ? "yes" : "no",
-                (pvt->nbcap & K8_NBCAP_CHIPKILL) ? "yes" : "no");
+                (pvt->nbcap & NBCAP_SECDED) ? "yes" : "no",
+                (pvt->nbcap & NBCAP_CHIPKILL) ? "yes" : "no");
 
         amd64_dump_dramcfg_low(pvt->dclr0, 0);
 
@@ -879,154 +808,95 @@ static void amd64_dump_misc_regs(struct amd64_pvt *pvt)
 
         debugf1("F1xF0 (DRAM Hole Address): 0x%08x, base: 0x%08x, "
                         "offset: 0x%08x\n",
-                        pvt->dhar,
-                        dhar_base(pvt->dhar),
-                        (boot_cpu_data.x86 == 0xf) ? k8_dhar_offset(pvt->dhar)
-                                                   : f10_dhar_offset(pvt->dhar));
+                        pvt->dhar, dhar_base(pvt),
+                        (boot_cpu_data.x86 == 0xf) ? k8_dhar_offset(pvt)
+                                                   : f10_dhar_offset(pvt));
+
+        debugf1("  DramHoleValid: %s\n", dhar_valid(pvt) ? "yes" : "no");
 
-        debugf1("  DramHoleValid: %s\n",
-                (pvt->dhar & DHAR_VALID) ? "yes" : "no");
+        amd64_debug_display_dimm_sizes(pvt, 0);
 
         /* everything below this point is Fam10h and above */
-        if (boot_cpu_data.x86 == 0xf) {
-                amd64_debug_display_dimm_sizes(0, pvt);
+        if (boot_cpu_data.x86 == 0xf)
                 return;
-        }
 
-        amd64_printk(KERN_INFO, "using %s syndromes.\n",
-                     ((pvt->syn_type == 8) ? "x8" : "x4"));
+        amd64_debug_display_dimm_sizes(pvt, 1);
+
+        amd64_info("using %s syndromes.\n", ((pvt->ecc_sym_sz == 8) ? "x8" : "x4"));
 
         /* Only if NOT ganged does dclr1 have valid info */
         if (!dct_ganging_enabled(pvt))
                 amd64_dump_dramcfg_low(pvt->dclr1, 1);
-
-        /*
-         * Determine if ganged and then dump memory sizes for first controller,
-         * and if NOT ganged dump info for 2nd controller.
-         */
-        ganged = dct_ganging_enabled(pvt);
-
-        amd64_debug_display_dimm_sizes(0, pvt);
-
-        if (!ganged)
-                amd64_debug_display_dimm_sizes(1, pvt);
-}
-
-/* Read in both of DBAM registers */
-static void amd64_read_dbam_reg(struct amd64_pvt *pvt)
-{
-        amd64_read_pci_cfg(pvt->dram_f2_ctl, DBAM0, &pvt->dbam0);
-
-        if (boot_cpu_data.x86 >= 0x10)
-                amd64_read_pci_cfg(pvt->dram_f2_ctl, DBAM1, &pvt->dbam1);
 }
 
 /*
- * NOTE: CPU Revision Dependent code: Rev E and Rev F
- *
- * Set the DCSB and DCSM mask values depending on the CPU revision value. Also
- * set the shift factor for the DCSB and DCSM values.
- *
- * ->dcs_mask_notused, RevE:
- *
- * To find the max InputAddr for the csrow, start with the base address and set
- * all bits that are "don't care" bits in the test at the start of section
- * 3.5.4 (p. 84).
- *
- * The "don't care" bits are all set bits in the mask and all bits in the gaps
- * between bit ranges [35:25] and [19:13]. The value REV_E_DCS_NOTUSED_BITS
- * represents bits [24:20] and [12:0], which are all bits in the above-mentioned
- * gaps.
- *
- * ->dcs_mask_notused, RevF and later:
- *
- * To find the max InputAddr for the csrow, start with the base address and set
- * all bits that are "don't care" bits in the test at the start of NPT section
- * 4.5.4 (p. 87).
- *
- * The "don't care" bits are all set bits in the mask and all bits in the gaps
- * between bit ranges [36:27] and [21:13].
- *
- * The value REV_F_F1Xh_DCS_NOTUSED_BITS represents bits [26:22] and [12:0],
- * which are all bits in the above-mentioned gaps.
+ * see BKDG, F2x[1,0][5C:40], F2[1,0][6C:60]
  */
-static void amd64_set_dct_base_and_mask(struct amd64_pvt *pvt)
+static void prep_chip_selects(struct amd64_pvt *pvt)
 {
-
         if (boot_cpu_data.x86 == 0xf && pvt->ext_model < K8_REV_F) {
-                pvt->dcsb_base          = REV_E_DCSB_BASE_BITS;
-                pvt->dcsm_mask          = REV_E_DCSM_MASK_BITS;
-                pvt->dcs_mask_notused   = REV_E_DCS_NOTUSED_BITS;
-                pvt->dcs_shift          = REV_E_DCS_SHIFT;
-                pvt->cs_count           = 8;
-                pvt->num_dcsm           = 8;
+                pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 8;
+                pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 8;
         } else {
-                pvt->dcsb_base          = REV_F_F1Xh_DCSB_BASE_BITS;
-                pvt->dcsm_mask          = REV_F_F1Xh_DCSM_MASK_BITS;
-                pvt->dcs_mask_notused   = REV_F_F1Xh_DCS_NOTUSED_BITS;
-                pvt->dcs_shift          = REV_F_F1Xh_DCS_SHIFT;
-
-                if (boot_cpu_data.x86 == 0x11) {
-                        pvt->cs_count = 4;
-                        pvt->num_dcsm = 2;
-                } else {
-                        pvt->cs_count = 8;
-                        pvt->num_dcsm = 4;
-                }
+                pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 8;
+                pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 4;
         }
 }
 
 /*
- * Function 2 Offset F10_DCSB0; read in the DCS Base and DCS Mask hw registers
+ * Function 2 Offset F10_DCSB0; read in the DCS Base and DCS Mask registers
  */
-static void amd64_read_dct_base_mask(struct amd64_pvt *pvt)
+static void read_dct_base_mask(struct amd64_pvt *pvt)
 {
-        int cs, reg;
+        int cs;
+
+        prep_chip_selects(pvt);
 
-        amd64_set_dct_base_and_mask(pvt);
+        for_each_chip_select(cs, 0, pvt) {
+                int reg0   = DCSB0 + (cs * 4);
+                int reg1   = DCSB1 + (cs * 4);
+                u32 *base0 = &pvt->csels[0].csbases[cs];
+                u32 *base1 = &pvt->csels[1].csbases[cs];
 
-        for (cs = 0; cs < pvt->cs_count; cs++) {
-                reg = K8_DCSB0 + (cs * 4);
-                if (!amd64_read_pci_cfg(pvt->dram_f2_ctl, reg, &pvt->dcsb0[cs]))
+                if (!amd64_read_dct_pci_cfg(pvt, reg0, base0))
                         debugf0("  DCSB0[%d]=0x%08x reg: F2x%x\n",
-                                cs, pvt->dcsb0[cs], reg);
-
-                /* If DCT are NOT ganged, then read in DCT1's base */
-                if (boot_cpu_data.x86 >= 0x10 && !dct_ganging_enabled(pvt)) {
-                        reg = F10_DCSB1 + (cs * 4);
-                        if (!amd64_read_pci_cfg(pvt->dram_f2_ctl, reg,
-                                                &pvt->dcsb1[cs]))
-                                debugf0("  DCSB1[%d]=0x%08x reg: F2x%x\n",
-                                        cs, pvt->dcsb1[cs], reg);
-                } else {
-                        pvt->dcsb1[cs] = 0;
-                }
+                                cs, *base0, reg0);
+
+                if (boot_cpu_data.x86 == 0xf || dct_ganging_enabled(pvt))
+                        continue;
+
+                if (!amd64_read_dct_pci_cfg(pvt, reg1, base1))
+                        debugf0("  DCSB1[%d]=0x%08x reg: F2x%x\n",
+                                cs, *base1, reg1);
         }
 
-        for (cs = 0; cs < pvt->num_dcsm; cs++) {
-                reg = K8_DCSM0 + (cs * 4);
-                if (!amd64_read_pci_cfg(pvt->dram_f2_ctl, reg, &pvt->dcsm0[cs]))
+        for_each_chip_select_mask(cs, 0, pvt) {
+                int reg0   = DCSM0 + (cs * 4);
+                int reg1   = DCSM1 + (cs * 4);
+                u32 *mask0 = &pvt->csels[0].csmasks[cs];
+                u32 *mask1 = &pvt->csels[1].csmasks[cs];
+
+                if (!amd64_read_dct_pci_cfg(pvt, reg0, mask0))
                         debugf0("    DCSM0[%d]=0x%08x reg: F2x%x\n",
-                                cs, pvt->dcsm0[cs], reg);
-
-                /* If DCT are NOT ganged, then read in DCT1's mask */
-                if (boot_cpu_data.x86 >= 0x10 && !dct_ganging_enabled(pvt)) {
-                        reg = F10_DCSM1 + (cs * 4);
-                        if (!amd64_read_pci_cfg(pvt->dram_f2_ctl, reg,
-                                                &pvt->dcsm1[cs]))
-                                debugf0("    DCSM1[%d]=0x%08x reg: F2x%x\n",
-                                        cs, pvt->dcsm1[cs], reg);
-                } else {
-                        pvt->dcsm1[cs] = 0;
-                }
+                                cs, *mask0, reg0);
+
+                if (boot_cpu_data.x86 == 0xf || dct_ganging_enabled(pvt))
+                        continue;
+
+                if (!amd64_read_dct_pci_cfg(pvt, reg1, mask1))
+                        debugf0("    DCSM1[%d]=0x%08x reg: F2x%x\n",
+                                cs, *mask1, reg1);
         }
 }
 
-static enum mem_type amd64_determine_memory_type(struct amd64_pvt *pvt)
+static enum mem_type amd64_determine_memory_type(struct amd64_pvt *pvt, int cs)
 {
         enum mem_type type;
 
-        if (boot_cpu_data.x86 >= 0x10 || pvt->ext_model >= K8_REV_F) {
+        /* F15h supports only DDR3 */
+        if (boot_cpu_data.x86 >= 0x15)
+                type = (pvt->dclr0 & BIT(16)) ? MEM_DDR3 : MEM_RDDR3;
+        else if (boot_cpu_data.x86 == 0x10 || pvt->ext_model >= K8_REV_F) {
                 if (pvt->dchr0 & DDR3_MODE)
                         type = (pvt->dclr0 & BIT(16)) ? MEM_DDR3 : MEM_RDDR3;
                 else
@@ -1035,35 +905,22 @@ static enum mem_type amd64_determine_memory_type(struct amd64_pvt *pvt)
                 type = (pvt->dclr0 & BIT(18)) ? MEM_DDR : MEM_RDDR;
         }
 
-        debugf1("  Memory type is: %s\n", edac_mem_types[type]);
+        amd64_info("CS%d: %s\n", cs, edac_mem_types[type]);
 
         return type;
 }
 
-/*
- * Read the DRAM Configuration Low register. It differs between CG, D & E revs
- * and the later RevF memory controllers (DDR vs DDR2)
- *
- * Return:
- *      number of memory channels in operation
- * Pass back:
- *      contents of the DCL0_LOW register
- */
+/* Get the number of DCT channels the memory controller is using. */
 static int k8_early_channel_count(struct amd64_pvt *pvt)
 {
-        int flag, err = 0;
+        int flag;
 
-        err = amd64_read_pci_cfg(pvt->dram_f2_ctl, F10_DCLR_0, &pvt->dclr0);
-        if (err)
-                return err;
-
-        if ((boot_cpu_data.x86_model >> 4) >= K8_REV_F) {
+        if (pvt->ext_model >= K8_REV_F)
                 /* RevF (NPT) and later */
-                flag = pvt->dclr0 & F10_WIDTH_128;
-        } else {
+                flag = pvt->dclr0 & WIDTH_128;
+        else
                 /* RevE and earlier */
                 flag = pvt->dclr0 & REVE_WIDTH_128;
-        }
 
         /* not used */
         pvt->dclr1 = 0;
@@ -1071,55 +928,121 @@ static int k8_early_channel_count(struct amd64_pvt *pvt)
         return (flag) ? 2 : 1;
 }
 
-/* extract the ERROR ADDRESS for the K8 CPUs */
-static u64 k8_get_error_address(struct mem_ctl_info *mci,
-                                struct err_regs *info)
+/* On F10h and later ErrAddr is MC4_ADDR[47:1] */
+static u64 get_error_address(struct mce *m)
 {
-        return (((u64) (info->nbeah & 0xff)) << 32) +
-                        (info->nbeal & ~0x03);
+        struct cpuinfo_x86 *c = &boot_cpu_data;
+        u64 addr;
+        u8 start_bit = 1;
+        u8 end_bit   = 47;
+
+        if (c->x86 == 0xf) {
+                start_bit = 3;
+                end_bit   = 39;
+        }
+
+        addr = m->addr & GENMASK(start_bit, end_bit);
+
+        /*
+         * Erratum 637 workaround
+         */
+        if (c->x86 == 0x15) {
+                struct amd64_pvt *pvt;
+                u64 cc6_base, tmp_addr;
+                u32 tmp;
+                u8 mce_nid, intlv_en;
+
+                if ((addr & GENMASK(24, 47)) >> 24 != 0x00fdf7)
+                        return addr;
+
+                mce_nid = amd_get_nb_id(m->extcpu);
+                pvt     = mcis[mce_nid]->pvt_info;
+
+                amd64_read_pci_cfg(pvt->F1, DRAM_LOCAL_NODE_LIM, &tmp);
+                intlv_en = tmp >> 21 & 0x7;
+
+                /* add [47:27] + 3 trailing bits */
+                cc6_base  = (tmp & GENMASK(0, 20)) << 3;
+
+                /* reverse and add DramIntlvEn */
+                cc6_base |= intlv_en ^ 0x7;
+
+                /* pin at [47:24] */
+                cc6_base <<= 24;
+
+                if (!intlv_en)
+                        return cc6_base | (addr & GENMASK(0, 23));
+
+                amd64_read_pci_cfg(pvt->F1, DRAM_LOCAL_NODE_BASE, &tmp);
+
+                                                        /* faster log2 */
+                tmp_addr  = (addr & GENMASK(12, 23)) << __fls(intlv_en + 1);
+
+                /* OR DramIntlvSel into bits [14:12] */
+                tmp_addr |= (tmp & GENMASK(21, 23)) >> 9;
+
+                /* add remaining [11:0] bits from original MC4_ADDR */
+                tmp_addr |= addr & GENMASK(0, 11);
+
+                return cc6_base | tmp_addr;
+        }
+
+        return addr;
 }
 
-/*
- * Read the Base and Limit registers for K8 based Memory controllers; extract
- * fields from the 'raw' reg into separate data fields
- *
- * Isolates: BASE, LIMIT, IntlvEn, IntlvSel, RW_EN
- */
-static void k8_read_dram_base_limit(struct amd64_pvt *pvt, int dram)
+static void read_dram_base_limit_regs(struct amd64_pvt *pvt, unsigned range)
 {
-        u32 low;
-        u32 off = dram << 3;    /* 8 bytes between DRAM entries */
+        struct cpuinfo_x86 *c = &boot_cpu_data;
+        int off = range << 3;
 
-        amd64_read_pci_cfg(pvt->addr_f1_ctl, K8_DRAM_BASE_LOW + off, &low);
+        amd64_read_pci_cfg(pvt->F1, DRAM_BASE_LO + off,  &pvt->ranges[range].base.lo);
+        amd64_read_pci_cfg(pvt->F1, DRAM_LIMIT_LO + off, &pvt->ranges[range].lim.lo);
 
-        /* Extract parts into separate data entries */
-        pvt->dram_base[dram] = ((u64) low & 0xFFFF0000) << 8;
-        pvt->dram_IntlvEn[dram] = (low >> 8) & 0x7;
-        pvt->dram_rw_en[dram] = (low & 0x3);
+        if (c->x86 == 0xf)
+                return;
 
-        amd64_read_pci_cfg(pvt->addr_f1_ctl, K8_DRAM_LIMIT_LOW + off, &low);
+        if (!dram_rw(pvt, range))
+                return;
 
-        /*
-         * Extract parts into separate data entries. Limit is the HIGHEST memory
-         * location of the region, so lower 24 bits need to be all ones
-         */
-        pvt->dram_limit[dram] = (((u64) low & 0xFFFF0000) << 8) | 0x00FFFFFF;
-        pvt->dram_IntlvSel[dram] = (low >> 8) & 0x7;
-        pvt->dram_DstNode[dram] = (low & 0x7);
+        amd64_read_pci_cfg(pvt->F1, DRAM_BASE_HI + off,  &pvt->ranges[range].base.hi);
+        amd64_read_pci_cfg(pvt->F1, DRAM_LIMIT_HI + off, &pvt->ranges[range].lim.hi);
+
+        /* Factor in CC6 save area by reading dst node's limit reg */
+        if (c->x86 == 0x15) {
+                struct pci_dev *f1 = NULL;
+                u8 nid = dram_dst_node(pvt, range);
+                u32 llim;
+
+                f1 = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0x18 + nid, 1));
+                if (WARN_ON(!f1))
+                        return;
+
+                amd64_read_pci_cfg(f1, DRAM_LOCAL_NODE_LIM, &llim);
+
+                pvt->ranges[range].lim.lo &= GENMASK(0, 15);
+
+                                            /* {[39:27],111b} */
+                pvt->ranges[range].lim.lo |= ((llim & 0x1fff) << 3 | 0x7) << 16;
+
+                pvt->ranges[range].lim.hi &= GENMASK(0, 7);
+
+                                            /* [47:40] */
+                pvt->ranges[range].lim.hi |= llim >> 13;
+
+                pci_dev_put(f1);
+        }
 }
 
-static void k8_map_sysaddr_to_csrow(struct mem_ctl_info *mci,
-                                    struct err_regs *err_info, u64 sys_addr)
+static void k8_map_sysaddr_to_csrow(struct mem_ctl_info *mci, u64 sys_addr,
+                                    u16 syndrome)
 {
         struct mem_ctl_info *src_mci;
+        struct amd64_pvt *pvt = mci->pvt_info;
         int channel, csrow;
         u32 page, offset;
-        u16 syndrome;
-
-        syndrome = extract_syndrome(err_info);
 
         /* CHIPKILL enabled */
-        if (err_info->nbcfg & K8_NBCFG_CHIPKILL) {
+        if (pvt->nbcfg & NBCFG_CHIPKILL) {
                 channel = get_channel_from_ecc_syndrome(mci, syndrome);
                 if (channel < 0) {
                         /*
@@ -1127,9 +1050,8 @@ static void k8_map_sysaddr_to_csrow(struct mem_ctl_info *mci,
                          * 2 DIMMs is in error. So we need to ID 'both' of them
                          * as suspect.
                          */
-                        amd64_mc_printk(mci, KERN_WARNING,
-                                        "unknown syndrome 0x%04x - possible "
-                                        "error reporting race\n", syndrome);
+                        amd64_mc_warn(mci, "unknown syndrome 0x%04x - possible "
+                                           "error reporting race\n", syndrome);
                         edac_mc_handle_ce_no_info(mci, EDAC_MOD_STR);
                         return;
                 }
@@ -1151,8 +1073,7 @@ static void k8_map_sysaddr_to_csrow(struct mem_ctl_info *mci,
          */
         src_mci = find_mc_by_sys_addr(mci, sys_addr);
         if (!src_mci) {
-                amd64_mc_printk(mci, KERN_ERR,
-                             "failed to map error address 0x%lx to a node\n",
+                amd64_mc_err(mci, "failed to map error addr 0x%lx to a node\n",
                              (unsigned long)sys_addr);
                 edac_mc_handle_ce_no_info(mci, EDAC_MOD_STR);
                 return;
@@ -1170,18 +1091,41 @@ static void k8_map_sysaddr_to_csrow(struct mem_ctl_info *mci,
         }
 }
 
-static int k8_dbam_to_chip_select(struct amd64_pvt *pvt, int cs_mode)
+static int ddr2_cs_size(unsigned i, bool dct_width)
 {
-        int *dbam_map;
+        unsigned shift = 0;
 
-        if (pvt->ext_model >= K8_REV_F)
-                dbam_map = ddr2_dbam;
-        else if (pvt->ext_model >= K8_REV_D)
-                dbam_map = ddr2_dbam_revD;
+        if (i <= 2)
+                shift = i;
+        else if (!(i & 0x1))
+                shift = i >> 1;
         else
-                dbam_map = ddr2_dbam_revCG;
+                shift = (i + 1) >> 1;
 
-        return dbam_map[cs_mode];
+        return 128 << (shift + !!dct_width);
+}
+
+static int k8_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct,
+                                  unsigned cs_mode)
+{
+        u32 dclr = dct ? pvt->dclr1 : pvt->dclr0;
+
+        if (pvt->ext_model >= K8_REV_F) {
+                WARN_ON(cs_mode > 11);
+                return ddr2_cs_size(cs_mode, dclr & WIDTH_128);
+        }
+        else if (pvt->ext_model >= K8_REV_D) {
+                WARN_ON(cs_mode > 10);
+
+                if (cs_mode == 3 || cs_mode == 8)
+                        return 32 << (cs_mode - 1);
+                else
+                        return 32 << cs_mode;
+        }
+        else {
+                WARN_ON(cs_mode > 6);
+                return 32 << cs_mode;
+        }
 }
 
 /*
@@ -1192,17 +1136,13 @@ static int k8_dbam_to_chip_select(struct amd64_pvt *pvt, int cs_mode)
  * Pass back:
  *      contents of the DCL0_LOW register
  */
-static int f10_early_channel_count(struct amd64_pvt *pvt)
+static int f1x_early_channel_count(struct amd64_pvt *pvt)
 {
-        int dbams[] = { DBAM0, DBAM1 };
         int i, j, channels = 0;
-        u32 dbam;
 
-        /* If we are in 128 bit mode, then we are using 2 channels */
-        if (pvt->dclr0 & F10_WIDTH_128) {
-                channels = 2;
-                return channels;
-        }
+        /* On F10h, if we are in 128 bit mode, then we are using 2 channels */
+        if (boot_cpu_data.x86 == 0x10 && (pvt->dclr0 & WIDTH_128))
+                return 2;
 
         /*
          * Need to check if in unganged mode: In such, there are 2 channels,
@@ -1219,9 +1159,8 @@ static int f10_early_channel_count(struct amd64_pvt *pvt)
          * is more than just one DIMM present in unganged mode. Need to check
          * both controllers since DIMMs can be placed in either one.
          */
-        for (i = 0; i < ARRAY_SIZE(dbams); i++) {
-                if (amd64_read_pci_cfg(pvt->dram_f2_ctl, dbams[i], &dbam))
-                        goto err_reg;
+        for (i = 0; i < 2; i++) {
+                u32 dbam = (i ? pvt->dbam1 : pvt->dbam0);
 
                 for (j = 0; j < 4; j++) {
                         if (DBAM_DIMM(j, dbam) > 0) {
@@ -1234,248 +1173,194 @@ static int f10_early_channel_count(struct amd64_pvt *pvt)
         if (channels > 2)
                 channels = 2;
 
-        debugf0("MCT channel count: %d\n", channels);
+        amd64_info("MCT channel count: %d\n", channels);
 
         return channels;
-
-err_reg:
-        return -1;
-
 }
 
-static int f10_dbam_to_chip_select(struct amd64_pvt *pvt, int cs_mode)
+static int ddr3_cs_size(unsigned i, bool dct_width)
 {
-        int *dbam_map;
+        unsigned shift = 0;
+        int cs_size = 0;
 
-        if (pvt->dchr0 & DDR3_MODE || pvt->dchr1 & DDR3_MODE)
-                dbam_map = ddr3_dbam;
+        if (i == 0 || i == 3 || i == 4)
+                cs_size = -1;
+        else if (i <= 2)
+                shift = i;
+        else if (i == 12)
+                shift = 7;
+        else if (!(i & 0x1))
+                shift = i >> 1;
         else
-                dbam_map = ddr2_dbam;
+                shift = (i + 1) >> 1;
 
-        return dbam_map[cs_mode];
-}
+        if (cs_size != -1)
+                cs_size = (128 * (1 << !!dct_width)) << shift;
 
-/* Enable extended configuration access via 0xCF8 feature */
-static void amd64_setup(struct amd64_pvt *pvt)
-{
-        u32 reg;
-
-        amd64_read_pci_cfg(pvt->misc_f3_ctl, F10_NB_CFG_HIGH, &reg);
-
-        pvt->flags.cf8_extcfg = !!(reg & F10_NB_CFG_LOW_ENABLE_EXT_CFG);
-        reg |= F10_NB_CFG_LOW_ENABLE_EXT_CFG;
-        pci_write_config_dword(pvt->misc_f3_ctl, F10_NB_CFG_HIGH, reg);
+        return cs_size;
 }
 
-/* Restore the extended configuration access via 0xCF8 feature */
-static void amd64_teardown(struct amd64_pvt *pvt)
+static int f10_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct,
+                                   unsigned cs_mode)
 {
-        u32 reg;
-
-        amd64_read_pci_cfg(pvt->misc_f3_ctl, F10_NB_CFG_HIGH, &reg);
+        u32 dclr = dct ? pvt->dclr1 : pvt->dclr0;
 
-        reg &= ~F10_NB_CFG_LOW_ENABLE_EXT_CFG;
-        if (pvt->flags.cf8_extcfg)
-                reg |= F10_NB_CFG_LOW_ENABLE_EXT_CFG;
-        pci_write_config_dword(pvt->misc_f3_ctl, F10_NB_CFG_HIGH, reg);
-}
+        WARN_ON(cs_mode > 11);
 
-static u64 f10_get_error_address(struct mem_ctl_info *mci,
-                        struct err_regs *info)
-{
-        return (((u64) (info->nbeah & 0xffff)) << 32) +
-                        (info->nbeal & ~0x01);
+        if (pvt->dchr0 & DDR3_MODE || pvt->dchr1 & DDR3_MODE)
+                return ddr3_cs_size(cs_mode, dclr & WIDTH_128);
+        else
+                return ddr2_cs_size(cs_mode, dclr & WIDTH_128);
 }
 
 /*
- * Read the Base and Limit registers for F10 based Memory controllers. Extract
- * fields from the 'raw' reg into separate data fields.
- *
- * Isolates: BASE, LIMIT, IntlvEn, IntlvSel, RW_EN.
+ * F15h supports only 64bit DCT interfaces
  */
-static void f10_read_dram_base_limit(struct amd64_pvt *pvt, int dram)
+static int f15_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct,
+                                   unsigned cs_mode)
 {
-        u32 high_offset, low_offset, high_base, low_base, high_limit, low_limit;
-
-        low_offset = K8_DRAM_BASE_LOW + (dram << 3);
-        high_offset = F10_DRAM_BASE_HIGH + (dram << 3);
-
-        /* read the 'raw' DRAM BASE Address register */
-        amd64_read_pci_cfg(pvt->addr_f1_ctl, low_offset, &low_base);
+        WARN_ON(cs_mode > 12);
 
-        /* Read from the ECS data register */
-        amd64_read_pci_cfg(pvt->addr_f1_ctl, high_offset, &high_base);
-
-        /* Extract parts into separate data entries */
-        pvt->dram_rw_en[dram] = (low_base & 0x3);
-
-        if (pvt->dram_rw_en[dram] == 0)
-                return;
-
-        pvt->dram_IntlvEn[dram] = (low_base >> 8) & 0x7;
-
-        pvt->dram_base[dram] = (((u64)high_base & 0x000000FF) << 40) |
-                               (((u64)low_base  & 0xFFFF0000) << 8);
-
-        low_offset = K8_DRAM_LIMIT_LOW + (dram << 3);
-        high_offset = F10_DRAM_LIMIT_HIGH + (dram << 3);
-
-        /* read the 'raw' LIMIT registers */
-        amd64_read_pci_cfg(pvt->addr_f1_ctl, low_offset, &low_limit);
-
-        /* Read from the ECS data register for the HIGH portion */
-        amd64_read_pci_cfg(pvt->addr_f1_ctl, high_offset, &high_limit);
-
-        pvt->dram_DstNode[dram] = (low_limit & 0x7);
-        pvt->dram_IntlvSel[dram] = (low_limit >> 8) & 0x7;
-
-        /*
-         * Extract address values and form a LIMIT address. Limit is the HIGHEST
-         * memory location of the region, so low 24 bits need to be all ones.
-         */
-        pvt->dram_limit[dram] = (((u64)high_limit & 0x000000FF) << 40) |
-                                (((u64) low_limit & 0xFFFF0000) << 8) |
-                                0x00FFFFFF;
+        return ddr3_cs_size(cs_mode, false);
 }
 
-static void f10_read_dram_ctl_register(struct amd64_pvt *pvt)
+static void read_dram_ctl_register(struct amd64_pvt *pvt)
 {
 
-        if (!amd64_read_pci_cfg(pvt->dram_f2_ctl, F10_DCTL_SEL_LOW,
-                                &pvt->dram_ctl_select_low)) {
-                debugf0("F2x110 (DCTL Sel. Low): 0x%08x, "
-                        "High range addresses at: 0x%x\n",
-                        pvt->dram_ctl_select_low,
-                        dct_sel_baseaddr(pvt));
+        if (boot_cpu_data.x86 == 0xf)
+                return;
+
+        if (!amd64_read_dct_pci_cfg(pvt, DCT_SEL_LO, &pvt->dct_sel_lo)) {
+                debugf0("F2x110 (DCTSelLow): 0x%08x, High range addrs at: 0x%x\n",
+                        pvt->dct_sel_lo, dct_sel_baseaddr(pvt));
 
-                debugf0("  DCT mode: %s, All DCTs on: %s\n",
-                        (dct_ganging_enabled(pvt) ? "ganged" : "unganged"),
-                        (dct_dram_enabled(pvt) ? "yes"   : "no"));
+                debugf0("  DCTs operate in %s mode.\n",
+                        (dct_ganging_enabled(pvt) ? "ganged" : "unganged"));
 
                 if (!dct_ganging_enabled(pvt))
                         debugf0("  Address range split per DCT: %s\n",
                                 (dct_high_range_enabled(pvt) ? "yes" : "no"));
 
-                debugf0("  DCT data interleave for ECC: %s, "
+                debugf0("  data interleave for ECC: %s, "
                         "DRAM cleared since last warm reset: %s\n",
                         (dct_data_intlv_enabled(pvt) ? "enabled" : "disabled"),
                         (dct_memory_cleared(pvt) ? "yes" : "no"));
 
-                debugf0("  DCT channel interleave: %s, "
-                        "DCT interleave bits selector: 0x%x\n",
+                debugf0("  channel interleave: %s, "
+                        "interleave bits selector: 0x%x\n",
                         (dct_interleave_enabled(pvt) ? "enabled" : "disabled"),
                         dct_sel_interleave_addr(pvt));
         }
 
-        amd64_read_pci_cfg(pvt->dram_f2_ctl, F10_DCTL_SEL_HIGH,
-                           &pvt->dram_ctl_select_high);
+        amd64_read_dct_pci_cfg(pvt, DCT_SEL_HI, &pvt->dct_sel_hi);
 }
 
 /*
- * determine channel based on the interleaving mode: F10h BKDG, 2.8.9 Memory
+ * Determine channel (DCT) based on the interleaving mode: F10h BKDG, 2.8.9 Memory
  * Interleaving Modes.
  */
-static u32 f10_determine_channel(struct amd64_pvt *pvt, u64 sys_addr,
-                                int hi_range_sel, u32 intlv_en)
+static u8 f1x_determine_channel(struct amd64_pvt *pvt, u64 sys_addr,
+                                bool hi_range_sel, u8 intlv_en)
 {
-        u32 cs, temp, dct_sel_high = (pvt->dram_ctl_select_low >> 1) & 1;
+        u8 dct_sel_high = (pvt->dct_sel_lo >> 1) & 1;
 
         if (dct_ganging_enabled(pvt))
-                cs = 0;
-        else if (hi_range_sel)
-                cs = dct_sel_high;
-        else if (dct_interleave_enabled(pvt)) {
-                /*
-                 * see F2x110[DctSelIntLvAddr] - channel interleave mode
-                 */
-                if (dct_sel_interleave_addr(pvt) == 0)
-                        cs = sys_addr >> 6 & 1;
-                else if ((dct_sel_interleave_addr(pvt) >> 1) & 1) {
-                        temp = hweight_long((u32) ((sys_addr >> 16) & 0x1F)) % 2;
+                return 0;
 
-                        if (dct_sel_interleave_addr(pvt) & 1)
-                                cs = (sys_addr >> 9 & 1) ^ temp;
-                        else
-                                cs = (sys_addr >> 6 & 1) ^ temp;
-                } else if (intlv_en & 4)
-                        cs = sys_addr >> 15 & 1;
-                else if (intlv_en & 2)
-                        cs = sys_addr >> 14 & 1;
-                else if (intlv_en & 1)
-                        cs = sys_addr >> 13 & 1;
-                else
-                        cs = sys_addr >> 12 & 1;
-        } else if (dct_high_range_enabled(pvt) && !dct_ganging_enabled(pvt))
-                cs = ~dct_sel_high & 1;
-        else
-                cs = 0;
+        if (hi_range_sel)
+                return dct_sel_high;
 
-        return cs;
-}
+        /*
+         * see F2x110[DctSelIntLvAddr] - channel interleave mode
+         */
+        if (dct_interleave_enabled(pvt)) {
+                u8 intlv_addr = dct_sel_interleave_addr(pvt);
 
-static inline u32 f10_map_intlv_en_to_shift(u32 intlv_en)
-{
-        if (intlv_en == 1)
-                return 1;
-        else if (intlv_en == 3)
-                return 2;
-        else if (intlv_en == 7)
-                return 3;
+                /* return DCT select function: 0=DCT0, 1=DCT1 */
+                if (!intlv_addr)
+                        return sys_addr >> 6 & 1;
+
+                if (intlv_addr & 0x2) {
+                        u8 shift = intlv_addr & 0x1 ? 9 : 6;
+                        u32 temp = hweight_long((u32) ((sys_addr >> 16) & 0x1F)) % 2;
+
+                        return ((sys_addr >> shift) & 1) ^ temp;
+                }
+
+                return (sys_addr >> (12 + hweight8(intlv_en))) & 1;
+        }
+
+        if (dct_high_range_enabled(pvt))
+                return ~dct_sel_high & 1;
 
         return 0;
 }
 
-/* See F10h BKDG, 2.8.10.2 DctSelBaseOffset Programming */
-static inline u64 f10_get_base_addr_offset(u64 sys_addr, int hi_range_sel,
-                                                 u32 dct_sel_base_addr,
-                                                 u64 dct_sel_base_off,
-                                                 u32 hole_valid, u32 hole_off,
-                                                 u64 dram_base)
+/* Convert the sys_addr to the normalized DCT address */
+static u64 f1x_get_norm_dct_addr(struct amd64_pvt *pvt, unsigned range,
+                                 u64 sys_addr, bool hi_rng,
+                                 u32 dct_sel_base_addr)
 {
         u64 chan_off;
+        u64 dram_base           = get_dram_base(pvt, range);
+        u64 hole_off            = f10_dhar_offset(pvt);
+        u64 dct_sel_base_off    = (pvt->dct_sel_hi & 0xFFFFFC00) << 16;
 
-        if (hi_range_sel) {
-                if (!(dct_sel_base_addr & 0xFFFF0000) &&
-                   hole_valid && (sys_addr >= 0x100000000ULL))
-                        chan_off = hole_off << 16;
+        if (hi_rng) {
+                /*
+                 * if
+                 * base address of high range is below 4Gb
+                 * (bits [47:27] at [31:11])
+                 * DRAM address space on this DCT is hoisted above 4Gb  &&
+                 * sys_addr > 4Gb
+                 *
+                 *      remove hole offset from sys_addr
+                 * else
+                 *      remove high range offset from sys_addr
+                 */
+                if ((!(dct_sel_base_addr >> 16) ||
+                     dct_sel_base_addr < dhar_base(pvt)) &&
+                    dhar_valid(pvt) &&
+                    (sys_addr >= BIT_64(32)))
+                        chan_off = hole_off;
                 else
                         chan_off = dct_sel_base_off;
         } else {
-                if (hole_valid && (sys_addr >= 0x100000000ULL))
-                        chan_off = hole_off << 16;
+                /*
+                 * if
+                 * we have a valid hole         &&
+                 * sys_addr > 4Gb
+                 *
+                 *      remove hole
+                 * else
+                 *      remove dram base to normalize to DCT address
+                 */
+                if (dhar_valid(pvt) && (sys_addr >= BIT_64(32)))
+                        chan_off = hole_off;
                 else
-                        chan_off = dram_base & 0xFFFFF8000000ULL;
+                        chan_off = dram_base;
         }
 
-        return (sys_addr & 0x0000FFFFFFFFFFC0ULL) -
-                        (chan_off & 0x0000FFFFFF800000ULL);
+        return (sys_addr & GENMASK(6,47)) - (chan_off & GENMASK(23,47));
 }
 
-/* Hack for the time being - Can we get this from BIOS?? */
-#define CH0SPARE_RANK   0
-#define CH1SPARE_RANK   1
-
 /*
  * checks if the csrow passed in is marked as SPARED, if so returns the new
  * spare row
  */
-static inline int f10_process_possible_spare(int csrow,
-                                u32 cs, struct amd64_pvt *pvt)
-{
-        u32 swap_done;
-        u32 bad_dram_cs;
-
-        /* Depending on channel, isolate respective SPARING info */
-        if (cs) {
-                swap_done = F10_ONLINE_SPARE_SWAPDONE1(pvt->online_spare);
-                bad_dram_cs = F10_ONLINE_SPARE_BADDRAM_CS1(pvt->online_spare);
-                if (swap_done && (csrow == bad_dram_cs))
-                        csrow = CH1SPARE_RANK;
-        } else {
-                swap_done = F10_ONLINE_SPARE_SWAPDONE0(pvt->online_spare);
-                bad_dram_cs = F10_ONLINE_SPARE_BADDRAM_CS0(pvt->online_spare);
-                if (swap_done && (csrow == bad_dram_cs))
-                        csrow = CH0SPARE_RANK;
+static int f10_process_possible_spare(struct amd64_pvt *pvt, u8 dct, int csrow)
+{
+        int tmp_cs;
+
+        if (online_spare_swap_done(pvt, dct) &&
+            csrow == online_spare_bad_dramcs(pvt, dct)) {
+
+                for_each_chip_select(tmp_cs, dct, pvt) {
+                        if (chip_select_base(tmp_cs, dct, pvt) & 0x2) {
+                                csrow = tmp_cs;
+                                break;
+                        }
+                }
         }
         return csrow;
 }
@@ -1488,53 +1373,39 @@ static inline int f10_process_possible_spare(int csrow,
  *      -EINVAL:  NOT FOUND
  *      0..csrow = Chip-Select Row
  */
-static int f10_lookup_addr_in_dct(u32 in_addr, u32 nid, u32 cs)
+static int f1x_lookup_addr_in_dct(u64 in_addr, u32 nid, u8 dct)
 {
         struct mem_ctl_info *mci;
         struct amd64_pvt *pvt;
-        u32 cs_base, cs_mask;
+        u64 cs_base, cs_mask;
         int cs_found = -EINVAL;
         int csrow;
 
-        mci = mci_lookup[nid];
+        mci = mcis[nid];
         if (!mci)
                 return cs_found;
 
         pvt = mci->pvt_info;
 
-        debugf1("InputAddr=0x%x  channelselect=%d\n", in_addr, cs);
-
-        for (csrow = 0; csrow < pvt->cs_count; csrow++) {
+        debugf1("input addr: 0x%llx, DCT: %d\n", in_addr, dct);
 
-                cs_base = amd64_get_dct_base(pvt, cs, csrow);
-                if (!(cs_base & K8_DCSB_CS_ENABLE))
+        for_each_chip_select(csrow, dct, pvt) {
+                if (!csrow_enabled(csrow, dct, pvt))
                         continue;
 
-                /*
-                 * We have an ENABLED CSROW, Isolate just the MASK bits of the
-                 * target: [28:19] and [13:5], which map to [36:27] and [21:13]
-                 * of the actual address.
-                 */
-                cs_base &= REV_F_F1Xh_DCSB_BASE_BITS;
-
-                /*
-                 * Get the DCT Mask, and ENABLE the reserved bits: [18:16] and
-                 * [4:0] to become ON. Then mask off bits [28:0] ([36:8])
-                 */
-                cs_mask = amd64_get_dct_mask(pvt, cs, csrow);
+                get_cs_base_and_mask(pvt, csrow, dct, &cs_base, &cs_mask);
 
-                debugf1("    CSROW=%d CSBase=0x%x RAW CSMask=0x%x\n",
-                                csrow, cs_base, cs_mask);
+                debugf1("    CSROW=%d CSBase=0x%llx CSMask=0x%llx\n",
+                        csrow, cs_base, cs_mask);
 
-                cs_mask = (cs_mask | 0x0007C01F) & 0x1FFFFFFF;
+                cs_mask = ~cs_mask;
 
-                debugf1("              Final CSMask=0x%x\n", cs_mask);
-                debugf1("    (InputAddr & ~CSMask)=0x%x "
-                                "(CSBase & ~CSMask)=0x%x\n",
-                                (in_addr & ~cs_mask), (cs_base & ~cs_mask));
+                debugf1("    (InputAddr & ~CSMask)=0x%llx "
+                        "(CSBase & ~CSMask)=0x%llx\n",
+                        (in_addr & cs_mask), (cs_base & cs_mask));
 
-                if ((in_addr & ~cs_mask) == (cs_base & ~cs_mask)) {
-                        cs_found = f10_process_possible_spare(csrow, cs, pvt);
+                if ((in_addr & cs_mask) == (cs_base & cs_mask)) {
+                        cs_found = f10_process_possible_spare(pvt, dct, csrow);
 
                         debugf1(" MATCH csrow=%d\n", cs_found);
                         break;
@@ -1543,38 +1414,71 @@ static int f10_lookup_addr_in_dct(u32 in_addr, u32 nid, u32 cs)
         return cs_found;
 }
 
-/* For a given @dram_range, check if @sys_addr falls within it. */
-static int f10_match_to_this_node(struct amd64_pvt *pvt, int dram_range,
-                                  u64 sys_addr, int *nid, int *chan_sel)
+/*
+ * See F2x10C. Non-interleaved graphics framebuffer memory under the 16G is
+ * swapped with a region located at the bottom of memory so that the GPU can use
+ * the interleaved region and thus two channels.
+ */
+static u64 f1x_swap_interleaved_region(struct amd64_pvt *pvt, u64 sys_addr)
 {
-        int node_id, cs_found = -EINVAL, high_range = 0;
-        u32 intlv_en, intlv_sel, intlv_shift, hole_off;
-        u32 hole_valid, tmp, dct_sel_base, channel;
-        u64 dram_base, chan_addr, dct_sel_base_off;
+        u32 swap_reg, swap_base, swap_limit, rgn_size, tmp_addr;
 
-        dram_base = pvt->dram_base[dram_range];
-        intlv_en = pvt->dram_IntlvEn[dram_range];
+        if (boot_cpu_data.x86 == 0x10) {
+                /* only revC3 and revE have that feature */
+                if (boot_cpu_data.x86_model < 4 ||
+                    (boot_cpu_data.x86_model < 0xa &&
+                     boot_cpu_data.x86_mask < 3))
+                        return sys_addr;
+        }
 
-        node_id = pvt->dram_DstNode[dram_range];
-        intlv_sel = pvt->dram_IntlvSel[dram_range];
+        amd64_read_dct_pci_cfg(pvt, SWAP_INTLV_REG, &swap_reg);
 
-        debugf1("(dram=%d) Base=0x%llx SystemAddr= 0x%llx Limit=0x%llx\n",
-                dram_range, dram_base, sys_addr, pvt->dram_limit[dram_range]);
+        if (!(swap_reg & 0x1))
+                return sys_addr;
 
-        /*
-         * This assumes that one node's DHAR is the same as all the other
-         * nodes' DHAR.
-         */
-        hole_off = (pvt->dhar & 0x0000FF80);
-        hole_valid = (pvt->dhar & 0x1);
-        dct_sel_base_off = (pvt->dram_ctl_select_high & 0xFFFFFC00) << 16;
+        swap_base       = (swap_reg >> 3) & 0x7f;
+        swap_limit      = (swap_reg >> 11) & 0x7f;
+        rgn_size        = (swap_reg >> 20) & 0x7f;
+        tmp_addr        = sys_addr >> 27;
+
+        if (!(sys_addr >> 34) &&
+            (((tmp_addr >= swap_base) &&
+             (tmp_addr <= swap_limit)) ||
+             (tmp_addr < rgn_size)))
+                return sys_addr ^ (u64)swap_base << 27;
 
-        debugf1("   HoleOffset=0x%x  HoleValid=0x%x IntlvSel=0x%x\n",
-                        hole_off, hole_valid, intlv_sel);
+        return sys_addr;
+}
 
-        if (intlv_en ||
-            (intlv_sel != ((sys_addr >> 12) & intlv_en)))
+/* For a given @dram_range, check if @sys_addr falls within it. */
+static int f1x_match_to_this_node(struct amd64_pvt *pvt, unsigned range,
+                                  u64 sys_addr, int *nid, int *chan_sel)
+{
+        int cs_found = -EINVAL;
+        u64 chan_addr;
+        u32 dct_sel_base;
+        u8 channel;
+        bool high_range = false;
+
+        u8 node_id    = dram_dst_node(pvt, range);
+        u8 intlv_en   = dram_intlv_en(pvt, range);
+        u32 intlv_sel = dram_intlv_sel(pvt, range);
+
+        debugf1("(range %d) SystemAddr= 0x%llx Limit=0x%llx\n",
+                range, sys_addr, get_dram_limit(pvt, range));
+
+        if (dhar_valid(pvt) &&
+            dhar_base(pvt) <= sys_addr &&
+            sys_addr < BIT_64(32)) {
+                amd64_warn("Huh? Address is in the MMIO hole: 0x%016llx\n",
+                            sys_addr);
                 return -EINVAL;
+        }
+
+        if (intlv_en && (intlv_sel != ((sys_addr >> 12) & intlv_en)))
+                return -EINVAL;
+
+        sys_addr = f1x_swap_interleaved_region(pvt, sys_addr);
 
         dct_sel_base = dct_sel_baseaddr(pvt);
 
@@ -1585,38 +1489,41 @@ static int f10_match_to_this_node(struct amd64_pvt *pvt, int dram_range,
         if (dct_high_range_enabled(pvt) &&
            !dct_ganging_enabled(pvt) &&
            ((sys_addr >> 27) >= (dct_sel_base >> 11)))
-                high_range = 1;
+                high_range = true;
 
-        channel = f10_determine_channel(pvt, sys_addr, high_range, intlv_en);
+        channel = f1x_determine_channel(pvt, sys_addr, high_range, intlv_en);
 
-        chan_addr = f10_get_base_addr_offset(sys_addr, high_range, dct_sel_base,
-                                             dct_sel_base_off, hole_valid,
-                                             hole_off, dram_base);
+        chan_addr = f1x_get_norm_dct_addr(pvt, range, sys_addr,
+                                          high_range, dct_sel_base);
 
-        intlv_shift = f10_map_intlv_en_to_shift(intlv_en);
+        /* Remove node interleaving, see F1x120 */
+        if (intlv_en)
+                chan_addr = ((chan_addr >> (12 + hweight8(intlv_en))) << 12) |
+                            (chan_addr & 0xfff);
 
-        /* remove Node ID (in case of memory interleaving) */
-        tmp = chan_addr & 0xFC0;
-
-        chan_addr = ((chan_addr >> intlv_shift) & 0xFFFFFFFFF000ULL) | tmp;
-
-        /* remove channel interleave and hash */
+        /* remove channel interleave */
         if (dct_interleave_enabled(pvt) &&
            !dct_high_range_enabled(pvt) &&
            !dct_ganging_enabled(pvt)) {
-                if (dct_sel_interleave_addr(pvt) != 1)
-                        chan_addr = (chan_addr >> 1) & 0xFFFFFFFFFFFFFFC0ULL;
-                else {
-                        tmp = chan_addr & 0xFC0;
-                        chan_addr = ((chan_addr & 0xFFFFFFFFFFFFC000ULL) >> 1)
-                                        | tmp;
-                }
+
+                if (dct_sel_interleave_addr(pvt) != 1) {
+                        if (dct_sel_interleave_addr(pvt) == 0x3)
+                                /* hash 9 */
+                                chan_addr = ((chan_addr >> 10) << 9) |
+                                             (chan_addr & 0x1ff);
+                        else
+                                /* A[6] or hash 6 */
+                                chan_addr = ((chan_addr >> 7) << 6) |
+                                             (chan_addr & 0x3f);
+                } else
+                        /* A[12] */
+                        chan_addr = ((chan_addr >> 13) << 12) |
+                                     (chan_addr & 0xfff);
         }
 
-        debugf1("   (ChannelAddrLong=0x%llx) >> 8 becomes InputAddr=0x%x\n",
-                chan_addr, (u32)(chan_addr >> 8));
+        debugf1("   Normalized DCT addr: 0x%llx\n", chan_addr);
 
-        cs_found = f10_lookup_addr_in_dct(chan_addr >> 8, node_id, channel);
+        cs_found = f1x_lookup_addr_in_dct(chan_addr, node_id, channel);
 
         if (cs_found >= 0) {
                 *nid = node_id;
@@ -1625,23 +1532,21 @@ static int f10_match_to_this_node(struct amd64_pvt *pvt, int dram_range,
         return cs_found;
 }
 
-static int f10_translate_sysaddr_to_cs(struct amd64_pvt *pvt, u64 sys_addr,
+static int f1x_translate_sysaddr_to_cs(struct amd64_pvt *pvt, u64 sys_addr,
                                        int *node, int *chan_sel)
 {
-        int dram_range, cs_found = -EINVAL;
-        u64 dram_base, dram_limit;
+        int cs_found = -EINVAL;
+        unsigned range;
 
-        for (dram_range = 0; dram_range < DRAM_REG_COUNT; dram_range++) {
+        for (range = 0; range < DRAM_RANGES; range++) {
 
-                if (!pvt->dram_rw_en[dram_range])
+                if (!dram_rw(pvt, range))
                         continue;
 
-                dram_base = pvt->dram_base[dram_range];
-                dram_limit = pvt->dram_limit[dram_range];
-
-                if ((dram_base <= sys_addr) && (sys_addr <= dram_limit)) {
+                if ((get_dram_base(pvt, range)  <= sys_addr) &&
+                    (get_dram_limit(pvt, range) >= sys_addr)) {
 
-                        cs_found = f10_match_to_this_node(pvt, dram_range,
+                        cs_found = f1x_match_to_this_node(pvt, range,
                                                           sys_addr, node,
                                                           chan_sel);
                         if (cs_found >= 0)
@@ -1658,16 +1563,14 @@ static int f10_translate_sysaddr_to_cs(struct amd64_pvt *pvt, u64 sys_addr,
  * The @sys_addr is usually an error address received from the hardware
  * (MCX_ADDR).
  */
-static void f10_map_sysaddr_to_csrow(struct mem_ctl_info *mci,
-                                     struct err_regs *err_info,
-                                     u64 sys_addr)
+static void f1x_map_sysaddr_to_csrow(struct mem_ctl_info *mci, u64 sys_addr,
+                                     u16 syndrome)
 {
         struct amd64_pvt *pvt = mci->pvt_info;
         u32 page, offset;
         int nid, csrow, chan = 0;
-        u16 syndrome;
 
-        csrow = f10_translate_sysaddr_to_cs(pvt, sys_addr, &nid, &chan);
+        csrow = f1x_translate_sysaddr_to_cs(pvt, sys_addr, &nid, &chan);
 
         if (csrow < 0) {
                 edac_mc_handle_ce_no_info(mci, EDAC_MOD_STR);
@@ -1676,14 +1579,12 @@ static void f10_map_sysaddr_to_csrow(struct mem_ctl_info *mci,
 
         error_address_to_page_and_offset(sys_addr, &page, &offset);
 
-        syndrome = extract_syndrome(err_info);
-
         /*
          * We need the syndromes for channel detection only when we're
          * ganged. Otherwise @chan should already contain the channel at
          * this point.
          */
-        if (dct_ganging_enabled(pvt) && (pvt->nbcfg & K8_NBCFG_CHIPKILL))
+        if (dct_ganging_enabled(pvt))
                 chan = get_channel_from_ecc_syndrome(mci, syndrome);
 
         if (chan >= 0)
@@ -1700,16 +1601,16 @@ static void f10_map_sysaddr_to_csrow(struct mem_ctl_info *mci,
 
 /*
  * debug routine to display the memory sizes of all logical DIMMs and its
- * CSROWs as well
+ * CSROWs
  */
-static void amd64_debug_display_dimm_sizes(int ctrl, struct amd64_pvt *pvt)
+static void amd64_debug_display_dimm_sizes(struct amd64_pvt *pvt, u8 ctrl)
 {
         int dimm, size0, size1, factor = 0;
-        u32 dbam;
-        u32 *dcsb;
+        u32 *dcsb = ctrl ? pvt->csels[1].csbases : pvt->csels[0].csbases;
+        u32 dbam  = ctrl ? pvt->dbam1 : pvt->dbam0;
 
         if (boot_cpu_data.x86 == 0xf) {
-                if (pvt->dclr0 & F10_WIDTH_128)
+                if (pvt->dclr0 & WIDTH_128)
                         factor = 1;
 
                 /* K8 families < revF not supported yet */
@@ -1719,11 +1620,11 @@ static void amd64_debug_display_dimm_sizes(int ctrl, struct amd64_pvt *pvt)
                        WARN_ON(ctrl != 0);
         }
 
-        debugf1("F2x%d80 (DRAM Bank Address Mapping): 0x%08x\n",
-                ctrl, ctrl ? pvt->dbam1 : pvt->dbam0);
+        dbam = (ctrl && !dct_ganging_enabled(pvt)) ? pvt->dbam1 : pvt->dbam0;
+        dcsb = (ctrl && !dct_ganging_enabled(pvt)) ? pvt->csels[1].csbases
+                                                   : pvt->csels[0].csbases;
 
-        dbam = ctrl ? pvt->dbam1 : pvt->dbam0;
-        dcsb = ctrl ? pvt->dcsb1 : pvt->dcsb0;
+        debugf1("F2x%d80 (DRAM Bank Address Mapping): 0x%08x\n", ctrl, dbam);
 
         edac_printk(KERN_DEBUG, EDAC_MC, "DCT%d chip selects:\n", ctrl);
 
@@ -1731,67 +1632,53 @@ static void amd64_debug_display_dimm_sizes(int ctrl, struct amd64_pvt *pvt)
         for (dimm = 0; dimm < 4; dimm++) {
 
                 size0 = 0;
-                if (dcsb[dimm*2] & K8_DCSB_CS_ENABLE)
-                        size0 = pvt->ops->dbam_to_cs(pvt, DBAM_DIMM(dimm, dbam));
+                if (dcsb[dimm*2] & DCSB_CS_ENABLE)
+                        size0 = pvt->ops->dbam_to_cs(pvt, ctrl,
+                                                     DBAM_DIMM(dimm, dbam));
 
                 size1 = 0;
-                if (dcsb[dimm*2 + 1] & K8_DCSB_CS_ENABLE)
-                        size1 = pvt->ops->dbam_to_cs(pvt, DBAM_DIMM(dimm, dbam));
+                if (dcsb[dimm*2 + 1] & DCSB_CS_ENABLE)
+                        size1 = pvt->ops->dbam_to_cs(pvt, ctrl,
+                                                     DBAM_DIMM(dimm, dbam));
 
-                edac_printk(KERN_DEBUG, EDAC_MC, " %d: %5dMB %d: %5dMB\n",
-                            dimm * 2,     size0 << factor,
-                            dimm * 2 + 1, size1 << factor);
+                amd64_info(EDAC_MC ": %d: %5dMB %d: %5dMB\n",
+                                dimm * 2,     size0 << factor,
+                                dimm * 2 + 1, size1 << factor);
         }
 }
 
-/*
- * There currently are 3 types type of MC devices for AMD Athlon/Opterons
- * (as per PCI DEVICE_IDs):
- *
- * Family K8: That is the Athlon64 and Opteron CPUs. They all have the same PCI
- * DEVICE ID, even though there is differences between the different Revisions
- * (CG,D,E,F).
- *
- * Family F10h and F11h.
- *
- */
 static struct amd64_family_type amd64_family_types[] = {
         [K8_CPUS] = {
-                .ctl_name = "RevF",
-                .addr_f1_ctl = PCI_DEVICE_ID_AMD_K8_NB_ADDRMAP,
-                .misc_f3_ctl = PCI_DEVICE_ID_AMD_K8_NB_MISC,
+                .ctl_name = "K8",
+                .f1_id = PCI_DEVICE_ID_AMD_K8_NB_ADDRMAP,
+                .f3_id = PCI_DEVICE_ID_AMD_K8_NB_MISC,
                 .ops = {
                         .early_channel_count    = k8_early_channel_count,
-                        .get_error_address      = k8_get_error_address,
-                        .read_dram_base_limit   = k8_read_dram_base_limit,
                         .map_sysaddr_to_csrow   = k8_map_sysaddr_to_csrow,
                         .dbam_to_cs             = k8_dbam_to_chip_select,
+                        .read_dct_pci_cfg       = k8_read_dct_pci_cfg,
                 }
         },
         [F10_CPUS] = {
-                .ctl_name = "Family 10h",
-                .addr_f1_ctl = PCI_DEVICE_ID_AMD_10H_NB_MAP,
-                .misc_f3_ctl = PCI_DEVICE_ID_AMD_10H_NB_MISC,
+                .ctl_name = "F10h",
+                .f1_id = PCI_DEVICE_ID_AMD_10H_NB_MAP,
+                .f3_id = PCI_DEVICE_ID_AMD_10H_NB_MISC,
                 .ops = {
-                        .early_channel_count    = f10_early_channel_count,
-                        .get_error_address      = f10_get_error_address,
-                        .read_dram_base_limit   = f10_read_dram_base_limit,
-                        .read_dram_ctl_register = f10_read_dram_ctl_register,
-                        .map_sysaddr_to_csrow   = f10_map_sysaddr_to_csrow,
+                        .early_channel_count    = f1x_early_channel_count,
+                        .map_sysaddr_to_csrow   = f1x_map_sysaddr_to_csrow,
                         .dbam_to_cs             = f10_dbam_to_chip_select,
+                        .read_dct_pci_cfg       = f10_read_dct_pci_cfg,
                 }
         },
-        [F11_CPUS] = {
-                .ctl_name = "Family 11h",
-                .addr_f1_ctl = PCI_DEVICE_ID_AMD_11H_NB_MAP,
-                .misc_f3_ctl = PCI_DEVICE_ID_AMD_11H_NB_MISC,
+        [F15_CPUS] = {
+                .ctl_name = "F15h",
+                .f1_id = PCI_DEVICE_ID_AMD_15H_NB_F1,
+                .f3_id = PCI_DEVICE_ID_AMD_15H_NB_F3,
                 .ops = {
-                        .early_channel_count    = f10_early_channel_count,
-                        .get_error_address      = f10_get_error_address,
-                        .read_dram_base_limit   = f10_read_dram_base_limit,
-                        .read_dram_ctl_register = f10_read_dram_ctl_register,
-                        .map_sysaddr_to_csrow   = f10_map_sysaddr_to_csrow,
-                        .dbam_to_cs             = f10_dbam_to_chip_select,
+                        .early_channel_count    = f1x_early_channel_count,
+                        .map_sysaddr_to_csrow   = f1x_map_sysaddr_to_csrow,
+                        .dbam_to_cs             = f15_dbam_to_chip_select,
+                        .read_dct_pci_cfg       = f15_read_dct_pci_cfg,
                 }
         },
 };
@@ -1881,15 +1768,15 @@ static u16 x8_vectors[] = {
         0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000,
 };
 
-static int decode_syndrome(u16 syndrome, u16 *vectors, int num_vecs,
-                           int v_dim)
+static int decode_syndrome(u16 syndrome, u16 *vectors, unsigned num_vecs,
+                           unsigned v_dim)
 {
         unsigned int i, err_sym;
 
         for (err_sym = 0; err_sym < num_vecs / v_dim; err_sym++) {
                 u16 s = syndrome;
-                int v_idx =  err_sym * v_dim;
-                int v_end = (err_sym + 1) * v_dim;
+                unsigned v_idx =  err_sym * v_dim;
+                unsigned v_end = (err_sym + 1) * v_dim;
 
                 /* walk over all 16 bits of the syndrome */
                 for (i = 1; i < (1U << 16); i <<= 1) {
@@ -1961,54 +1848,50 @@ static int get_channel_from_ecc_syndrome(struct mem_ctl_info *mci, u16 syndrome)
         struct amd64_pvt *pvt = mci->pvt_info;
         int err_sym = -1;
 
-        if (pvt->syn_type == 8)
+        if (pvt->ecc_sym_sz == 8)
                 err_sym = decode_syndrome(syndrome, x8_vectors,
                                           ARRAY_SIZE(x8_vectors),
-                                          pvt->syn_type);
-        else if (pvt->syn_type == 4)
+                                          pvt->ecc_sym_sz);
+        else if (pvt->ecc_sym_sz == 4)
                 err_sym = decode_syndrome(syndrome, x4_vectors,
                                           ARRAY_SIZE(x4_vectors),
-                                          pvt->syn_type);
+                                          pvt->ecc_sym_sz);
         else {
-                amd64_printk(KERN_WARNING, "%s: Illegal syndrome type: %u\n",
-                                           __func__, pvt->syn_type);
+                amd64_warn("Illegal syndrome type: %u\n", pvt->ecc_sym_sz);
                 return err_sym;
         }
 
-        return map_err_sym_to_channel(err_sym, pvt->syn_type);
+        return map_err_sym_to_channel(err_sym, pvt->ecc_sym_sz);
 }
 
 /*
  * Handle any Correctable Errors (CEs) that have occurred. Check for valid ERROR
  * ADDRESS and process.
  */
-static void amd64_handle_ce(struct mem_ctl_info *mci,
-                            struct err_regs *info)
+static void amd64_handle_ce(struct mem_ctl_info *mci, struct mce *m)
 {
         struct amd64_pvt *pvt = mci->pvt_info;
         u64 sys_addr;
+        u16 syndrome;
 
         /* Ensure that the Error Address is VALID */
-        if ((info->nbsh & K8_NBSH_VALID_ERROR_ADDR) == 0) {
-                amd64_mc_printk(mci, KERN_ERR,
-                        "HW has no ERROR_ADDRESS available\n");
+        if (!(m->status & MCI_STATUS_ADDRV)) {
+                amd64_mc_err(mci, "HW has no ERROR_ADDRESS available\n");
                 edac_mc_handle_ce_no_info(mci, EDAC_MOD_STR);
                 return;
         }
 
-        sys_addr = pvt->ops->get_error_address(mci, info);
+        sys_addr = get_error_address(m);
+        syndrome = extract_syndrome(m->status);
 
-        amd64_mc_printk(mci, KERN_ERR,
-                "CE ERROR_ADDRESS= 0x%llx\n", sys_addr);
+        amd64_mc_err(mci, "CE ERROR_ADDRESS= 0x%llx\n", sys_addr);
 
-        pvt->ops->map_sysaddr_to_csrow(mci, info, sys_addr);
+        pvt->ops->map_sysaddr_to_csrow(mci, sys_addr, syndrome);
 }
 
 /* Handle any Un-correctable Errors (UEs) */
-static void amd64_handle_ue(struct mem_ctl_info *mci,
-                            struct err_regs *info)
+static void amd64_handle_ue(struct mem_ctl_info *mci, struct mce *m)
 {
-        struct amd64_pvt *pvt = mci->pvt_info;
         struct mem_ctl_info *log_mci, *src_mci = NULL;
         int csrow;
         u64 sys_addr;
@@ -2016,14 +1899,13 @@ static void amd64_handle_ue(struct mem_ctl_info *mci,
 
         log_mci = mci;
 
-        if ((info->nbsh & K8_NBSH_VALID_ERROR_ADDR) == 0) {
-                amd64_mc_printk(mci, KERN_CRIT,
-                        "HW has no ERROR_ADDRESS available\n");
+        if (!(m->status & MCI_STATUS_ADDRV)) {
+                amd64_mc_err(mci, "HW has no ERROR_ADDRESS available\n");
                 edac_mc_handle_ue_no_info(log_mci, EDAC_MOD_STR);
                 return;
         }
 
-        sys_addr = pvt->ops->get_error_address(mci, info);
+        sys_addr = get_error_address(m);
 
         /*
          * Find out which node the error address belongs to. This may be
@@ -2031,9 +1913,8 @@ static void amd64_handle_ue(struct mem_ctl_info *mci,
          */
         src_mci = find_mc_by_sys_addr(mci, sys_addr);
         if (!src_mci) {
-                amd64_mc_printk(mci, KERN_CRIT,
-                        "ERROR ADDRESS (0x%lx) value NOT mapped to a MC\n",
-                        (unsigned long)sys_addr);
+                amd64_mc_err(mci, "ERROR ADDRESS (0x%lx) NOT mapped to a MC\n",
+                                  (unsigned long)sys_addr);
                 edac_mc_handle_ue_no_info(log_mci, EDAC_MOD_STR);
                 return;
         }
@@ -2042,9 +1923,8 @@ static void amd64_handle_ue(struct mem_ctl_info *mci,
 
         csrow = sys_addr_to_csrow(log_mci, sys_addr);
         if (csrow < 0) {
-                amd64_mc_printk(mci, KERN_CRIT,
-                        "ERROR_ADDRESS (0x%lx) value NOT mapped to 'csrow'\n",
-                        (unsigned long)sys_addr);
+                amd64_mc_err(mci, "ERROR_ADDRESS (0x%lx) NOT mapped to CS\n",
+                                  (unsigned long)sys_addr);
                 edac_mc_handle_ue_no_info(log_mci, EDAC_MOD_STR);
         } else {
                 error_address_to_page_and_offset(sys_addr, &page, &offset);
@@ -2053,14 +1933,14 @@ static void amd64_handle_ue(struct mem_ctl_info *mci,
 }
 
 static inline void __amd64_decode_bus_error(struct mem_ctl_info *mci,
-                                            struct err_regs *info)
+                                            struct mce *m)
 {
-        u32 ec  = ERROR_CODE(info->nbsl);
-        u32 xec = EXT_ERROR_CODE(info->nbsl);
-        int ecc_type = (info->nbsh >> 13) & 0x3;
+        u16 ec = EC(m->status);
+        u8 xec = XEC(m->status, 0x1f);
+        u8 ecc_type = (m->status >> 45) & 0x3;
 
         /* Bail early out if this was an 'observed' error */
-        if (PP(ec) == K8_NBSL_PP_OBS)
+        if (PP(ec) == NBSL_PP_OBS)
                 return;
 
         /* Do only ECC errors */
@@ -2068,103 +1948,68 @@ static inline void __amd64_decode_bus_error(struct mem_ctl_info *mci,
                 return;
 
         if (ecc_type == 2)
-                amd64_handle_ce(mci, info);
+                amd64_handle_ce(mci, m);
         else if (ecc_type == 1)
-                amd64_handle_ue(mci, info);
+                amd64_handle_ue(mci, m);
 }
 
-void amd64_decode_bus_error(int node_id, struct err_regs *regs)
+void amd64_decode_bus_error(int node_id, struct mce *m, u32 nbcfg)
 {
-        struct mem_ctl_info *mci = mci_lookup[node_id];
-
-        __amd64_decode_bus_error(mci, regs);
-
-        /*
-         * Check the UE bit of the NB status high register, if set generate some
-         * logs. If NOT a GART error, then process the event as a NO-INFO event.
-         * If it was a GART error, skip that process.
-         *
-         * FIXME: this should go somewhere else, if at all.
-         */
-        if (regs->nbsh & K8_NBSH_UC_ERR && !report_gart_errors)
-                edac_mc_handle_ue_no_info(mci, "UE bit is set");
+        struct mem_ctl_info *mci = mcis[node_id];
 
+        __amd64_decode_bus_error(mci, m);
 }
 
 /*
- * Input:
- *      1) struct amd64_pvt which contains pvt->dram_f2_ctl pointer
- *      2) AMD Family index value
- *
- * Ouput:
- *      Upon return of 0, the following filled in:
- *
- *              struct pvt->addr_f1_ctl
- *              struct pvt->misc_f3_ctl
- *
- *      Filled in with related device funcitions of 'dram_f2_ctl'
- *      These devices are "reserved" via the pci_get_device()
- *
- *      Upon return of 1 (error status):
- *
- *              Nothing reserved
+ * Use pvt->F2 which contains the F2 CPU PCI device to get the related
+ * F1 (AddrMap) and F3 (Misc) devices. Return negative value on error.
  */
-static int amd64_reserve_mc_sibling_devices(struct amd64_pvt *pvt, int mc_idx)
+static int reserve_mc_sibling_devs(struct amd64_pvt *pvt, u16 f1_id, u16 f3_id)
 {
-        const struct amd64_family_type *amd64_dev = &amd64_family_types[mc_idx];
-
         /* Reserve the ADDRESS MAP Device */
-        pvt->addr_f1_ctl = pci_get_related_function(pvt->dram_f2_ctl->vendor,
-                                                    amd64_dev->addr_f1_ctl,
-                                                    pvt->dram_f2_ctl);
-
-        if (!pvt->addr_f1_ctl) {
-                amd64_printk(KERN_ERR, "error address map device not found: "
-                             "vendor %x device 0x%x (broken BIOS?)\n",
-                             PCI_VENDOR_ID_AMD, amd64_dev->addr_f1_ctl);
-                return 1;
+        pvt->F1 = pci_get_related_function(pvt->F2->vendor, f1_id, pvt->F2);
+        if (!pvt->F1) {
+                amd64_err("error address map device not found: "
+                          "vendor %x device 0x%x (broken BIOS?)\n",
+                          PCI_VENDOR_ID_AMD, f1_id);
+                return -ENODEV;
         }
 
         /* Reserve the MISC Device */
-        pvt->misc_f3_ctl = pci_get_related_function(pvt->dram_f2_ctl->vendor,
-                                                    amd64_dev->misc_f3_ctl,
-                                                    pvt->dram_f2_ctl);
+        pvt->F3 = pci_get_related_function(pvt->F2->vendor, f3_id, pvt->F2);
+        if (!pvt->F3) {
+                pci_dev_put(pvt->F1);
+                pvt->F1 = NULL;
 
-        if (!pvt->misc_f3_ctl) {
-                pci_dev_put(pvt->addr_f1_ctl);
-                pvt->addr_f1_ctl = NULL;
+                amd64_err("error F3 device not found: "
+                          "vendor %x device 0x%x (broken BIOS?)\n",
+                          PCI_VENDOR_ID_AMD, f3_id);
 
-                amd64_printk(KERN_ERR, "error miscellaneous device not found: "
-                             "vendor %x device 0x%x (broken BIOS?)\n",
-                             PCI_VENDOR_ID_AMD, amd64_dev->misc_f3_ctl);
-                return 1;
+                return -ENODEV;
         }
-
-        debugf1("    Addr Map device PCI Bus ID:\t%s\n",
-                pci_name(pvt->addr_f1_ctl));
-        debugf1("    DRAM MEM-CTL PCI Bus ID:\t%s\n",
-                pci_name(pvt->dram_f2_ctl));
-        debugf1("    Misc device PCI Bus ID:\t%s\n",
-                pci_name(pvt->misc_f3_ctl));
+        debugf1("F1: %s\n", pci_name(pvt->F1));
+        debugf1("F2: %s\n", pci_name(pvt->F2));
+        debugf1("F3: %s\n", pci_name(pvt->F3));
 
         return 0;
 }
 
-static void amd64_free_mc_sibling_devices(struct amd64_pvt *pvt)
+static void free_mc_sibling_devs(struct amd64_pvt *pvt)
 {
-        pci_dev_put(pvt->addr_f1_ctl);
-        pci_dev_put(pvt->misc_f3_ctl);
+        pci_dev_put(pvt->F1);
+        pci_dev_put(pvt->F3);
 }
 
 /*
  * Retrieve the hardware registers of the memory controller (this includes the
  * 'Address Map' and 'Misc' device regs)
  */
-static void amd64_read_mc_registers(struct amd64_pvt *pvt)
+static void read_mc_regs(struct amd64_pvt *pvt)
 {
+        struct cpuinfo_x86 *c = &boot_cpu_data;
         u64 msr_val;
         u32 tmp;
-        int dram;
+        unsigned range;
 
         /*
          * Retrieve TOP_MEM and TOP_MEM2; no masking off of reserved bits since
@@ -2181,78 +2026,66 @@ static void amd64_read_mc_registers(struct amd64_pvt *pvt)
         } else
                 debugf0("  TOP_MEM2 disabled.\n");
 
-        amd64_cpu_display_info(pvt);
+        amd64_read_pci_cfg(pvt->F3, NBCAP, &pvt->nbcap);
 
-        amd64_read_pci_cfg(pvt->misc_f3_ctl, K8_NBCAP, &pvt->nbcap);
+        read_dram_ctl_register(pvt);
 
-        if (pvt->ops->read_dram_ctl_register)
-                pvt->ops->read_dram_ctl_register(pvt);
+        for (range = 0; range < DRAM_RANGES; range++) {
+                u8 rw;
 
-        for (dram = 0; dram < DRAM_REG_COUNT; dram++) {
-                /*
-                 * Call CPU specific READ function to get the DRAM Base and
-                 * Limit values from the DCT.
-                 */
-                pvt->ops->read_dram_base_limit(pvt, dram);
+                /* read settings for this DRAM range */
+                read_dram_base_limit_regs(pvt, range);
 
-                /*
-                 * Only print out debug info on rows with both R and W Enabled.
-                 * Normal processing, compiler should optimize this whole 'if'
-                 * debug output block away.
-                 */
-                if (pvt->dram_rw_en[dram] != 0) {
-                        debugf1("  DRAM-BASE[%d]: 0x%016llx "
-                                "DRAM-LIMIT:  0x%016llx\n",
-                                dram,
-                                pvt->dram_base[dram],
-                                pvt->dram_limit[dram]);
-
-                        debugf1("        IntlvEn=%s %s %s "
-                                "IntlvSel=%d DstNode=%d\n",
-                                pvt->dram_IntlvEn[dram] ?
-                                        "Enabled" : "Disabled",
-                                (pvt->dram_rw_en[dram] & 0x2) ? "W" : "!W",
-                                (pvt->dram_rw_en[dram] & 0x1) ? "R" : "!R",
-                                pvt->dram_IntlvSel[dram],
-                                pvt->dram_DstNode[dram]);
-                }
+                rw = dram_rw(pvt, range);
+                if (!rw)
+                        continue;
+
+                debugf1("  DRAM range[%d], base: 0x%016llx; limit: 0x%016llx\n",
+                        range,
+                        get_dram_base(pvt, range),
+                        get_dram_limit(pvt, range));
+
+                debugf1("   IntlvEn=%s; Range access: %s%s IntlvSel=%d DstNode=%d\n",
+                        dram_intlv_en(pvt, range) ? "Enabled" : "Disabled",
+                        (rw & 0x1) ? "R" : "-",
+                        (rw & 0x2) ? "W" : "-",
+                        dram_intlv_sel(pvt, range),
+                        dram_dst_node(pvt, range));
         }
 
-        amd64_read_dct_base_mask(pvt);
+        read_dct_base_mask(pvt);
 
-        amd64_read_pci_cfg(pvt->addr_f1_ctl, K8_DHAR, &pvt->dhar);
-        amd64_read_dbam_reg(pvt);
+        amd64_read_pci_cfg(pvt->F1, DHAR, &pvt->dhar);
+        amd64_read_dct_pci_cfg(pvt, DBAM0, &pvt->dbam0);
 
-        amd64_read_pci_cfg(pvt->misc_f3_ctl,
-                           F10_ONLINE_SPARE, &pvt->online_spare);
+        amd64_read_pci_cfg(pvt->F3, F10_ONLINE_SPARE, &pvt->online_spare);
 
-        amd64_read_pci_cfg(pvt->dram_f2_ctl, F10_DCLR_0, &pvt->dclr0);
-        amd64_read_pci_cfg(pvt->dram_f2_ctl, F10_DCHR_0, &pvt->dchr0);
+        amd64_read_dct_pci_cfg(pvt, DCLR0, &pvt->dclr0);
+        amd64_read_dct_pci_cfg(pvt, DCHR0, &pvt->dchr0);
 
-        if (boot_cpu_data.x86 >= 0x10) {
-                if (!dct_ganging_enabled(pvt)) {
-                        amd64_read_pci_cfg(pvt->dram_f2_ctl, F10_DCLR_1, &pvt->dclr1);
-                        amd64_read_pci_cfg(pvt->dram_f2_ctl, F10_DCHR_1, &pvt->dchr1);
-                }
-                amd64_read_pci_cfg(pvt->misc_f3_ctl, EXT_NB_MCA_CFG, &tmp);
+        if (!dct_ganging_enabled(pvt)) {
+                amd64_read_dct_pci_cfg(pvt, DCLR1, &pvt->dclr1);
+                amd64_read_dct_pci_cfg(pvt, DCHR1, &pvt->dchr1);
         }
 
-        if (boot_cpu_data.x86 == 0x10 &&
-            boot_cpu_data.x86_model > 7 &&
-            /* F3x180[EccSymbolSize]=1 => x8 symbols */
-            tmp & BIT(25))
-                pvt->syn_type = 8;
-        else
-                pvt->syn_type = 4;
+        pvt->ecc_sym_sz = 4;
+
+        if (c->x86 >= 0x10) {
+                amd64_read_pci_cfg(pvt->F3, EXT_NB_MCA_CFG, &tmp);
+                amd64_read_dct_pci_cfg(pvt, DBAM1, &pvt->dbam1);
 
-        amd64_dump_misc_regs(pvt);
+                /* F10h, revD and later can do x8 ECC too */
+                if ((c->x86 > 0x10 || c->x86_model > 7) && tmp & BIT(25))
+                        pvt->ecc_sym_sz = 8;
+        }
+        dump_misc_regs(pvt);
 }
 
 /*
  * NOTE: CPU Revision Dependent code
  *
  * Input:
- *      @csrow_nr ChipSelect Row Number (0..pvt->cs_count-1)
+ *      @csrow_nr ChipSelect Row Number (0..NUM_CHIPSELECTS-1)
  *      k8 private pointer to -->
  *                      DRAM Bank Address mapping register
  *                      node_id
@@ -2282,7 +2115,7 @@ static void amd64_read_mc_registers(struct amd64_pvt *pvt)
  *      encompasses
  *
  */
-static u32 amd64_csrow_nr_pages(int csrow_nr, struct amd64_pvt *pvt)
+static u32 amd64_csrow_nr_pages(struct amd64_pvt *pvt, u8 dct, int csrow_nr)
 {
         u32 cs_mode, nr_pages;
 
@@ -2295,7 +2128,7 @@ static u32 amd64_csrow_nr_pages(int csrow_nr, struct amd64_pvt *pvt)
          */
         cs_mode = (pvt->dbam0 >> ((csrow_nr / 2) * 4)) & 0xF;
 
-        nr_pages = pvt->ops->dbam_to_cs(pvt, cs_mode) << (20 - PAGE_SHIFT);
+        nr_pages = pvt->ops->dbam_to_cs(pvt, dct, cs_mode) << (20 - PAGE_SHIFT);
 
         /*
          * If dual channel then double the memory size of single channel.
@@ -2314,26 +2147,26 @@ static u32 amd64_csrow_nr_pages(int csrow_nr, struct amd64_pvt *pvt)
  * Initialize the array of csrow attribute instances, based on the values
  * from pci config hardware registers.
  */
-static int amd64_init_csrows(struct mem_ctl_info *mci)
+static int init_csrows(struct mem_ctl_info *mci)
 {
         struct csrow_info *csrow;
-        struct amd64_pvt *pvt;
-        u64 input_addr_min, input_addr_max, sys_addr;
+        struct amd64_pvt *pvt = mci->pvt_info;
+        u64 input_addr_min, input_addr_max, sys_addr, base, mask;
+        u32 val;
         int i, empty = 1;
 
-        pvt = mci->pvt_info;
+        amd64_read_pci_cfg(pvt->F3, NBCFG, &val);
 
-        amd64_read_pci_cfg(pvt->misc_f3_ctl, K8_NBCFG, &pvt->nbcfg);
+        pvt->nbcfg = val;
 
-        debugf0("NBCFG= 0x%x  CHIPKILL= %s DRAM ECC= %s\n", pvt->nbcfg,
-                (pvt->nbcfg & K8_NBCFG_CHIPKILL) ? "Enabled" : "Disabled",
-                (pvt->nbcfg & K8_NBCFG_ECC_ENABLE) ? "Enabled" : "Disabled"
-                );
+        debugf0("node %d, NBCFG=0x%08x[ChipKillEccCap: %d|DramEccEn: %d]\n",
+                pvt->mc_node_id, val,
+                !!(val & NBCFG_CHIPKILL), !!(val & NBCFG_ECC_ENABLE));
 
-        for (i = 0; i < pvt->cs_count; i++) {
+        for_each_chip_select(i, 0, pvt) {
                 csrow = &mci->csrows[i];
 
-                if ((pvt->dcsb0[i] & K8_DCSB_CS_ENABLE) == 0) {
+                if (!csrow_enabled(i, 0, pvt)) {
                         debugf1("----CSROW %d EMPTY for node %d\n", i,
                                 pvt->mc_node_id);
                         continue;
@@ -2343,16 +2176,18 @@ static int amd64_init_csrows(struct mem_ctl_info *mci)
                         i, pvt->mc_node_id);
 
                 empty = 0;
-                csrow->nr_pages = amd64_csrow_nr_pages(i, pvt);
+                csrow->nr_pages = amd64_csrow_nr_pages(pvt, 0, i);
                 find_csrow_limits(mci, i, &input_addr_min, &input_addr_max);
                 sys_addr = input_addr_to_sys_addr(mci, input_addr_min);
                 csrow->first_page = (u32) (sys_addr >> PAGE_SHIFT);
                 sys_addr = input_addr_to_sys_addr(mci, input_addr_max);
                 csrow->last_page = (u32) (sys_addr >> PAGE_SHIFT);
-                csrow->page_mask = ~mask_from_dct_mask(pvt, i);
+
+                get_cs_base_and_mask(pvt, i, 0, &base, &mask);
+                csrow->page_mask = ~mask;
                 /* 8 bytes of resolution */
 
-                csrow->mtype = amd64_determine_memory_type(pvt);
+                csrow->mtype = amd64_determine_memory_type(pvt, i);
 
                 debugf1("  for MC node %d csrow %d:\n", pvt->mc_node_id, i);
                 debugf1("    input_addr_min: 0x%lx input_addr_max: 0x%lx\n",
@@ -2368,9 +2203,9 @@ static int amd64_init_csrows(struct mem_ctl_info *mci)
                 /*
                  * determine whether CHIPKILL or JUST ECC or NO ECC is operating
                  */
-                if (pvt->nbcfg & K8_NBCFG_ECC_ENABLE)
+                if (pvt->nbcfg & NBCFG_ECC_ENABLE)
                         csrow->edac_mode =
-                            (pvt->nbcfg & K8_NBCFG_CHIPKILL) ?
+                            (pvt->nbcfg & NBCFG_CHIPKILL) ?
                             EDAC_S4ECD4ED : EDAC_SECDED;
                 else
                         csrow->edac_mode = EDAC_NONE;
@@ -2380,7 +2215,7 @@ static int amd64_init_csrows(struct mem_ctl_info *mci)
 }
 
 /* get all cores on this DCT */
-static void get_cpus_on_this_dct_cpumask(struct cpumask *mask, int nid)
+static void get_cpus_on_this_dct_cpumask(struct cpumask *mask, unsigned nid)
 {
         int cpu;
 
@@ -2390,15 +2225,14 @@ static void get_cpus_on_this_dct_cpumask(struct cpumask *mask, int nid)
 }
 
 /* check MCG_CTL on all the cpus on this node */
-static bool amd64_nb_mce_bank_enabled_on_node(int nid)
+static bool amd64_nb_mce_bank_enabled_on_node(unsigned nid)
 {
         cpumask_var_t mask;
         int cpu, nbe;
         bool ret = false;
 
         if (!zalloc_cpumask_var(&mask, GFP_KERNEL)) {
-                amd64_printk(KERN_WARNING, "%s: error allocating mask\n",
-                             __func__);
+                amd64_warn("%s: Error allocating mask\n", __func__);
                 return false;
         }
 
@@ -2408,7 +2242,7 @@ static bool amd64_nb_mce_bank_enabled_on_node(int nid)
 
         for_each_cpu(cpu, mask) {
                 struct msr *reg = per_cpu_ptr(msrs, cpu);
-                nbe = reg->l & K8_MSR_MCGCTL_NBE;
+                nbe = reg->l & MSR_MCGCTL_NBE;
 
                 debugf0("core: %u, MCG_CTL: 0x%llx, NB MSR is %s\n",
                         cpu, reg->q,
@@ -2424,18 +2258,17 @@ out:
         return ret;
 }
 
-static int amd64_toggle_ecc_err_reporting(struct amd64_pvt *pvt, bool on)
+static int toggle_ecc_err_reporting(struct ecc_settings *s, u8 nid, bool on)
 {
         cpumask_var_t cmask;
         int cpu;
 
         if (!zalloc_cpumask_var(&cmask, GFP_KERNEL)) {
-                amd64_printk(KERN_WARNING, "%s: error allocating mask\n",
-                             __func__);
+                amd64_warn("%s: error allocating mask\n", __func__);
                 return false;
         }
 
-        get_cpus_on_this_dct_cpumask(cmask, pvt->mc_node_id);
+        get_cpus_on_this_dct_cpumask(cmask, nid);
 
         rdmsr_on_cpus(cmask, MSR_IA32_MCG_CTL, msrs);
 
@@ -2444,16 +2277,16 @@ static int amd64_toggle_ecc_err_reporting(struct amd64_pvt *pvt, bool on)
                 struct msr *reg = per_cpu_ptr(msrs, cpu);
 
                 if (on) {
-                        if (reg->l & K8_MSR_MCGCTL_NBE)
-                                pvt->flags.nb_mce_enable = 1;
+                        if (reg->l & MSR_MCGCTL_NBE)
+                                s->flags.nb_mce_enable = 1;
 
-                        reg->l |= K8_MSR_MCGCTL_NBE;
+                        reg->l |= MSR_MCGCTL_NBE;
                 } else {
                         /*
                          * Turn off NB MCE reporting only when it was off before
                          */
-                        if (!pvt->flags.nb_mce_enable)
-                                reg->l &= ~K8_MSR_MCGCTL_NBE;
+                        if (!s->flags.nb_mce_enable)
+                                reg->l &= ~MSR_MCGCTL_NBE;
                 }
         }
         wrmsr_on_cpus(cmask, MSR_IA32_MCG_CTL, msrs);
@@ -2463,92 +2296,90 @@ static int amd64_toggle_ecc_err_reporting(struct amd64_pvt *pvt, bool on)
         return 0;
 }
 
-static void amd64_enable_ecc_error_reporting(struct mem_ctl_info *mci)
+static bool enable_ecc_error_reporting(struct ecc_settings *s, u8 nid,
+                                       struct pci_dev *F3)
 {
-        struct amd64_pvt *pvt = mci->pvt_info;
-        u32 value, mask = K8_NBCTL_CECCEn | K8_NBCTL_UECCEn;
+        bool ret = true;
+        u32 value, mask = 0x3;          /* UECC/CECC enable */
+
+        if (toggle_ecc_err_reporting(s, nid, ON)) {
+                amd64_warn("Error enabling ECC reporting over MCGCTL!\n");
+                return false;
+        }
 
-        amd64_read_pci_cfg(pvt->misc_f3_ctl, K8_NBCTL, &value);
+        amd64_read_pci_cfg(F3, NBCTL, &value);
 
-        /* turn on UECCn and CECCEn bits */
-        pvt->old_nbctl = value & mask;
-        pvt->nbctl_mcgctl_saved = 1;
+        s->old_nbctl   = value & mask;
+        s->nbctl_valid = true;
 
         value |= mask;
-        pci_write_config_dword(pvt->misc_f3_ctl, K8_NBCTL, value);
+        amd64_write_pci_cfg(F3, NBCTL, value);
 
-        if (amd64_toggle_ecc_err_reporting(pvt, ON))
-                amd64_printk(KERN_WARNING, "Error enabling ECC reporting over "
-                                           "MCGCTL!\n");
+        amd64_read_pci_cfg(F3, NBCFG, &value);
 
-        amd64_read_pci_cfg(pvt->misc_f3_ctl, K8_NBCFG, &value);
+        debugf0("1: node %d, NBCFG=0x%08x[DramEccEn: %d]\n",
+                nid, value, !!(value & NBCFG_ECC_ENABLE));
 
-        debugf0("NBCFG(1)= 0x%x  CHIPKILL= %s ECC_ENABLE= %s\n", value,
-                (value & K8_NBCFG_CHIPKILL) ? "Enabled" : "Disabled",
-                (value & K8_NBCFG_ECC_ENABLE) ? "Enabled" : "Disabled");
+        if (!(value & NBCFG_ECC_ENABLE)) {
+                amd64_warn("DRAM ECC disabled on this node, enabling...\n");
 
-        if (!(value & K8_NBCFG_ECC_ENABLE)) {
-                amd64_printk(KERN_WARNING,
-                        "This node reports that DRAM ECC is "
-                        "currently Disabled; ENABLING now\n");
-
-                pvt->flags.nb_ecc_prev = 0;
+                s->flags.nb_ecc_prev = 0;
 
                 /* Attempt to turn on DRAM ECC Enable */
-                value |= K8_NBCFG_ECC_ENABLE;
-                pci_write_config_dword(pvt->misc_f3_ctl, K8_NBCFG, value);
+                value |= NBCFG_ECC_ENABLE;
+                amd64_write_pci_cfg(F3, NBCFG, value);
 
-                amd64_read_pci_cfg(pvt->misc_f3_ctl, K8_NBCFG, &value);
+                amd64_read_pci_cfg(F3, NBCFG, &value);
 
-                if (!(value & K8_NBCFG_ECC_ENABLE)) {
-                        amd64_printk(KERN_WARNING,
-                                "Hardware rejects Enabling DRAM ECC checking\n"
-                                "Check memory DIMM configuration\n");
+                if (!(value & NBCFG_ECC_ENABLE)) {
+                        amd64_warn("Hardware rejected DRAM ECC enable,"
+                                   "check memory DIMM configuration.\n");
+                        ret = false;
                 } else {
-                        amd64_printk(KERN_DEBUG,
-                                "Hardware accepted DRAM ECC Enable\n");
+                        amd64_info("Hardware accepted DRAM ECC Enable\n");
                 }
         } else {
-                pvt->flags.nb_ecc_prev = 1;
+                s->flags.nb_ecc_prev = 1;
         }
 
-        debugf0("NBCFG(2)= 0x%x  CHIPKILL= %s ECC_ENABLE= %s\n", value,
-                (value & K8_NBCFG_CHIPKILL) ? "Enabled" : "Disabled",
-                (value & K8_NBCFG_ECC_ENABLE) ? "Enabled" : "Disabled");
+        debugf0("2: node %d, NBCFG=0x%08x[DramEccEn: %d]\n",
+                nid, value, !!(value & NBCFG_ECC_ENABLE));
 
-        pvt->ctl_error_info.nbcfg = value;
+        return ret;
 }
 
-static void amd64_restore_ecc_error_reporting(struct amd64_pvt *pvt)
+static void restore_ecc_error_reporting(struct ecc_settings *s, u8 nid,
+                                        struct pci_dev *F3)
 {
-        u32 value, mask = K8_NBCTL_CECCEn | K8_NBCTL_UECCEn;
+        u32 value, mask = 0x3;          /* UECC/CECC enable */
 
-        if (!pvt->nbctl_mcgctl_saved)
+
+        if (!s->nbctl_valid)
                 return;
 
-        amd64_read_pci_cfg(pvt->misc_f3_ctl, K8_NBCTL, &value);
+        amd64_read_pci_cfg(F3, NBCTL, &value);
         value &= ~mask;
-        value |= pvt->old_nbctl;
+        value |= s->old_nbctl;
 
-        pci_write_config_dword(pvt->misc_f3_ctl, K8_NBCTL, value);
+        amd64_write_pci_cfg(F3, NBCTL, value);
 
-        /* restore previous BIOS DRAM ECC "off" setting which we force-enabled */
-        if (!pvt->flags.nb_ecc_prev) {
-                amd64_read_pci_cfg(pvt->misc_f3_ctl, K8_NBCFG, &value);
-                value &= ~K8_NBCFG_ECC_ENABLE;
-                pci_write_config_dword(pvt->misc_f3_ctl, K8_NBCFG, value);
+        /* restore previous BIOS DRAM ECC "off" setting we force-enabled */
+        if (!s->flags.nb_ecc_prev) {
+                amd64_read_pci_cfg(F3, NBCFG, &value);
+                value &= ~NBCFG_ECC_ENABLE;
+                amd64_write_pci_cfg(F3, NBCFG, value);
         }
 
         /* restore the NB Enable MCGCTL bit */
-        if (amd64_toggle_ecc_err_reporting(pvt, OFF))
-                amd64_printk(KERN_WARNING, "Error restoring NB MCGCTL settings!\n");
+        if (toggle_ecc_err_reporting(s, nid, OFF))
+                amd64_warn("Error restoring NB MCGCTL settings!\n");
 }
 
 /*
- * EDAC requires that the BIOS have ECC enabled before taking over the
- * processing of ECC errors. This is because the BIOS can properly initialize
- * the memory system completely. A command line option allows to force-enable
- * hardware ECC later in amd64_enable_ecc_error_reporting().
+ * EDAC requires that the BIOS have ECC enabled before
+ * taking over the processing of ECC errors. A command line
+ * option allows to force-enable hardware ECC later in
+ * enable_ecc_error_reporting().
  */
 static const char *ecc_msg =
         "ECC disabled in the BIOS or no ECC capability, module will not load.\n"
@@ -2556,38 +2387,28 @@ static const char *ecc_msg =
         "'ecc_enable_override'.\n"
         " (Note that use of the override may cause unknown side effects.)\n";
 
-static int amd64_check_ecc_enabled(struct amd64_pvt *pvt)
+static bool ecc_enabled(struct pci_dev *F3, u8 nid)
 {
         u32 value;
-        u8 ecc_enabled = 0;
+        u8 ecc_en = 0;
         bool nb_mce_en = false;
 
-        amd64_read_pci_cfg(pvt->misc_f3_ctl, K8_NBCFG, &value);
+        amd64_read_pci_cfg(F3, NBCFG, &value);
 
-        ecc_enabled = !!(value & K8_NBCFG_ECC_ENABLE);
-        if (!ecc_enabled)
-                amd64_printk(KERN_NOTICE, "This node reports that Memory ECC "
-                             "is currently disabled, set F3x%x[22] (%s).\n",
-                             K8_NBCFG, pci_name(pvt->misc_f3_ctl));
-        else
-                amd64_printk(KERN_INFO, "ECC is enabled by BIOS.\n");
+        ecc_en = !!(value & NBCFG_ECC_ENABLE);
+        amd64_info("DRAM ECC %s.\n", (ecc_en ? "enabled" : "disabled"));
 
-        nb_mce_en = amd64_nb_mce_bank_enabled_on_node(pvt->mc_node_id);
+        nb_mce_en = amd64_nb_mce_bank_enabled_on_node(nid);
         if (!nb_mce_en)
-                amd64_printk(KERN_NOTICE, "NB MCE bank disabled, set MSR "
+                amd64_notice("NB MCE bank disabled, set MSR "
                              "0x%08x[4] on node %d to enable.\n",
-                             MSR_IA32_MCG_CTL, pvt->mc_node_id);
+                             MSR_IA32_MCG_CTL, nid);
 
-        if (!ecc_enabled || !nb_mce_en) {
-                if (!ecc_enable_override) {
-                        amd64_printk(KERN_NOTICE, "%s", ecc_msg);
-                        return -ENODEV;
-                } else {
-                        amd64_printk(KERN_WARNING, "Forcing ECC checking on!\n");
-                }
+        if (!ecc_en || !nb_mce_en) {
+                amd64_notice("%s", ecc_msg);
+                return false;
         }
-
-        return 0;
+        return true;
 }
 
 struct mcidev_sysfs_attribute sysfs_attrs[ARRAY_SIZE(amd64_dbg_attrs) +
@@ -2596,39 +2417,41 @@ struct mcidev_sysfs_attribute sysfs_attrs[ARRAY_SIZE(amd64_dbg_attrs) +
 
 struct mcidev_sysfs_attribute terminator = { .attr = { .name = NULL } };
 
-static void amd64_set_mc_sysfs_attributes(struct mem_ctl_info *mci)
+static void set_mc_sysfs_attrs(struct mem_ctl_info *mci)
 {
         unsigned int i = 0, j = 0;
 
         for (; i < ARRAY_SIZE(amd64_dbg_attrs); i++)
                 sysfs_attrs[i] = amd64_dbg_attrs[i];
 
-        for (j = 0; j < ARRAY_SIZE(amd64_inj_attrs); j++, i++)
-                sysfs_attrs[i] = amd64_inj_attrs[j];
+        if (boot_cpu_data.x86 >= 0x10)
+                for (j = 0; j < ARRAY_SIZE(amd64_inj_attrs); j++, i++)
+                        sysfs_attrs[i] = amd64_inj_attrs[j];
 
         sysfs_attrs[i] = terminator;
 
         mci->mc_driver_sysfs_attributes = sysfs_attrs;
 }
 
-static void amd64_setup_mci_misc_attributes(struct mem_ctl_info *mci)
+static void setup_mci_misc_attrs(struct mem_ctl_info *mci,
+                                 struct amd64_family_type *fam)
 {
         struct amd64_pvt *pvt = mci->pvt_info;
 
         mci->mtype_cap          = MEM_FLAG_DDR2 | MEM_FLAG_RDDR2;
         mci->edac_ctl_cap       = EDAC_FLAG_NONE;
 
-        if (pvt->nbcap & K8_NBCAP_SECDED)
+        if (pvt->nbcap & NBCAP_SECDED)
                 mci->edac_ctl_cap |= EDAC_FLAG_SECDED;
 
-        if (pvt->nbcap & K8_NBCAP_CHIPKILL)
+        if (pvt->nbcap & NBCAP_CHIPKILL)
                 mci->edac_ctl_cap |= EDAC_FLAG_S4ECD4ED;
 
         mci->edac_cap           = amd64_determine_edac_cap(pvt);
         mci->mod_name           = EDAC_MOD_STR;
         mci->mod_ver            = EDAC_AMD64_VERSION;
-        mci->ctl_name           = get_amd_family_name(pvt->mc_type_index);
-        mci->dev_name           = pci_name(pvt->dram_f2_ctl);
+        mci->ctl_name           = fam->ctl_name;
+        mci->dev_name           = pci_name(pvt->F2);
         mci->ctl_page_to_phys   = NULL;
 
         /* memory scrubber interface */
@@ -2637,111 +2460,96 @@ static void amd64_setup_mci_misc_attributes(struct mem_ctl_info *mci)
 }
 
 /*
- * Init stuff for this DRAM Controller device.
- *
- * Due to a hardware feature on Fam10h CPUs, the Enable Extended Configuration
- * Space feature MUST be enabled on ALL Processors prior to actually reading
- * from the ECS registers. Since the loading of the module can occur on any
- * 'core', and cores don't 'see' all the other processors ECS data when the
- * others are NOT enabled. Our solution is to first enable ECS access in this
- * routine on all processors, gather some data in a amd64_pvt structure and
- * later come back in a finish-setup function to perform that final
- * initialization. See also amd64_init_2nd_stage() for that.
+ * returns a pointer to the family descriptor on success, NULL otherwise.
  */
-static int amd64_probe_one_instance(struct pci_dev *dram_f2_ctl,
-                                    int mc_type_index)
+static struct amd64_family_type *amd64_per_family_init(struct amd64_pvt *pvt)
+{
+        u8 fam = boot_cpu_data.x86;
+        struct amd64_family_type *fam_type = NULL;
+
+        switch (fam) {
+        case 0xf:
+                fam_type                = &amd64_family_types[K8_CPUS];
+                pvt->ops                = &amd64_family_types[K8_CPUS].ops;
+                break;
+
+        case 0x10:
+                fam_type                = &amd64_family_types[F10_CPUS];
+                pvt->ops                = &amd64_family_types[F10_CPUS].ops;
+                break;
+
+        case 0x15:
+                fam_type                = &amd64_family_types[F15_CPUS];
+                pvt->ops                = &amd64_family_types[F15_CPUS].ops;
+                break;
+
+        default:
+                amd64_err("Unsupported family!\n");
+                return NULL;
+        }
+
+        pvt->ext_model = boot_cpu_data.x86_model >> 4;
+
+        amd64_info("%s %sdetected (node %d).\n", fam_type->ctl_name,
+                     (fam == 0xf ?
+                                (pvt->ext_model >= K8_REV_F  ? "revF or later "
+                                                             : "revE or earlier ")
+                                 : ""), pvt->mc_node_id);
+        return fam_type;
+}
+
+static int amd64_init_one_instance(struct pci_dev *F2)
 {
         struct amd64_pvt *pvt = NULL;
+        struct amd64_family_type *fam_type = NULL;
+        struct mem_ctl_info *mci = NULL;
         int err = 0, ret;
+        u8 nid = get_node_id(F2);
 
         ret = -ENOMEM;
         pvt = kzalloc(sizeof(struct amd64_pvt), GFP_KERNEL);
         if (!pvt)
-                goto err_exit;
+                goto err_ret;
 
-        pvt->mc_node_id = get_node_id(dram_f2_ctl);
+        pvt->mc_node_id = nid;
+        pvt->F2 = F2;
 
-        pvt->dram_f2_ctl        = dram_f2_ctl;
-        pvt->ext_model          = boot_cpu_data.x86_model >> 4;
-        pvt->mc_type_index      = mc_type_index;
-        pvt->ops                = family_ops(mc_type_index);
+        ret = -EINVAL;
+        fam_type = amd64_per_family_init(pvt);
+        if (!fam_type)
+                goto err_free;
 
-        /*
-         * We have the dram_f2_ctl device as an argument, now go reserve its
-         * sibling devices from the PCI system.
-         */
         ret = -ENODEV;
-        err = amd64_reserve_mc_sibling_devices(pvt, mc_type_index);
+        err = reserve_mc_sibling_devs(pvt, fam_type->f1_id, fam_type->f3_id);
         if (err)
                 goto err_free;
 
-        ret = -EINVAL;
-        err = amd64_check_ecc_enabled(pvt);
-        if (err)
-                goto err_put;
-
-        /*
-         * Key operation here: setup of HW prior to performing ops on it. Some
-         * setup is required to access ECS data. After this is performed, the
-         * 'teardown' function must be called upon error and normal exit paths.
-         */
-        if (boot_cpu_data.x86 >= 0x10)
-                amd64_setup(pvt);
-
-        /*
-         * Save the pointer to the private data for use in 2nd initialization
-         * stage
-         */
-        pvt_lookup[pvt->mc_node_id] = pvt;
-
-        return 0;
-
-err_put:
-        amd64_free_mc_sibling_devices(pvt);
-
-err_free:
-        kfree(pvt);
-
-err_exit:
-        return ret;
-}
-
-/*
- * This is the finishing stage of the init code. Needs to be performed after all
- * MCs' hardware have been prepped for accessing extended config space.
- */
-static int amd64_init_2nd_stage(struct amd64_pvt *pvt)
-{
-        int node_id = pvt->mc_node_id;
-        struct mem_ctl_info *mci;
-        int ret = -ENODEV;
-
-        amd64_read_mc_registers(pvt);
+        read_mc_regs(pvt);
 
         /*
          * We need to determine how many memory channels there are. Then use
          * that information for calculating the size of the dynamic instance
-         * tables in the 'mci' structure
+         * tables in the 'mci' structure.
          */
+        ret = -EINVAL;
         pvt->channel_count = pvt->ops->early_channel_count(pvt);
         if (pvt->channel_count < 0)
-                goto err_exit;
+                goto err_siblings;
 
         ret = -ENOMEM;
-        mci = edac_mc_alloc(0, pvt->cs_count, pvt->channel_count, node_id);
+        mci = edac_mc_alloc(0, pvt->csels[0].b_cnt, pvt->channel_count, nid);
         if (!mci)
-                goto err_exit;
+                goto err_siblings;
 
         mci->pvt_info = pvt;
+        mci->dev = &pvt->F2->dev;
 
-        mci->dev = &pvt->dram_f2_ctl->dev;
-        amd64_setup_mci_misc_attributes(mci);
+        setup_mci_misc_attrs(mci, fam_type);
 
-        if (amd64_init_csrows(mci))
+        if (init_csrows(mci))
                 mci->edac_cap = EDAC_FLAG_NONE;
 
-        amd64_enable_ecc_error_reporting(mci);
-        amd64_set_mc_sysfs_attributes(mci);
+        set_mc_sysfs_attrs(mci);
 
         ret = -ENODEV;
         if (edac_mc_add_mc(mci)) {
@@ -2749,54 +2557,77 @@ static int amd64_init_2nd_stage(struct amd64_pvt *pvt)
                 goto err_add_mc;
         }
 
-        mci_lookup[node_id] = mci;
-        pvt_lookup[node_id] = NULL;
-
         /* register stuff with EDAC MCE */
         if (report_gart_errors)
                 amd_report_gart_errors(true);
 
         amd_register_ecc_decoder(amd64_decode_bus_error);
 
+        mcis[nid] = mci;
+
+        atomic_inc(&drv_instances);
+
         return 0;
 
 err_add_mc:
         edac_mc_free(mci);
 
-err_exit:
-        debugf0("failure to init 2nd stage: ret=%d\n", ret);
-
-        amd64_restore_ecc_error_reporting(pvt);
-
-        if (boot_cpu_data.x86 > 0xf)
-                amd64_teardown(pvt);
+err_siblings:
+        free_mc_sibling_devs(pvt);
 
-        amd64_free_mc_sibling_devices(pvt);
-
-        kfree(pvt_lookup[pvt->mc_node_id]);
-        pvt_lookup[node_id] = NULL;
+err_free:
+        kfree(pvt);
 
+err_ret:
         return ret;
 }
 
-
-static int __devinit amd64_init_one_instance(struct pci_dev *pdev,
-                                 const struct pci_device_id *mc_type)
+static int __devinit amd64_probe_one_instance(struct pci_dev *pdev,
+                                             const struct pci_device_id *mc_type)
 {
+        u8 nid = get_node_id(pdev);
+        struct pci_dev *F3 = node_to_amd_nb(nid)->misc;
+        struct ecc_settings *s;
         int ret = 0;
 
-        debugf0("(MC node=%d,mc_type='%s')\n", get_node_id(pdev),
-                get_amd_family_name(mc_type->driver_data));
-
         ret = pci_enable_device(pdev);
-        if (ret < 0)
-                ret = -EIO;
-        else
-                ret = amd64_probe_one_instance(pdev, mc_type->driver_data);
-
-        if (ret < 0)
+        if (ret < 0) {
                 debugf0("ret=%d\n", ret);
+                return -EIO;
+        }
+
+        ret = -ENOMEM;
+        s = kzalloc(sizeof(struct ecc_settings), GFP_KERNEL);
+        if (!s)
+                goto err_out;
+
+        ecc_stngs[nid] = s;
+
+        if (!ecc_enabled(F3, nid)) {
+                ret = -ENODEV;
+
+                if (!ecc_enable_override)
+                        goto err_enable;
+
+                amd64_warn("Forcing ECC on!\n");
+
+                if (!enable_ecc_error_reporting(s, nid, F3))
+                        goto err_enable;
+        }
 
+        ret = amd64_init_one_instance(pdev);
+        if (ret < 0) {
+                amd64_err("Error probing instance: %d\n", nid);
+                restore_ecc_error_reporting(s, nid, F3);
+        }
+
+        return ret;
+
+err_enable:
+        kfree(s);
+        ecc_stngs[nid] = NULL;
+
+err_out:
         return ret;
 }
 
@@ -2804,6 +2635,9 @@ static void __devexit amd64_remove_one_instance(struct pci_dev *pdev)
 {
         struct mem_ctl_info *mci;
         struct amd64_pvt *pvt;
+        u8 nid = get_node_id(pdev);
+        struct pci_dev *F3 = node_to_amd_nb(nid)->misc;
+        struct ecc_settings *s = ecc_stngs[nid];
 
         /* Remove from EDAC CORE tracking list */
         mci = edac_mc_del_mc(&pdev->dev);
@@ -2812,20 +2646,20 @@ static void __devexit amd64_remove_one_instance(struct pci_dev *pdev)
 
         pvt = mci->pvt_info;
 
-        amd64_restore_ecc_error_reporting(pvt);
-
-        if (boot_cpu_data.x86 > 0xf)
-                amd64_teardown(pvt);
+        restore_ecc_error_reporting(s, nid, F3);
 
-        amd64_free_mc_sibling_devices(pvt);
+        free_mc_sibling_devs(pvt);
 
         /* unregister from EDAC MCE */
         amd_report_gart_errors(false);
         amd_unregister_ecc_decoder(amd64_decode_bus_error);
 
+        kfree(ecc_stngs[nid]);
+        ecc_stngs[nid] = NULL;
+
         /* Free the EDAC CORE resources */
         mci->pvt_info = NULL;
-        mci_lookup[pvt->mc_node_id] = NULL;
+        mcis[nid] = NULL;
 
         kfree(pvt);
         edac_mc_free(mci);
@@ -2844,7 +2678,6 @@ static const struct pci_device_id amd64_pci_table[] __devinitdata = {
                 .subdevice      = PCI_ANY_ID,
                 .class          = 0,
                 .class_mask     = 0,
-                .driver_data    = K8_CPUS
         },
         {
                 .vendor         = PCI_VENDOR_ID_AMD,
@@ -2853,29 +2686,28 @@ static const struct pci_device_id amd64_pci_table[] __devinitdata = {
                 .subdevice      = PCI_ANY_ID,
                 .class          = 0,
                 .class_mask     = 0,
-                .driver_data    = F10_CPUS
         },
         {
                 .vendor         = PCI_VENDOR_ID_AMD,
-                .device         = PCI_DEVICE_ID_AMD_11H_NB_DRAM,
+                .device         = PCI_DEVICE_ID_AMD_15H_NB_F2,
                 .subvendor      = PCI_ANY_ID,
                 .subdevice      = PCI_ANY_ID,
                 .class          = 0,
                 .class_mask     = 0,
-                .driver_data    = F11_CPUS
         },
+
         {0, }
 };
 MODULE_DEVICE_TABLE(pci, amd64_pci_table);
 
 static struct pci_driver amd64_pci_driver = {
         .name           = EDAC_MOD_STR,
-        .probe          = amd64_init_one_instance,
+        .probe          = amd64_probe_one_instance,
         .remove         = __devexit_p(amd64_remove_one_instance),
         .id_table       = amd64_pci_table,
 };
 
-static void amd64_setup_pci_device(void)
+static void setup_pci_device(void)
 {
         struct mem_ctl_info *mci;
         struct amd64_pvt *pvt;
@@ -2883,13 +2715,12 @@ static void amd64_setup_pci_device(void)
         if (amd64_ctl_pci)
                 return;
 
-        mci = mci_lookup[0];
+        mci = mcis[0];
         if (mci) {
 
                 pvt = mci->pvt_info;
                 amd64_ctl_pci =
-                        edac_pci_create_generic_ctl(&pvt->dram_f2_ctl->dev,
-                                                    EDAC_MOD_STR);
+                        edac_pci_create_generic_ctl(&pvt->F2->dev, EDAC_MOD_STR);
 
                 if (!amd64_ctl_pci) {
                         pr_warning("%s(): Unable to create PCI control\n",
@@ -2903,51 +2734,50 @@ static void amd64_setup_pci_device(void)
 
 static int __init amd64_edac_init(void)
 {
-        int nb, err = -ENODEV;
-        bool load_ok = false;
+        int err = -ENODEV;
 
-        edac_printk(KERN_INFO, EDAC_MOD_STR, EDAC_AMD64_VERSION "\n");
+        printk(KERN_INFO "AMD64 EDAC driver v%s\n", EDAC_AMD64_VERSION);
 
         opstate_init();
 
-        if (cache_k8_northbridges() < 0)
+        if (amd_cache_northbridges() < 0)
                 goto err_ret;
 
+        err = -ENOMEM;
+        mcis      = kzalloc(amd_nb_num() * sizeof(mcis[0]), GFP_KERNEL);
+        ecc_stngs = kzalloc(amd_nb_num() * sizeof(ecc_stngs[0]), GFP_KERNEL);
+        if (!(mcis && ecc_stngs))
+                goto err_free;
+
         msrs = msrs_alloc();
         if (!msrs)
-                goto err_ret;
+                goto err_free;
 
         err = pci_register_driver(&amd64_pci_driver);
         if (err)
                 goto err_pci;
 
-        /*
-         * At this point, the array 'pvt_lookup[]' contains pointers to alloc'd
-         * amd64_pvt structs. These will be used in the 2nd stage init function
-         * to finish initialization of the MC instances.
-         */
         err = -ENODEV;
-        for (nb = 0; nb < num_k8_northbridges; nb++) {
-                if (!pvt_lookup[nb])
-                        continue;
-
-                err = amd64_init_2nd_stage(pvt_lookup[nb]);
-                if (err)
-                        goto err_2nd_stage;
-
-                load_ok = true;
-        }
+        if (!atomic_read(&drv_instances))
+                goto err_no_instances;
 
-        if (load_ok) {
-                amd64_setup_pci_device();
-                return 0;
-        }
+        setup_pci_device();
+        return 0;
 
-err_2nd_stage:
+err_no_instances:
         pci_unregister_driver(&amd64_pci_driver);
+
 err_pci:
         msrs_free(msrs);
         msrs = NULL;
+
+err_free:
+        kfree(mcis);
+        mcis = NULL;
+
+        kfree(ecc_stngs);
+        ecc_stngs = NULL;
+
 err_ret:
         return err;
 }
@@ -2959,6 +2789,12 @@ static void __exit amd64_edac_exit(void)
 
         pci_unregister_driver(&amd64_pci_driver);
 
+        kfree(ecc_stngs);
+        ecc_stngs = NULL;
+
+        kfree(mcis);
+        mcis = NULL;
+
         msrs_free(msrs);
         msrs = NULL;
 }
diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h
index 613b9381e71a..9a666cb985b2 100644
--- a/drivers/edac/amd64_edac.h
+++ b/drivers/edac/amd64_edac.h
@@ -72,13 +72,28 @@
 #include <linux/edac.h>
 #include <asm/msr.h>
 #include "edac_core.h"
-#include "edac_mce_amd.h"
+#include "mce_amd.h"
 
-#define amd64_printk(level, fmt, arg...) \
-        edac_printk(level, "amd64", fmt, ##arg)
+#define amd64_debug(fmt, arg...) \
+        edac_printk(KERN_DEBUG, "amd64", fmt, ##arg)
 
-#define amd64_mc_printk(mci, level, fmt, arg...) \
-        edac_mc_chipset_printk(mci, level, "amd64", fmt, ##arg)
+#define amd64_info(fmt, arg...) \
+        edac_printk(KERN_INFO, "amd64", fmt, ##arg)
+
+#define amd64_notice(fmt, arg...) \
+        edac_printk(KERN_NOTICE, "amd64", fmt, ##arg)
+
+#define amd64_warn(fmt, arg...) \
+        edac_printk(KERN_WARNING, "amd64", fmt, ##arg)
+
+#define amd64_err(fmt, arg...) \
+        edac_printk(KERN_ERR, "amd64", fmt, ##arg)
+
+#define amd64_mc_warn(mci, fmt, arg...) \
+        edac_mc_chipset_printk(mci, KERN_WARNING, "amd64", fmt, ##arg)
+
+#define amd64_mc_err(mci, fmt, arg...) \
+        edac_mc_chipset_printk(mci, KERN_ERR, "amd64", fmt, ##arg)
 
 /*
  * Throughout the comments in this code, the following terms are used:
@@ -129,96 +144,76 @@
  *         sections 3.5.4 and 3.5.5 for more information.
  */
 
-#define EDAC_AMD64_VERSION              " Ver: 3.3.0 " __DATE__
+#define EDAC_AMD64_VERSION              "3.4.0"
 #define EDAC_MOD_STR                    "amd64_edac"
 
-#define EDAC_MAX_NUMNODES               8
-
 /* Extended Model from CPUID, for CPU Revision numbers */
 #define K8_REV_D                        1
 #define K8_REV_E                        2
 #define K8_REV_F                        4
 
 /* Hardware limit on ChipSelect rows per MC and processors per system */
-#define MAX_CS_COUNT                    8
-#define DRAM_REG_COUNT                  8
+#define NUM_CHIPSELECTS                 8
+#define DRAM_RANGES                     8
 
 #define ON true
 #define OFF false
 
 /*
+ * Create a contiguous bitmask starting at bit position @lo and ending at
+ * position @hi. For example
+ *
+ * GENMASK(21, 39) gives us the 64bit vector 0x000000ffffe00000.
+ */
+#define GENMASK(lo, hi)                 (((1ULL << ((hi) - (lo) + 1)) - 1) << (lo))
+
+/*
  * PCI-defined configuration space registers
  */
+#define PCI_DEVICE_ID_AMD_15H_NB_F1     0x1601
+#define PCI_DEVICE_ID_AMD_15H_NB_F2     0x1602
 
 
 /*
  * Function 1 - Address Map
  */
-#define K8_DRAM_BASE_LOW                0x40
-#define K8_DRAM_LIMIT_LOW               0x44
-#define K8_DHAR                         0xf0
-
-#define DHAR_VALID                      BIT(0)
-#define F10_DRAM_MEM_HOIST_VALID        BIT(1)
+#define DRAM_BASE_LO                    0x40
+#define DRAM_LIMIT_LO                   0x44
 
-#define DHAR_BASE_MASK                  0xff000000
-#define dhar_base(dhar)                 (dhar & DHAR_BASE_MASK)
+#define dram_intlv_en(pvt, i)           ((u8)((pvt->ranges[i].base.lo >> 8) & 0x7))
+#define dram_rw(pvt, i)                 ((u8)(pvt->ranges[i].base.lo & 0x3))
+#define dram_intlv_sel(pvt, i)          ((u8)((pvt->ranges[i].lim.lo >> 8) & 0x7))
+#define dram_dst_node(pvt, i)           ((u8)(pvt->ranges[i].lim.lo & 0x7))
 
-#define K8_DHAR_OFFSET_MASK             0x0000ff00
-#define k8_dhar_offset(dhar)            ((dhar & K8_DHAR_OFFSET_MASK) << 16)
+#define DHAR                            0xf0
+#define dhar_valid(pvt)                 ((pvt)->dhar & BIT(0))
+#define dhar_mem_hoist_valid(pvt)       ((pvt)->dhar & BIT(1))
+#define dhar_base(pvt)                  ((pvt)->dhar & 0xff000000)
+#define k8_dhar_offset(pvt)             (((pvt)->dhar & 0x0000ff00) << 16)
 
-#define F10_DHAR_OFFSET_MASK            0x0000ff80
                                         /* NOTE: Extra mask bit vs K8 */
-#define f10_dhar_offset(dhar)           ((dhar & F10_DHAR_OFFSET_MASK) << 16)
+#define f10_dhar_offset(pvt)            (((pvt)->dhar & 0x0000ff80) << 16)
 
+#define DCT_CFG_SEL                     0x10C
 
-/* F10 High BASE/LIMIT registers */
-#define F10_DRAM_BASE_HIGH              0x140
-#define F10_DRAM_LIMIT_HIGH             0x144
+#define DRAM_LOCAL_NODE_BASE            0x120
+#define DRAM_LOCAL_NODE_LIM             0x124
 
+#define DRAM_BASE_HI                    0x140
+#define DRAM_LIMIT_HI                   0x144
 
-/*
- * Function 2 - DRAM controller
- */
-#define K8_DCSB0                        0x40
-#define F10_DCSB1                       0x140
-
-#define K8_DCSB_CS_ENABLE               BIT(0)
-#define K8_DCSB_NPT_SPARE               BIT(1)
-#define K8_DCSB_NPT_TESTFAIL            BIT(2)
 
 /*
- * REV E: select [31:21] and [15:9] from DCSB and the shift amount to form
- * the address
- */
-#define REV_E_DCSB_BASE_BITS            (0xFFE0FE00ULL)
-#define REV_E_DCS_SHIFT                 4
-
-#define REV_F_F1Xh_DCSB_BASE_BITS       (0x1FF83FE0ULL)
-#define REV_F_F1Xh_DCS_SHIFT            8
-
-/*
- * REV F and later: selects [28:19] and [13:5] from DCSB and the shift amount
- * to form the address
+ * Function 2 - DRAM controller
  */
-#define REV_F_DCSB_BASE_BITS            (0x1FF83FE0ULL)
-#define REV_F_DCS_SHIFT                 8
-
-/* DRAM CS Mask Registers */
-#define K8_DCSM0                        0x60
-#define F10_DCSM1                       0x160
-
-/* REV E: select [29:21] and [15:9] from DCSM */
-#define REV_E_DCSM_MASK_BITS            0x3FE0FE00
-
-/* unused bits [24:20] and [12:0] */
-#define REV_E_DCS_NOTUSED_BITS          0x01F01FFF
+#define DCSB0                           0x40
+#define DCSB1                           0x140
+#define DCSB_CS_ENABLE                  BIT(0)
 
-/* REV F and later: select [28:19] and [13:5] from DCSM */
-#define REV_F_F1Xh_DCSM_MASK_BITS       0x1FF83FE0
+#define DCSM0                           0x60
+#define DCSM1                           0x160
 
-/* unused bits [26:22] and [12:0] */
-#define REV_F_F1Xh_DCS_NOTUSED_BITS     0x07C01FFF
+#define csrow_enabled(i, dct, pvt)      ((pvt)->csels[(dct)].csbases[(i)] & DCSB_CS_ENABLE)
 
 #define DBAM0                           0x80
 #define DBAM1                           0x180
@@ -228,152 +223,84 @@
 
 #define DBAM_MAX_VALUE                  11
 
-
-#define F10_DCLR_0                      0x90
-#define F10_DCLR_1                      0x190
+#define DCLR0                           0x90
+#define DCLR1                           0x190
 #define REVE_WIDTH_128                  BIT(16)
-#define F10_WIDTH_128                   BIT(11)
+#define WIDTH_128                       BIT(11)
 
+#define DCHR0                           0x94
+#define DCHR1                           0x194
+#define DDR3_MODE                       BIT(8)
 
-#define F10_DCHR_0                      0x94
-#define F10_DCHR_1                      0x194
+#define DCT_SEL_LO                      0x110
+#define dct_sel_baseaddr(pvt)           ((pvt)->dct_sel_lo & 0xFFFFF800)
+#define dct_sel_interleave_addr(pvt)    (((pvt)->dct_sel_lo >> 6) & 0x3)
+#define dct_high_range_enabled(pvt)     ((pvt)->dct_sel_lo & BIT(0))
+#define dct_interleave_enabled(pvt)     ((pvt)->dct_sel_lo & BIT(2))
 
-#define F10_DCHR_FOUR_RANK_DIMM         BIT(18)
-#define DDR3_MODE                       BIT(8)
-#define F10_DCHR_MblMode                BIT(6)
+#define dct_ganging_enabled(pvt)        ((boot_cpu_data.x86 == 0x10) && ((pvt)->dct_sel_lo & BIT(4)))
 
+#define dct_data_intlv_enabled(pvt)     ((pvt)->dct_sel_lo & BIT(5))
+#define dct_memory_cleared(pvt)         ((pvt)->dct_sel_lo & BIT(10))
 
-#define F10_DCTL_SEL_LOW                0x110
-#define dct_sel_baseaddr(pvt)           ((pvt->dram_ctl_select_low) & 0xFFFFF800)
-#define dct_sel_interleave_addr(pvt)    (((pvt->dram_ctl_select_low) >> 6) & 0x3)
-#define dct_high_range_enabled(pvt)     (pvt->dram_ctl_select_low & BIT(0))
-#define dct_interleave_enabled(pvt)     (pvt->dram_ctl_select_low & BIT(2))
-#define dct_ganging_enabled(pvt)        (pvt->dram_ctl_select_low & BIT(4))
-#define dct_data_intlv_enabled(pvt)     (pvt->dram_ctl_select_low & BIT(5))
-#define dct_dram_enabled(pvt)           (pvt->dram_ctl_select_low & BIT(8))
-#define dct_memory_cleared(pvt)         (pvt->dram_ctl_select_low & BIT(10))
+#define SWAP_INTLV_REG                  0x10c
 
-#define F10_DCTL_SEL_HIGH               0x114
+#define DCT_SEL_HI                      0x114
 
 /*
  * Function 3 - Misc Control
  */
-#define K8_NBCTL                        0x40
-
-/* Correctable ECC error reporting enable */
-#define K8_NBCTL_CECCEn                 BIT(0)
-
-/* UnCorrectable ECC error reporting enable */
-#define K8_NBCTL_UECCEn                 BIT(1)
-
-#define K8_NBCFG                        0x44
-#define K8_NBCFG_CHIPKILL               BIT(23)
-#define K8_NBCFG_ECC_ENABLE             BIT(22)
+#define NBCTL                           0x40
 
-#define K8_NBSL                         0x48
+#define NBCFG                           0x44
+#define NBCFG_CHIPKILL                  BIT(23)
+#define NBCFG_ECC_ENABLE                BIT(22)
 
-
-/* Family F10h: Normalized Extended Error Codes */
-#define F10_NBSL_EXT_ERR_RES            0x0
+/* F3x48: NBSL */
 #define F10_NBSL_EXT_ERR_ECC            0x8
+#define NBSL_PP_OBS                     0x2
 
-/* Next two are overloaded values */
-#define F10_NBSL_EXT_ERR_LINK_PROTO     0xB
-#define F10_NBSL_EXT_ERR_L3_PROTO       0xB
-
-#define F10_NBSL_EXT_ERR_NB_ARRAY       0xC
-#define F10_NBSL_EXT_ERR_DRAM_PARITY    0xD
-#define F10_NBSL_EXT_ERR_LINK_RETRY     0xE
-
-/* Next two are overloaded values */
-#define F10_NBSL_EXT_ERR_GART_WALK      0xF
-#define F10_NBSL_EXT_ERR_DEV_WALK       0xF
-
-/* 0x10 to 0x1B: Reserved */
-#define F10_NBSL_EXT_ERR_L3_DATA        0x1C
-#define F10_NBSL_EXT_ERR_L3_TAG         0x1D
-#define F10_NBSL_EXT_ERR_L3_LRU         0x1E
-
-/* K8: Normalized Extended Error Codes */
-#define K8_NBSL_EXT_ERR_ECC             0x0
-#define K8_NBSL_EXT_ERR_CRC             0x1
-#define K8_NBSL_EXT_ERR_SYNC            0x2
-#define K8_NBSL_EXT_ERR_MST             0x3
-#define K8_NBSL_EXT_ERR_TGT             0x4
-#define K8_NBSL_EXT_ERR_GART            0x5
-#define K8_NBSL_EXT_ERR_RMW             0x6
-#define K8_NBSL_EXT_ERR_WDT             0x7
-#define K8_NBSL_EXT_ERR_CHIPKILL_ECC    0x8
-#define K8_NBSL_EXT_ERR_DRAM_PARITY     0xD
-
-/*
- * The following are for BUS type errors AFTER values have been normalized by
- * shifting right
- */
-#define K8_NBSL_PP_SRC                  0x0
-#define K8_NBSL_PP_RES                  0x1
-#define K8_NBSL_PP_OBS                  0x2
-#define K8_NBSL_PP_GENERIC              0x3
-
-#define EXTRACT_ERR_CPU_MAP(x)          ((x) & 0xF)
-
-#define K8_NBEAL                        0x50
-#define K8_NBEAH                        0x54
-#define K8_SCRCTRL                      0x58
-
-#define F10_NB_CFG_LOW                  0x88
-#define F10_NB_CFG_LOW_ENABLE_EXT_CFG   BIT(14)
-
-#define F10_NB_CFG_HIGH                 0x8C
+#define SCRCTRL                         0x58
 
 #define F10_ONLINE_SPARE                0xB0
-#define F10_ONLINE_SPARE_SWAPDONE0(x)   ((x) & BIT(1))
-#define F10_ONLINE_SPARE_SWAPDONE1(x)   ((x) & BIT(3))
-#define F10_ONLINE_SPARE_BADDRAM_CS0(x) (((x) >> 4) & 0x00000007)
-#define F10_ONLINE_SPARE_BADDRAM_CS1(x) (((x) >> 8) & 0x00000007)
+#define online_spare_swap_done(pvt, c)  (((pvt)->online_spare >> (1 + 2 * (c))) & 0x1)
+#define online_spare_bad_dramcs(pvt, c) (((pvt)->online_spare >> (4 + 4 * (c))) & 0x7)
 
 #define F10_NB_ARRAY_ADDR               0xB8
-
-#define F10_NB_ARRAY_DRAM_ECC           0x80000000
+#define F10_NB_ARRAY_DRAM_ECC           BIT(31)
 
 /* Bits [2:1] are used to select 16-byte section within a 64-byte cacheline  */
 #define SET_NB_ARRAY_ADDRESS(section)   (((section) & 0x3) << 1)
 
 #define F10_NB_ARRAY_DATA               0xBC
-
 #define SET_NB_DRAM_INJECTION_WRITE(word, bits)  \
                                         (BIT(((word) & 0xF) + 20) | \
                                         BIT(17) | bits)
-
 #define SET_NB_DRAM_INJECTION_READ(word, bits)  \
                                         (BIT(((word) & 0xF) + 20) | \
                                         BIT(16) |  bits)
 
-#define K8_NBCAP                        0xE8
-#define K8_NBCAP_CORES                  (BIT(12)|BIT(13))
-#define K8_NBCAP_CHIPKILL               BIT(4)
-#define K8_NBCAP_SECDED                 BIT(3)
-#define K8_NBCAP_DCT_DUAL               BIT(0)
+#define NBCAP                           0xE8
+#define NBCAP_CHIPKILL                  BIT(4)
+#define NBCAP_SECDED                    BIT(3)
+#define NBCAP_DCT_DUAL                  BIT(0)
 
 #define EXT_NB_MCA_CFG                  0x180
 
 /* MSRs */
-#define K8_MSR_MCGCTL_NBE               BIT(4)
-
-#define K8_MSR_MC4CTL                   0x0410
-#define K8_MSR_MC4STAT                  0x0411
-#define K8_MSR_MC4ADDR                  0x0412
+#define MSR_MCGCTL_NBE                  BIT(4)
 
 /* AMD sets the first MC device at device ID 0x18. */
-static inline int get_node_id(struct pci_dev *pdev)
+static inline u8 get_node_id(struct pci_dev *pdev)
 {
         return PCI_SLOT(pdev->devfn) - 0x18;
 }
 
-enum amd64_chipset_families {
+enum amd_families {
         K8_CPUS = 0,
         F10_CPUS,
-        F11_CPUS,
+        F15_CPUS,
+        NUM_FAMILIES,
 };
 
 /* Error injection control structure */
@@ -383,17 +310,36 @@ struct error_injection {
         u32     bit_map;
 };
 
+/* low and high part of PCI config space regs */
+struct reg_pair {
+        u32 lo, hi;
+};
+
+/*
+ * See F1x[1, 0][7C:40] DRAM Base/Limit Registers
+ */
+struct dram_range {
+        struct reg_pair base;
+        struct reg_pair lim;
+};
+
+/* A DCT chip selects collection */
+struct chip_select {
+        u32 csbases[NUM_CHIPSELECTS];
+        u8 b_cnt;
+
+        u32 csmasks[NUM_CHIPSELECTS];
+        u8 m_cnt;
+};
+
 struct amd64_pvt {
+        struct low_ops *ops;
+
         /* pci_device handles which we utilize */
-        struct pci_dev *addr_f1_ctl;
-        struct pci_dev *dram_f2_ctl;
-        struct pci_dev *misc_f3_ctl;
+        struct pci_dev *F1, *F2, *F3;
 
-        int mc_node_id;         /* MC index of this MC node */
+        unsigned mc_node_id;    /* MC index of this MC node */
         int ext_model;          /* extended model value of this node */
-
-        struct low_ops *ops;    /* pointer to per PCI Device ID func table */
-
         int channel_count;
 
         /* Raw registers */
@@ -408,85 +354,66 @@ struct amd64_pvt {
         u32 dbam0;              /* DRAM Base Address Mapping reg for DCT0 */
         u32 dbam1;              /* DRAM Base Address Mapping reg for DCT1 */
 
-        /* DRAM CS Base Address Registers F2x[1,0][5C:40] */
-        u32 dcsb0[MAX_CS_COUNT];
-        u32 dcsb1[MAX_CS_COUNT];
-
-        /* DRAM CS Mask Registers F2x[1,0][6C:60] */
-        u32 dcsm0[MAX_CS_COUNT];
-        u32 dcsm1[MAX_CS_COUNT];
-
-        /*
-         * Decoded parts of DRAM BASE and LIMIT Registers
-         * F1x[78,70,68,60,58,50,48,40]
-         */
-        u64 dram_base[DRAM_REG_COUNT];
-        u64 dram_limit[DRAM_REG_COUNT];
-        u8  dram_IntlvSel[DRAM_REG_COUNT];
-        u8  dram_IntlvEn[DRAM_REG_COUNT];
-        u8  dram_DstNode[DRAM_REG_COUNT];
-        u8  dram_rw_en[DRAM_REG_COUNT];
-
-        /*
-         * The following fields are set at (load) run time, after CPU revision
-         * has been determined, since the dct_base and dct_mask registers vary
-         * based on revision
-         */
-        u32 dcsb_base;          /* DCSB base bits */
-        u32 dcsm_mask;          /* DCSM mask bits */
-        u32 cs_count;           /* num chip selects (== num DCSB registers) */
-        u32 num_dcsm;           /* Number of DCSM registers */
-        u32 dcs_mask_notused;   /* DCSM notused mask bits */
-        u32 dcs_shift;          /* DCSB and DCSM shift value */
+        /* one for each DCT */
+        struct chip_select csels[2];
+
+        /* DRAM base and limit pairs F1x[78,70,68,60,58,50,48,40] */
+        struct dram_range ranges[DRAM_RANGES];
 
         u64 top_mem;            /* top of memory below 4GB */
         u64 top_mem2;           /* top of memory above 4GB */
 
-        u32 dram_ctl_select_low;        /* DRAM Controller Select Low Reg */
-        u32 dram_ctl_select_high;       /* DRAM Controller Select High Reg */
-        u32 online_spare;               /* On-Line spare Reg */
+        u32 dct_sel_lo;         /* DRAM Controller Select Low */
+        u32 dct_sel_hi;         /* DRAM Controller Select High */
+        u32 online_spare;       /* On-Line spare Reg */
 
         /* x4 or x8 syndromes in use */
-        u8 syn_type;
-
-        /* temp storage for when input is received from sysfs */
-        struct err_regs ctl_error_info;
+        u8 ecc_sym_sz;
 
         /* place to store error injection parameters prior to issue */
         struct error_injection injection;
+};
 
-        /* Save old hw registers' values before we modified them */
-        u32 nbctl_mcgctl_saved;         /* When true, following 2 are valid */
-        u32 old_nbctl;
+static inline u64 get_dram_base(struct amd64_pvt *pvt, unsigned i)
+{
+        u64 addr = ((u64)pvt->ranges[i].base.lo & 0xffff0000) << 8;
+
+        if (boot_cpu_data.x86 == 0xf)
+                return addr;
+
+        return (((u64)pvt->ranges[i].base.hi & 0x000000ff) << 40) | addr;
+}
+
+static inline u64 get_dram_limit(struct amd64_pvt *pvt, unsigned i)
+{
+        u64 lim = (((u64)pvt->ranges[i].lim.lo & 0xffff0000) << 8) | 0x00ffffff;
 
-        /* MC Type Index value: socket F vs Family 10h */
-        u32 mc_type_index;
+        if (boot_cpu_data.x86 == 0xf)
+                return lim;
+
+        return (((u64)pvt->ranges[i].lim.hi & 0x000000ff) << 40) | lim;
+}
+
+static inline u16 extract_syndrome(u64 status)
+{
+        return ((status >> 47) & 0xff) | ((status >> 16) & 0xff00);
+}
+
+/*
+ * per-node ECC settings descriptor
+ */
+struct ecc_settings {
+        u32 old_nbctl;
+        bool nbctl_valid;
 
-        /* misc settings */
         struct flags {
-                unsigned long cf8_extcfg:1;
                 unsigned long nb_mce_enable:1;
                 unsigned long nb_ecc_prev:1;
         } flags;
 };
 
-struct scrubrate {
-       u32 scrubval;           /* bit pattern for scrub rate */
-       u32 bandwidth;          /* bandwidth consumed (bytes/sec) */
-};
-
-extern struct scrubrate scrubrates[23];
-extern const char *tt_msgs[4];
-extern const char *ll_msgs[4];
-extern const char *rrrr_msgs[16];
-extern const char *to_msgs[2];
-extern const char *pp_msgs[4];
-extern const char *ii_msgs[4];
-extern const char *ext_msgs[32];
-extern const char *htlink_msgs[8];
-
 #ifdef CONFIG_EDAC_DEBUG
-#define NUM_DBG_ATTRS 9
+#define NUM_DBG_ATTRS 5
 #else
 #define NUM_DBG_ATTRS 0
 #endif
@@ -506,58 +433,30 @@ extern struct mcidev_sysfs_attribute amd64_dbg_attrs[NUM_DBG_ATTRS],
  */
 struct low_ops {
         int (*early_channel_count)      (struct amd64_pvt *pvt);
-
-        u64 (*get_error_address)        (struct mem_ctl_info *mci,
-                                         struct err_regs *info);
-        void (*read_dram_base_limit)    (struct amd64_pvt *pvt, int dram);
-        void (*read_dram_ctl_register)  (struct amd64_pvt *pvt);
-        void (*map_sysaddr_to_csrow)    (struct mem_ctl_info *mci,
-                                         struct err_regs *info, u64 SystemAddr);
-        int (*dbam_to_cs)               (struct amd64_pvt *pvt, int cs_mode);
+        void (*map_sysaddr_to_csrow)    (struct mem_ctl_info *mci, u64 sys_addr,
+                                         u16 syndrome);
+        int (*dbam_to_cs)               (struct amd64_pvt *pvt, u8 dct, unsigned cs_mode);
+        int (*read_dct_pci_cfg)         (struct amd64_pvt *pvt, int offset,
+                                         u32 *val, const char *func);
 };
 
 struct amd64_family_type {
         const char *ctl_name;
-        u16 addr_f1_ctl;
-        u16 misc_f3_ctl;
+        u16 f1_id, f3_id;
         struct low_ops ops;
 };
 
-static struct amd64_family_type amd64_family_types[];
-
-static inline const char *get_amd_family_name(int index)
-{
-        return amd64_family_types[index].ctl_name;
-}
-
-static inline struct low_ops *family_ops(int index)
-{
-        return &amd64_family_types[index].ops;
-}
-
-static inline int amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset,
-                                           u32 *val, const char *func)
-{
-        int err = 0;
-
-        err = pci_read_config_dword(pdev, offset, val);
-        if (err)
-                amd64_printk(KERN_WARNING, "%s: error reading F%dx%x.\n",
-                             func, PCI_FUNC(pdev->devfn), offset);
-
-        return err;
-}
+int __amd64_write_pci_cfg_dword(struct pci_dev *pdev, int offset,
+                                u32 val, const char *func);
 
 #define amd64_read_pci_cfg(pdev, offset, val)   \
-        amd64_read_pci_cfg_dword(pdev, offset, val, __func__)
+        __amd64_read_pci_cfg_dword(pdev, offset, val, __func__)
 
-/*
- * For future CPU versions, verify the following as new 'slow' rates appear and
- * modify the necessary skip values for the supported CPU.
- */
-#define K8_MIN_SCRUB_RATE_BITS  0x0
-#define F10_MIN_SCRUB_RATE_BITS 0x5
-#define F11_MIN_SCRUB_RATE_BITS 0x6
+#define amd64_write_pci_cfg(pdev, offset, val)  \
+        __amd64_write_pci_cfg_dword(pdev, offset, val, __func__)
+
+#define amd64_read_dct_pci_cfg(pvt, offset, val) \
+        pvt->ops->read_dct_pci_cfg(pvt, offset, val, __func__)
 
 int amd64_get_dram_hole_info(struct mem_ctl_info *mci, u64 *hole_base,
                              u64 *hole_offset, u64 *hole_size);
diff --git a/drivers/edac/amd64_edac_dbg.c b/drivers/edac/amd64_edac_dbg.c
index 59cf2cf6e11e..e3562288f4ce 100644
--- a/drivers/edac/amd64_edac_dbg.c
+++ b/drivers/edac/amd64_edac_dbg.c
@@ -1,167 +1,16 @@
 #include "amd64_edac.h"
 
-/*
- * accept a hex value and store it into the virtual error register file, field:
- * nbeal and nbeah. Assume virtual error values have already been set for: NBSL,
- * NBSH and NBCFG. Then proceed to map the error values to a MC, CSROW and
- * CHANNEL
- */
-static ssize_t amd64_nbea_store(struct mem_ctl_info *mci, const char *data,
-                                size_t count)
-{
-        struct amd64_pvt *pvt = mci->pvt_info;
-        unsigned long long value;
-        int ret = 0;
-
-        ret = strict_strtoull(data, 16, &value);
-        if (ret != -EINVAL) {
-                debugf0("received NBEA= 0x%llx\n", value);
-
-                /* place the value into the virtual error packet */
-                pvt->ctl_error_info.nbeal = (u32) value;
-                value >>= 32;
-                pvt->ctl_error_info.nbeah = (u32) value;
-
-                /* Process the Mapping request */
-                /* TODO: Add race prevention */
-                amd_decode_nb_mce(pvt->mc_node_id, &pvt->ctl_error_info, 1);
-
-                return count;
-        }
-        return ret;
-}
-
-/* display back what the last NBEA (MCA NB Address (MC4_ADDR)) was written */
-static ssize_t amd64_nbea_show(struct mem_ctl_info *mci, char *data)
-{
-        struct amd64_pvt *pvt = mci->pvt_info;
-        u64 value;
-
-        value = pvt->ctl_error_info.nbeah;
-        value <<= 32;
-        value |= pvt->ctl_error_info.nbeal;
-
-        return sprintf(data, "%llx\n", value);
-}
-
-/* store the NBSL (MCA NB Status Low (MC4_STATUS)) value user desires */
-static ssize_t amd64_nbsl_store(struct mem_ctl_info *mci, const char *data,
-                                size_t count)
-{
-        struct amd64_pvt *pvt = mci->pvt_info;
-        unsigned long value;
-        int ret = 0;
-
-        ret = strict_strtoul(data, 16, &value);
-        if (ret != -EINVAL) {
-                debugf0("received NBSL= 0x%lx\n", value);
-
-                pvt->ctl_error_info.nbsl = (u32) value;
-
-                return count;
-        }
-        return ret;
-}
-
-/* display back what the last NBSL value written */
-static ssize_t amd64_nbsl_show(struct mem_ctl_info *mci, char *data)
-{
-        struct amd64_pvt *pvt = mci->pvt_info;
-        u32 value;
-
-        value = pvt->ctl_error_info.nbsl;
-
-        return sprintf(data, "%x\n", value);
-}
-
-/* store the NBSH (MCA NB Status High) value user desires */
-static ssize_t amd64_nbsh_store(struct mem_ctl_info *mci, const char *data,
-                                size_t count)
-{
-        struct amd64_pvt *pvt = mci->pvt_info;
-        unsigned long value;
-        int ret = 0;
-
-        ret = strict_strtoul(data, 16, &value);
-        if (ret != -EINVAL) {
-                debugf0("received NBSH= 0x%lx\n", value);
-
-                pvt->ctl_error_info.nbsh = (u32) value;
-
-                return count;
-        }
-        return ret;
-}
-
-/* display back what the last NBSH value written */
-static ssize_t amd64_nbsh_show(struct mem_ctl_info *mci, char *data)
-{
-        struct amd64_pvt *pvt = mci->pvt_info;
-        u32 value;
-
-        value = pvt->ctl_error_info.nbsh;
-
-        return sprintf(data, "%x\n", value);
+#define EDAC_DCT_ATTR_SHOW(reg)                                         \
+static ssize_t amd64_##reg##_show(struct mem_ctl_info *mci, char *data) \
+{                                                                       \
+        struct amd64_pvt *pvt = mci->pvt_info;                          \
+                return sprintf(data, "0x%016llx\n", (u64)pvt->reg);     \
 }
 
-/* accept and store the NBCFG (MCA NB Configuration) value user desires */
-static ssize_t amd64_nbcfg_store(struct mem_ctl_info *mci,
-                                        const char *data, size_t count)
-{
-        struct amd64_pvt *pvt = mci->pvt_info;
-        unsigned long value;
-        int ret = 0;
-
-        ret = strict_strtoul(data, 16, &value);
-        if (ret != -EINVAL) {
-                debugf0("received NBCFG= 0x%lx\n", value);
-
-                pvt->ctl_error_info.nbcfg = (u32) value;
-
-                return count;
-        }
-        return ret;
-}
-
-/* various show routines for the controls of a MCI */
-static ssize_t amd64_nbcfg_show(struct mem_ctl_info *mci, char *data)
-{
-        struct amd64_pvt *pvt = mci->pvt_info;
-
-        return sprintf(data, "%x\n", pvt->ctl_error_info.nbcfg);
-}
-
-
-static ssize_t amd64_dhar_show(struct mem_ctl_info *mci, char *data)
-{
-        struct amd64_pvt *pvt = mci->pvt_info;
-
-        return sprintf(data, "%x\n", pvt->dhar);
-}
-
-
-static ssize_t amd64_dbam_show(struct mem_ctl_info *mci, char *data)
-{
-        struct amd64_pvt *pvt = mci->pvt_info;
-
-        return sprintf(data, "%x\n", pvt->dbam0);
-}
-
-
-static ssize_t amd64_topmem_show(struct mem_ctl_info *mci, char *data)
-{
-        struct amd64_pvt *pvt = mci->pvt_info;
-
-        return sprintf(data, "%llx\n", pvt->top_mem);
-}
-
-
-static ssize_t amd64_topmem2_show(struct mem_ctl_info *mci, char *data)
-{
-        struct amd64_pvt *pvt = mci->pvt_info;
-
-        return sprintf(data, "%llx\n", pvt->top_mem2);
-}
+EDAC_DCT_ATTR_SHOW(dhar);
+EDAC_DCT_ATTR_SHOW(dbam0);
+EDAC_DCT_ATTR_SHOW(top_mem);
+EDAC_DCT_ATTR_SHOW(top_mem2);
 
 static ssize_t amd64_hole_show(struct mem_ctl_info *mci, char *data)
 {
@@ -182,38 +31,6 @@ struct mcidev_sysfs_attribute amd64_dbg_attrs[] = {
 
         {
                 .attr = {
-                        .name = "nbea_ctl",
-                        .mode = (S_IRUGO | S_IWUSR)
-                },
-                .show = amd64_nbea_show,
-                .store = amd64_nbea_store,
-        },
-        {
-                .attr = {
-                        .name = "nbsl_ctl",
-                        .mode = (S_IRUGO | S_IWUSR)
-                },
-                .show = amd64_nbsl_show,
-                .store = amd64_nbsl_store,
-        },
-        {
-                .attr = {
-                        .name = "nbsh_ctl",
-                        .mode = (S_IRUGO | S_IWUSR)
-                },
-                .show = amd64_nbsh_show,
-                .store = amd64_nbsh_store,
-        },
-        {
-                .attr = {
-                        .name = "nbcfg_ctl",
-                        .mode = (S_IRUGO | S_IWUSR)
-                },
-                .show = amd64_nbcfg_show,
-                .store = amd64_nbcfg_store,
-        },
-        {
-                .attr = {
                         .name = "dhar",
                         .mode = (S_IRUGO)
                 },
@@ -225,7 +42,7 @@ struct mcidev_sysfs_attribute amd64_dbg_attrs[] = {
                         .name = "dbam",
                         .mode = (S_IRUGO)
                 },
-                .show = amd64_dbam_show,
+                .show = amd64_dbam0_show,
                 .store = NULL,
         },
         {
@@ -233,7 +50,7 @@ struct mcidev_sysfs_attribute amd64_dbg_attrs[] = {
                         .name = "topmem",
                         .mode = (S_IRUGO)
                 },
-                .show = amd64_topmem_show,
+                .show = amd64_top_mem_show,
                 .store = NULL,
         },
         {
@@ -241,7 +58,7 @@ struct mcidev_sysfs_attribute amd64_dbg_attrs[] = {
                         .name = "topmem2",
                         .mode = (S_IRUGO)
                 },
-                .show = amd64_topmem2_show,
+                .show = amd64_top_mem2_show,
                 .store = NULL,
         },
         {
diff --git a/drivers/edac/amd64_edac_inj.c b/drivers/edac/amd64_edac_inj.c
index 29f1f7a612d9..303f10e03dda 100644
--- a/drivers/edac/amd64_edac_inj.c
+++ b/drivers/edac/amd64_edac_inj.c
@@ -23,9 +23,7 @@ static ssize_t amd64_inject_section_store(struct mem_ctl_info *mci,
         if (ret != -EINVAL) {
 
                 if (value > 3) {
-                        amd64_printk(KERN_WARNING,
-                                     "%s: invalid section 0x%lx\n",
-                                     __func__, value);
+                        amd64_warn("%s: invalid section 0x%lx\n", __func__, value);
                         return -EINVAL;
                 }
 
@@ -58,9 +56,7 @@ static ssize_t amd64_inject_word_store(struct mem_ctl_info *mci,
         if (ret != -EINVAL) {
 
                 if (value > 8) {
-                        amd64_printk(KERN_WARNING,
-                                     "%s: invalid word 0x%lx\n",
-                                     __func__, value);
+                        amd64_warn("%s: invalid word 0x%lx\n", __func__, value);
                         return -EINVAL;
                 }
 
@@ -92,9 +88,8 @@ static ssize_t amd64_inject_ecc_vector_store(struct mem_ctl_info *mci,
         if (ret != -EINVAL) {
 
                 if (value & 0xFFFF0000) {
-                        amd64_printk(KERN_WARNING,
-                                     "%s: invalid EccVector: 0x%lx\n",
-                                     __func__, value);
+                        amd64_warn("%s: invalid EccVector: 0x%lx\n",
+                                   __func__, value);
                         return -EINVAL;
                 }
 
@@ -122,15 +117,13 @@ static ssize_t amd64_inject_read_store(struct mem_ctl_info *mci,
                 /* Form value to choose 16-byte section of cacheline */
                 section = F10_NB_ARRAY_DRAM_ECC |
                                 SET_NB_ARRAY_ADDRESS(pvt->injection.section);
-                pci_write_config_dword(pvt->misc_f3_ctl,
-                                        F10_NB_ARRAY_ADDR, section);
+                amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_ADDR, section);
 
                 word_bits = SET_NB_DRAM_INJECTION_READ(pvt->injection.word,
                                                 pvt->injection.bit_map);
 
                 /* Issue 'word' and 'bit' along with the READ request */
-                pci_write_config_dword(pvt->misc_f3_ctl,
-                                        F10_NB_ARRAY_DATA, word_bits);
+                amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_DATA, word_bits);
 
                 debugf0("section=0x%x word_bits=0x%x\n", section, word_bits);
 
@@ -157,15 +150,13 @@ static ssize_t amd64_inject_write_store(struct mem_ctl_info *mci,
                 /* Form value to choose 16-byte section of cacheline */
                 section = F10_NB_ARRAY_DRAM_ECC |
                                 SET_NB_ARRAY_ADDRESS(pvt->injection.section);
-                pci_write_config_dword(pvt->misc_f3_ctl,
-                                        F10_NB_ARRAY_ADDR, section);
+                amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_ADDR, section);
 
                 word_bits = SET_NB_DRAM_INJECTION_WRITE(pvt->injection.word,
                                                 pvt->injection.bit_map);
 
                 /* Issue 'word' and 'bit' along with the READ request */
-                pci_write_config_dword(pvt->misc_f3_ctl,
-                                        F10_NB_ARRAY_DATA, word_bits);
+                amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_DATA, word_bits);
 
                 debugf0("section=0x%x word_bits=0x%x\n", section, word_bits);
 
diff --git a/drivers/edac/amd76x_edac.c b/drivers/edac/amd76x_edac.c
index cace0a7b707a..e47e73bbbcc5 100644
--- a/drivers/edac/amd76x_edac.c
+++ b/drivers/edac/amd76x_edac.c
@@ -19,7 +19,7 @@
 #include <linux/edac.h>
 #include "edac_core.h"
 
-#define AMD76X_REVISION " Ver: 2.0.2 "  __DATE__
+#define AMD76X_REVISION " Ver: 2.0.2"
 #define EDAC_MOD_STR    "amd76x_edac"
 
 #define amd76x_printk(level, fmt, arg...) \
diff --git a/drivers/edac/amd8111_edac.c b/drivers/edac/amd8111_edac.c
index 35b78d04bbfa..ddd890052ce2 100644
--- a/drivers/edac/amd8111_edac.c
+++ b/drivers/edac/amd8111_edac.c
@@ -33,7 +33,7 @@
 #include "edac_module.h"
 #include "amd8111_edac.h"
 
-#define AMD8111_EDAC_REVISION   " Ver: 1.0.0 " __DATE__
+#define AMD8111_EDAC_REVISION   " Ver: 1.0.0"
 #define AMD8111_EDAC_MOD_STR    "amd8111_edac"
 
 #define PCI_DEVICE_ID_AMD_8111_PCI      0x7460
diff --git a/drivers/edac/amd8131_edac.c b/drivers/edac/amd8131_edac.c
index b432d60c622a..a5c680561c73 100644
--- a/drivers/edac/amd8131_edac.c
+++ b/drivers/edac/amd8131_edac.c
@@ -33,7 +33,7 @@
 #include "edac_module.h"
 #include "amd8131_edac.h"
 
-#define AMD8131_EDAC_REVISION   " Ver: 1.0.0 " __DATE__
+#define AMD8131_EDAC_REVISION   " Ver: 1.0.0"
 #define AMD8131_EDAC_MOD_STR    "amd8131_edac"
 
 /* Wrapper functions for accessing PCI configuration space */
diff --git a/drivers/edac/amd8131_edac.h b/drivers/edac/amd8131_edac.h
index 60e0d1c72dee..6f8b07131ec4 100644
--- a/drivers/edac/amd8131_edac.h
+++ b/drivers/edac/amd8131_edac.h
@@ -99,7 +99,7 @@ struct amd8131_dev_info {
 
 /*
  * AMD8131 chipset has two pairs of PCIX Bridge and related IOAPIC
- * Controler, and ATCA-6101 has two AMD8131 chipsets, so there are
+ * Controller, and ATCA-6101 has two AMD8131 chipsets, so there are
  * four PCIX Bridges on ATCA-6101 altogether.
  *
  * These PCIX Bridges share the same PCI Device ID and are all of
diff --git a/drivers/edac/cell_edac.c b/drivers/edac/cell_edac.c
index c973004c002c..db1df59ae2b6 100644
--- a/drivers/edac/cell_edac.c
+++ b/drivers/edac/cell_edac.c
@@ -47,7 +47,7 @@ static void cell_edac_count_ce(struct mem_ctl_info *mci, int chan, u64 ar)
         offset = address & ~PAGE_MASK;
         syndrome = (ar & 0x000000001fe00000ul) >> 21;
 
-        /* TODO: Decoding of the error addresss */
+        /* TODO: Decoding of the error address */
         edac_mc_handle_ce(mci, csrow->first_page + pfn, offset,
                           syndrome, 0, chan, "");
 }
@@ -68,7 +68,7 @@ static void cell_edac_count_ue(struct mem_ctl_info *mci, int chan, u64 ar)
         pfn = address >> PAGE_SHIFT;
         offset = address & ~PAGE_MASK;
 
-        /* TODO: Decoding of the error addresss */
+        /* TODO: Decoding of the error address */
         edac_mc_handle_ue(mci, csrow->first_page + pfn, offset, 0, "");
 }
 
diff --git a/drivers/edac/cpc925_edac.c b/drivers/edac/cpc925_edac.c
index 1609a19df495..a687a0d16962 100644
--- a/drivers/edac/cpc925_edac.c
+++ b/drivers/edac/cpc925_edac.c
@@ -30,7 +30,7 @@
 #include "edac_core.h"
 #include "edac_module.h"
 
-#define CPC925_EDAC_REVISION    " Ver: 1.0.0 " __DATE__
+#define CPC925_EDAC_REVISION    " Ver: 1.0.0"
 #define CPC925_EDAC_MOD_STR     "cpc925_edac"
 
 #define cpc925_printk(level, fmt, arg...) \
@@ -817,10 +817,11 @@ static void cpc925_del_edac_devices(void)
         }
 }
 
-/* Convert current back-ground scrub rate into byte/sec bandwith */
-static int cpc925_get_sdram_scrub_rate(struct mem_ctl_info *mci, u32 *bw)
+/* Convert current back-ground scrub rate into byte/sec bandwidth */
+static int cpc925_get_sdram_scrub_rate(struct mem_ctl_info *mci)
 {
         struct cpc925_mc_pdata *pdata = mci->pvt_info;
+        int bw;
         u32 mscr;
         u8 si;
 
@@ -832,11 +833,11 @@ static int cpc925_get_sdram_scrub_rate(struct mem_ctl_info *mci, u32 *bw)
         if (((mscr & MSCR_SCRUB_MOD_MASK) != MSCR_BACKGR_SCRUB) ||
             (si == 0)) {
                 cpc925_mc_printk(mci, KERN_INFO, "Scrub mode not enabled\n");
-                *bw = 0;
+                bw = 0;
         } else
-                *bw = CPC925_SCRUB_BLOCK_SIZE * 0xFA67 / si;
+                bw = CPC925_SCRUB_BLOCK_SIZE * 0xFA67 / si;
 
-        return 0;
+        return bw;
 }
 
 /* Return 0 for single channel; 1 for dual channel */
diff --git a/drivers/edac/e752x_edac.c b/drivers/edac/e752x_edac.c
index 073f5a06d238..1af531a11d21 100644
--- a/drivers/edac/e752x_edac.c
+++ b/drivers/edac/e752x_edac.c
@@ -24,7 +24,7 @@
 #include <linux/edac.h>
 #include "edac_core.h"
 
-#define E752X_REVISION  " Ver: 2.0.2 " __DATE__
+#define E752X_REVISION  " Ver: 2.0.2"
 #define EDAC_MOD_STR    "e752x_edac"
 
 static int report_non_memory_errors;
@@ -983,11 +983,11 @@ static int set_sdram_scrub_rate(struct mem_ctl_info *mci, u32 new_bw)
 
         pci_write_config_word(pdev, E752X_MCHSCRB, scrubrates[i].scrubval);
 
-        return 0;
+        return scrubrates[i].bandwidth;
 }
 
 /* Convert current scrub rate value into byte/sec bandwidth */
-static int get_sdram_scrub_rate(struct mem_ctl_info *mci, u32 *bw)
+static int get_sdram_scrub_rate(struct mem_ctl_info *mci)
 {
         const struct scrubrate *scrubrates;
         struct e752x_pvt *pvt = (struct e752x_pvt *) mci->pvt_info;
@@ -1013,10 +1013,8 @@ static int get_sdram_scrub_rate(struct mem_ctl_info *mci, u32 *bw)
                         "Invalid sdram scrub control value: 0x%x\n", scrubval);
                 return -1;
         }
+        return scrubrates[i].bandwidth;
 
-        *bw = scrubrates[i].bandwidth;
-
-        return 0;
 }
 
 /* Return 1 if dual channel mode is active.  Else return 0. */
diff --git a/drivers/edac/e7xxx_edac.c b/drivers/edac/e7xxx_edac.c
index 1731d7245816..6ffb6d23281f 100644
--- a/drivers/edac/e7xxx_edac.c
+++ b/drivers/edac/e7xxx_edac.c
@@ -29,7 +29,7 @@
 #include <linux/edac.h>
 #include "edac_core.h"
 
-#define E7XXX_REVISION " Ver: 2.0.2 " __DATE__
+#define E7XXX_REVISION " Ver: 2.0.2"
 #define EDAC_MOD_STR    "e7xxx_edac"
 
 #define e7xxx_printk(level, fmt, arg...) \
diff --git a/drivers/edac/edac_core.h b/drivers/edac/edac_core.h
index ce7146677e9b..55b8278bb172 100644
--- a/drivers/edac/edac_core.h
+++ b/drivers/edac/edac_core.h
@@ -41,9 +41,11 @@
 #define MC_PROC_NAME_MAX_LEN    7
 
 #if PAGE_SHIFT < 20
-#define PAGES_TO_MiB( pages )   ( ( pages ) >> ( 20 - PAGE_SHIFT ) )
+#define PAGES_TO_MiB(pages)     ((pages) >> (20 - PAGE_SHIFT))
+#define MiB_TO_PAGES(mb)        ((mb) << (20 - PAGE_SHIFT))
 #else                           /* PAGE_SHIFT > 20 */
-#define PAGES_TO_MiB( pages )   ( ( pages ) << ( PAGE_SHIFT - 20 ) )
+#define PAGES_TO_MiB(pages)     ((pages) << (PAGE_SHIFT - 20))
+#define MiB_TO_PAGES(mb)        ((mb) >> (PAGE_SHIFT - 20))
 #endif
 
 #define edac_printk(level, prefix, fmt, arg...) \
@@ -66,9 +68,10 @@
 #define EDAC_PCI "PCI"
 #define EDAC_DEBUG "DEBUG"
 
+extern const char *edac_mem_types[];
+
 #ifdef CONFIG_EDAC_DEBUG
 extern int edac_debug_level;
-extern const char *edac_mem_types[];
 
 #define edac_debug_printk(level, fmt, arg...)                           \
         do {                                                            \
@@ -161,7 +164,7 @@ enum mem_type {
 /* chipset Error Detection and Correction capabilities and mode */
 enum edac_type {
         EDAC_UNKNOWN = 0,       /* Unknown if ECC is available */
-        EDAC_NONE,              /* Doesnt support ECC */
+        EDAC_NONE,              /* Doesn't support ECC */
         EDAC_RESERVED,          /* Reserved ECC type */
         EDAC_PARITY,            /* Detects parity errors */
         EDAC_EC,                /* Error Checking - no correction */
@@ -230,7 +233,7 @@ enum scrub_type {
  *                      of these in parallel provides 64 bits which is common
  *                      for a memory stick.
  *
- * Memory Stick:        A printed circuit board that agregates multiple
+ * Memory Stick:        A printed circuit board that aggregates multiple
  *                      memory devices in parallel.  This is the atomic
  *                      memory component that is purchaseable by Joe consumer
  *                      and loaded into a memory socket.
@@ -256,7 +259,7 @@ enum scrub_type {
  *                      for single channel are 64 bits, for dual channel 128
  *                      bits.
  *
- * Single-Ranked stick: A Single-ranked stick has 1 chip-select row of memmory.
+ * Single-Ranked stick: A Single-ranked stick has 1 chip-select row of memory.
  *                      Motherboards commonly drive two chip-select pins to
  *                      a memory stick. A single-ranked stick, will occupy
  *                      only one of those rows. The other will be unused.
@@ -328,7 +331,7 @@ struct csrow_info {
 
 struct mcidev_sysfs_group {
         const char *name;                               /* group name */
-        struct mcidev_sysfs_attribute *mcidev_attr;     /* group attributes */
+        const struct mcidev_sysfs_attribute *mcidev_attr; /* group attributes */
 };
 
 struct mcidev_sysfs_group_kobj {
@@ -336,7 +339,7 @@ struct mcidev_sysfs_group_kobj {
 
         struct kobject kobj;            /* kobj for the group */
 
-        struct mcidev_sysfs_group *grp; /* group description table */
+        const struct mcidev_sysfs_group *grp;   /* group description table */
         struct mem_ctl_info *mci;       /* the parent */
 };
 
@@ -347,7 +350,7 @@ struct mcidev_sysfs_group_kobj {
 struct mcidev_sysfs_attribute {
         /* It should use either attr or grp */
         struct attribute attr;
-        struct mcidev_sysfs_group *grp; /* Points to a group of attributes */
+        const struct mcidev_sysfs_group *grp;   /* Points to a group of attributes */
 
         /* Ops for show/store values at the attribute - not used on group */
         ssize_t (*show)(struct mem_ctl_info *,char *);
@@ -382,9 +385,9 @@ struct mem_ctl_info {
 
         /* Get the current sdram memory scrub rate from the internal
            representation and converts it to the closest matching
-           bandwith in bytes/sec.
+           bandwidth in bytes/sec.
          */
-        int (*get_sdram_scrub_rate) (struct mem_ctl_info * mci, u32 * bw);
+        int (*get_sdram_scrub_rate) (struct mem_ctl_info * mci);
 
 
         /* pointer to edac checking routine */
@@ -418,10 +421,6 @@ struct mem_ctl_info {
         u32 ce_count;           /* Total Correctable Errors for this MC */
         unsigned long start_time;       /* mci load start time (in jiffies) */
 
-        /* this stuff is for safe removal of mc devices from global list while
-         * NMI handlers may be traversing list
-         */
-        struct rcu_head rcu;
         struct completion complete;
 
         /* edac sysfs device control */
@@ -440,7 +439,7 @@ struct mem_ctl_info {
          * If attributes are desired, then set to array of attributes
          * If no attributes are desired, leave NULL
          */
-        struct mcidev_sysfs_attribute *mc_driver_sysfs_attributes;
+        const struct mcidev_sysfs_attribute *mc_driver_sysfs_attributes;
 
         /* work struct for this MC */
         struct delayed_work work;
@@ -617,10 +616,6 @@ struct edac_device_ctl_info {
 
         unsigned long start_time;       /* edac_device load start time (jiffies) */
 
-        /* these are for safe removal of mc devices from global list while
-         * NMI handlers may be traversing list
-         */
-        struct rcu_head rcu;
         struct completion removal_complete;
 
         /* sysfs top name under 'edac' directory
@@ -719,10 +714,6 @@ struct edac_pci_ctl_info {
 
         unsigned long start_time;       /* edac_pci load start time (jiffies) */
 
-        /* these are for safe removal of devices from global list while
-         * NMI handlers may be traversing list
-         */
-        struct rcu_head rcu;
         struct completion complete;
 
         /* sysfs top name under 'edac' directory
@@ -810,6 +801,7 @@ extern struct mem_ctl_info *edac_mc_alloc(unsigned sz_pvt, unsigned nr_csrows,
 extern int edac_mc_add_mc(struct mem_ctl_info *mci);
 extern void edac_mc_free(struct mem_ctl_info *mci);
 extern struct mem_ctl_info *edac_mc_find(int idx);
+extern struct mem_ctl_info *find_mci_by_dev(struct device *dev);
 extern struct mem_ctl_info *edac_mc_del_mc(struct device *dev);
 extern int edac_mc_find_csrow_by_page(struct mem_ctl_info *mci,
                                       unsigned long page);
@@ -819,7 +811,7 @@ extern int edac_mc_find_csrow_by_page(struct mem_ctl_info *mci,
  * There are a limited number of error logging registers that can
  * be exausted.  When all registers are exhausted and an additional
  * error occurs then an error overflow register records that an
- * error occured and the type of error, but doesn't have any
+ * error occurred and the type of error, but doesn't have any
  * further information.  The ce/ue versions make for cleaner
  * reporting logic and function interface - reduces conditional
  * statement clutter and extra function arguments.
diff --git a/drivers/edac/edac_device.c b/drivers/edac/edac_device.c
index d5e13c94714f..c3f67437afb6 100644
--- a/drivers/edac/edac_device.c
+++ b/drivers/edac/edac_device.c
@@ -346,30 +346,18 @@ fail1:
 }
 
 /*
- * complete_edac_device_list_del
- *
- *      callback function when reference count is zero
- */
-static void complete_edac_device_list_del(struct rcu_head *head)
-{
-        struct edac_device_ctl_info *edac_dev;
-
-        edac_dev = container_of(head, struct edac_device_ctl_info, rcu);
-        INIT_LIST_HEAD(&edac_dev->link);
-}
-
-/*
  * del_edac_device_from_global_list
- *
- *      remove the RCU, setup for a callback call,
- *      then wait for the callback to occur
  */
 static void del_edac_device_from_global_list(struct edac_device_ctl_info
                                                 *edac_device)
 {
         list_del_rcu(&edac_device->link);
-        call_rcu(&edac_device->rcu, complete_edac_device_list_del);
-        rcu_barrier();
+
+        /* these are for safe removal of devices from global list while
+         * NMI handlers may be traversing list
+         */
+        synchronize_rcu();
+        INIT_LIST_HEAD(&edac_device->link);
 }
 
 /*
@@ -672,7 +660,7 @@ void edac_device_handle_ce(struct edac_device_ctl_info *edac_dev,
                 block->counters.ce_count++;
         }
 
-        /* Propogate the count up the 'totals' tree */
+        /* Propagate the count up the 'totals' tree */
         instance->counters.ce_count++;
         edac_dev->counters.ce_count++;
 
@@ -718,7 +706,7 @@ void edac_device_handle_ue(struct edac_device_ctl_info *edac_dev,
                 block->counters.ue_count++;
         }
 
-        /* Propogate the count up the 'totals' tree */
+        /* Propagate the count up the 'totals' tree */
         instance->counters.ue_count++;
         edac_dev->counters.ue_count++;
 
diff --git a/drivers/edac/edac_device_sysfs.c b/drivers/edac/edac_device_sysfs.c
index 070968178a24..86649df00285 100644
--- a/drivers/edac/edac_device_sysfs.c
+++ b/drivers/edac/edac_device_sysfs.c
@@ -1,7 +1,7 @@
 /*
  * file for managing the edac_device class of devices for EDAC
  *
- * (C) 2007 SoftwareBitMaker (http://www.softwarebitmaker.com)
+ * (C) 2007 SoftwareBitMaker 
  *
  * This file may be distributed under the terms of the
  * GNU General Public License.
@@ -13,6 +13,7 @@
 #include <linux/ctype.h>
 #include <linux/module.h>
 #include <linux/slab.h>
+#include <linux/edac.h>
 
 #include "edac_core.h"
 #include "edac_module.h"
@@ -235,7 +236,7 @@ int edac_device_register_sysfs_main_kobj(struct edac_device_ctl_info *edac_dev)
         debugf1("%s()\n", __func__);
 
         /* get the /sys/devices/system/edac reference */
-        edac_class = edac_get_edac_class();
+        edac_class = edac_get_sysfs_class();
         if (edac_class == NULL) {
                 debugf1("%s() no edac_class error\n", __func__);
                 err = -ENODEV;
@@ -255,7 +256,7 @@ int edac_device_register_sysfs_main_kobj(struct edac_device_ctl_info *edac_dev)
 
         if (!try_module_get(edac_dev->owner)) {
                 err = -ENODEV;
-                goto err_out;
+                goto err_mod_get;
         }
 
         /* register */
@@ -282,6 +283,9 @@ int edac_device_register_sysfs_main_kobj(struct edac_device_ctl_info *edac_dev)
 err_kobj_reg:
         module_put(edac_dev->owner);
 
+err_mod_get:
+        edac_put_sysfs_class();
+
 err_out:
         return err;
 }
@@ -290,12 +294,11 @@ err_out:
  * edac_device_unregister_sysfs_main_kobj:
  *      the '..../edac/<name>' kobject
  */
-void edac_device_unregister_sysfs_main_kobj(
-                                        struct edac_device_ctl_info *edac_dev)
+void edac_device_unregister_sysfs_main_kobj(struct edac_device_ctl_info *dev)
 {
         debugf0("%s()\n", __func__);
         debugf4("%s() name of kobject is: %s\n",
-                __func__, kobject_name(&edac_dev->kobj));
+                __func__, kobject_name(&dev->kobj));
 
         /*
          * Unregister the edac device's kobject and
@@ -304,7 +307,8 @@ void edac_device_unregister_sysfs_main_kobj(
          *   a) module_put() this module
          *   b) 'kfree' the memory
          */
-        kobject_put(&edac_dev->kobj);
+        kobject_put(&dev->kobj);
+        edac_put_sysfs_class();
 }
 
 /* edac_dev -> instance information */
@@ -529,7 +533,7 @@ static int edac_device_create_block(struct edac_device_ctl_info *edac_dev,
         memset(&block->kobj, 0, sizeof(struct kobject));
 
         /* bump the main kobject's reference count for this controller
-         * and this instance is dependant on the main
+         * and this instance is dependent on the main
          */
         main_kobj = kobject_get(&edac_dev->kobj);
         if (!main_kobj) {
@@ -631,7 +635,7 @@ static int edac_device_create_instance(struct edac_device_ctl_info *edac_dev,
         instance->ctl = edac_dev;
 
         /* bump the main kobject's reference count for this controller
-         * and this instance is dependant on the main
+         * and this instance is dependent on the main
          */
         main_kobj = kobject_get(&edac_dev->kobj);
         if (!main_kobj) {
diff --git a/drivers/edac/edac_mc.c b/drivers/edac/edac_mc.c
index 6b21e25f7a84..d69144a09043 100644
--- a/drivers/edac/edac_mc.c
+++ b/drivers/edac/edac_mc.c
@@ -76,6 +76,8 @@ static void edac_mc_dump_mci(struct mem_ctl_info *mci)
         debugf3("\tpvt_info = %p\n\n", mci->pvt_info);
 }
 
+#endif                          /* CONFIG_EDAC_DEBUG */
+
 /*
  * keep those in sync with the enum mem_type
  */
@@ -100,8 +102,6 @@ const char *edac_mem_types[] = {
 };
 EXPORT_SYMBOL_GPL(edac_mem_types);
 
-#endif                          /* CONFIG_EDAC_DEBUG */
-
 /* 'ptr' points to a possibly unaligned item X such that sizeof(X) is 'size'.
  * Adjust 'ptr' so that its alignment is at least as stringent as what the
  * compiler would provide for X and return the aligned result.
@@ -207,6 +207,7 @@ struct mem_ctl_info *edac_mc_alloc(unsigned sz_pvt, unsigned nr_csrows,
         }
 
         mci->op_state = OP_ALLOC;
+        INIT_LIST_HEAD(&mci->grp_kobj_list);
 
         /*
          * Initialize the 'root' kobj for the edac_mc controller
@@ -234,18 +235,24 @@ EXPORT_SYMBOL_GPL(edac_mc_alloc);
  */
 void edac_mc_free(struct mem_ctl_info *mci)
 {
+        debugf1("%s()\n", __func__);
+
         edac_mc_unregister_sysfs_main_kobj(mci);
+
+        /* free the mci instance memory here */
+        kfree(mci);
 }
 EXPORT_SYMBOL_GPL(edac_mc_free);
 
 
-/*
+/**
  * find_mci_by_dev
  *
  *      scan list of controllers looking for the one that manages
  *      the 'dev' device
+ * @dev: pointer to a struct device related with the MCI
  */
-static struct mem_ctl_info *find_mci_by_dev(struct device *dev)
+struct mem_ctl_info *find_mci_by_dev(struct device *dev)
 {
         struct mem_ctl_info *mci;
         struct list_head *item;
@@ -261,6 +268,7 @@ static struct mem_ctl_info *find_mci_by_dev(struct device *dev)
 
         return NULL;
 }
+EXPORT_SYMBOL_GPL(find_mci_by_dev);
 
 /*
  * handler for EDAC to check if NMI type handler has asserted interrupt
@@ -439,20 +447,16 @@ fail1:
         return 1;
 }
 
-static void complete_mc_list_del(struct rcu_head *head)
-{
-        struct mem_ctl_info *mci;
-
-        mci = container_of(head, struct mem_ctl_info, rcu);
-        INIT_LIST_HEAD(&mci->link);
-}
-
 static void del_mc_from_global_list(struct mem_ctl_info *mci)
 {
         atomic_dec(&edac_handlers);
         list_del_rcu(&mci->link);
-        call_rcu(&mci->rcu, complete_mc_list_del);
-        rcu_barrier();
+
+        /* these are for safe removal of devices from global list while
+         * NMI handlers may be traversing list
+         */
+        synchronize_rcu();
+        INIT_LIST_HEAD(&mci->link);
 }
 
 /**
@@ -578,14 +582,16 @@ struct mem_ctl_info *edac_mc_del_mc(struct device *dev)
                 return NULL;
         }
 
-        /* marking MCI offline */
-        mci->op_state = OP_OFFLINE;
-
         del_mc_from_global_list(mci);
         mutex_unlock(&mem_ctls_mutex);
 
-        /* flush workq processes and remove sysfs */
+        /* flush workq processes */
         edac_mc_workq_teardown(mci);
+
+        /* marking MCI offline */
+        mci->op_state = OP_OFFLINE;
+
+        /* remove from sysfs */
         edac_remove_sysfs_mci_device(mci);
 
         edac_printk(KERN_INFO, EDAC_MC,
@@ -714,7 +720,7 @@ void edac_mc_handle_ce(struct mem_ctl_info *mci,
                  * Some MC's can remap memory so that it is still available
                  * at a different address when PCI devices map into memory.
                  * MC's that can't do this lose the memory where PCI devices
-                 * are mapped.  This mapping is MC dependant and so we call
+                 * are mapped.  This mapping is MC dependent and so we call
                  * back into the MC driver for it to map the MC page to
                  * a physical (CPU) page which can then be mapped to a virtual
                  * page - which can then be scrubbed.
diff --git a/drivers/edac/edac_mc_sysfs.c b/drivers/edac/edac_mc_sysfs.c
index 8aad94d10c0c..29ffa350bfbe 100644
--- a/drivers/edac/edac_mc_sysfs.c
+++ b/drivers/edac/edac_mc_sysfs.c
@@ -11,6 +11,7 @@
 
 #include <linux/ctype.h>
 #include <linux/slab.h>
+#include <linux/edac.h>
 #include <linux/bug.h>
 
 #include "edac_core.h"
@@ -435,56 +436,54 @@ static ssize_t mci_reset_counters_store(struct mem_ctl_info *mci,
         return count;
 }
 
-/* memory scrubbing */
+/* Memory scrubbing interface:
+ *
+ * A MC driver can limit the scrubbing bandwidth based on the CPU type.
+ * Therefore, ->set_sdram_scrub_rate should be made to return the actual
+ * bandwidth that is accepted or 0 when scrubbing is to be disabled.
+ *
+ * Negative value still means that an error has occurred while setting
+ * the scrub rate.
+ */
 static ssize_t mci_sdram_scrub_rate_store(struct mem_ctl_info *mci,
                                           const char *data, size_t count)
 {
         unsigned long bandwidth = 0;
-        int err;
+        int new_bw = 0;
 
-        if (!mci->set_sdram_scrub_rate) {
-                edac_printk(KERN_WARNING, EDAC_MC,
-                            "Memory scrub rate setting not implemented!\n");
+        if (!mci->set_sdram_scrub_rate)
                 return -EINVAL;
-        }
 
         if (strict_strtoul(data, 10, &bandwidth) < 0)
                 return -EINVAL;
 
-        err = mci->set_sdram_scrub_rate(mci, (u32)bandwidth);
-        if (err) {
-                edac_printk(KERN_DEBUG, EDAC_MC,
-                            "Failed setting scrub rate to %lu\n", bandwidth);
+        new_bw = mci->set_sdram_scrub_rate(mci, bandwidth);
+        if (new_bw < 0) {
+                edac_printk(KERN_WARNING, EDAC_MC,
+                            "Error setting scrub rate to: %lu\n", bandwidth);
                 return -EINVAL;
         }
-        else {
-                edac_printk(KERN_DEBUG, EDAC_MC,
-                            "Scrub rate set to: %lu\n", bandwidth);
-                return count;
-        }
+
+        return count;
 }
 
+/*
+ * ->get_sdram_scrub_rate() return value semantics same as above.
+ */
 static ssize_t mci_sdram_scrub_rate_show(struct mem_ctl_info *mci, char *data)
 {
-        u32 bandwidth = 0;
-        int err;
+        int bandwidth = 0;
 
-        if (!mci->get_sdram_scrub_rate) {
-                edac_printk(KERN_WARNING, EDAC_MC,
-                            "Memory scrub rate reading not implemented\n");
+        if (!mci->get_sdram_scrub_rate)
                 return -EINVAL;
-        }
 
-        err = mci->get_sdram_scrub_rate(mci, &bandwidth);
-        if (err) {
+        bandwidth = mci->get_sdram_scrub_rate(mci);
+        if (bandwidth < 0) {
                 edac_printk(KERN_DEBUG, EDAC_MC, "Error reading scrub rate\n");
-                return err;
-        }
-        else {
-                edac_printk(KERN_DEBUG, EDAC_MC,
-                            "Read scrub rate: %d\n", bandwidth);
-                return sprintf(data, "%d\n", bandwidth);
+                return bandwidth;
         }
+
+        return sprintf(data, "%d\n", bandwidth);
 }
 
 /* default attribute files for the MCI object */
@@ -630,9 +629,6 @@ static void edac_mci_control_release(struct kobject *kobj)
 
         /* decrement the module ref count */
         module_put(mci->owner);
-
-        /* free the mci instance memory here */
-        kfree(mci);
 }
 
 static struct kobj_type ktype_mci = {
@@ -712,6 +708,8 @@ fail_out:
  */
 void edac_mc_unregister_sysfs_main_kobj(struct mem_ctl_info *mci)
 {
+        debugf1("%s()\n", __func__);
+
         /* delete the kobj from the mc_kset */
         kobject_put(&mci->edac_mci_kobj);
 }
@@ -759,8 +757,6 @@ static void edac_inst_grp_release(struct kobject *kobj)
 
         grp = container_of(kobj, struct mcidev_sysfs_group_kobj, kobj);
         mci = grp->mci;
-
-        kobject_put(&mci->edac_mci_kobj);
 }
 
 /* Intermediate show/store table */
@@ -783,14 +779,15 @@ static struct kobj_type ktype_inst_grp = {
  * object tree.
  */
 static int edac_create_mci_instance_attributes(struct mem_ctl_info *mci,
-                                struct mcidev_sysfs_attribute *sysfs_attrib,
+                                const struct mcidev_sysfs_attribute *sysfs_attrib,
                                 struct kobject *kobj)
 {
         int err;
 
-        debugf1("%s()\n", __func__);
+        debugf4("%s()\n", __func__);
 
         while (sysfs_attrib) {
+                debugf4("%s() sysfs_attrib = %p\n",__func__, sysfs_attrib);
                 if (sysfs_attrib->grp) {
                         struct mcidev_sysfs_group_kobj *grp_kobj;
 
@@ -798,10 +795,9 @@ static int edac_create_mci_instance_attributes(struct mem_ctl_info *mci,
                         if (!grp_kobj)
                                 return -ENOMEM;
 
-                        list_add_tail(&grp_kobj->list, &mci->grp_kobj_list);
-
                         grp_kobj->grp = sysfs_attrib->grp;
                         grp_kobj->mci = mci;
+                        list_add_tail(&grp_kobj->list, &mci->grp_kobj_list);
 
                         debugf0("%s() grp %s, mci %p\n", __func__,
                                 sysfs_attrib->grp->name, mci);
@@ -810,26 +806,28 @@ static int edac_create_mci_instance_attributes(struct mem_ctl_info *mci,
                                                 &ktype_inst_grp,
                                                 &mci->edac_mci_kobj,
                                                 sysfs_attrib->grp->name);
-                        if (err)
+                        if (err < 0) {
+                                printk(KERN_ERR "kobject_init_and_add failed: %d\n", err);
                                 return err;
-
+                        }
                         err = edac_create_mci_instance_attributes(mci,
                                         grp_kobj->grp->mcidev_attr,
                                         &grp_kobj->kobj);
 
-                        if (err)
+                        if (err < 0)
                                 return err;
                 } else if (sysfs_attrib->attr.name) {
-                        debugf0("%s() file %s\n", __func__,
+                        debugf4("%s() file %s\n", __func__,
                                 sysfs_attrib->attr.name);
 
                         err = sysfs_create_file(kobj, &sysfs_attrib->attr);
+                        if (err < 0) {
+                                printk(KERN_ERR "sysfs_create_file failed: %d\n", err);
+                                return err;
+                        }
                 } else
                         break;
 
-                if (err) {
-                        return err;
-                }
                 sysfs_attrib++;
         }
 
@@ -842,7 +840,7 @@ static int edac_create_mci_instance_attributes(struct mem_ctl_info *mci,
  *      directory of this mci instance.
  */
 static void edac_remove_mci_instance_attributes(struct mem_ctl_info *mci,
-                                struct mcidev_sysfs_attribute *sysfs_attrib,
+                                const struct mcidev_sysfs_attribute *sysfs_attrib,
                                 struct kobject *kobj, int count)
 {
         struct mcidev_sysfs_group_kobj *grp_kobj, *tmp;
@@ -851,18 +849,29 @@ static void edac_remove_mci_instance_attributes(struct mem_ctl_info *mci,
 
         /*
          * loop if there are attributes and until we hit a NULL entry
-         * Remove first all the atributes
+         * Remove first all the attributes
          */
         while (sysfs_attrib) {
+                debugf4("%s() sysfs_attrib = %p\n",__func__, sysfs_attrib);
                 if (sysfs_attrib->grp) {
-                        list_for_each_entry(grp_kobj, &mci->grp_kobj_list,
-                                            list)
-                                if (grp_kobj->grp == sysfs_attrib->grp)
+                        debugf4("%s() seeking for group %s\n",
+                                __func__, sysfs_attrib->grp->name);
+                        list_for_each_entry(grp_kobj,
+                                            &mci->grp_kobj_list, list) {
+                                debugf4("%s() grp_kobj->grp = %p\n",__func__, grp_kobj->grp);
+                                if (grp_kobj->grp == sysfs_attrib->grp) {
                                         edac_remove_mci_instance_attributes(mci,
                                                     grp_kobj->grp->mcidev_attr,
                                                     &grp_kobj->kobj, count + 1);
+                                        debugf4("%s() group %s\n", __func__,
+                                                sysfs_attrib->grp->name);
+                                        kobject_put(&grp_kobj->kobj);
+                                }
+                        }
+                        debugf4("%s() end of seeking for group %s\n",
+                                __func__, sysfs_attrib->grp->name);
                 } else if (sysfs_attrib->attr.name) {
-                        debugf0("%s() file %s\n", __func__,
+                        debugf4("%s() file %s\n", __func__,
                                 sysfs_attrib->attr.name);
                         sysfs_remove_file(kobj, &sysfs_attrib->attr);
                 } else
@@ -870,15 +879,14 @@ static void edac_remove_mci_instance_attributes(struct mem_ctl_info *mci,
                 sysfs_attrib++;
         }
 
-        /*
-         * Now that all attributes got removed, it is save to remove all groups
-         */
-        if (!count)
-                list_for_each_entry_safe(grp_kobj, tmp, &mci->grp_kobj_list,
-                                         list) {
-                        debugf0("%s() grp %s\n", __func__, grp_kobj->grp->name);
-                        kobject_put(&grp_kobj->kobj);
-                }
+        /* Remove the group objects */
+        if (count)
+                return;
+        list_for_each_entry_safe(grp_kobj, tmp,
+                                 &mci->grp_kobj_list, list) {
+                list_del(&grp_kobj->list);
+                kfree(grp_kobj);
+        }
 }
 
 
@@ -970,6 +978,7 @@ void edac_remove_sysfs_mci_device(struct mem_ctl_info *mci)
         debugf0("%s()\n", __func__);
 
         /* remove all csrow kobjects */
+        debugf4("%s()  unregister this mci kobj\n", __func__);
         for (i = 0; i < mci->nr_csrows; i++) {
                 if (mci->csrows[i].nr_pages > 0) {
                         debugf0("%s()  unreg csrow-%d\n", __func__, i);
@@ -977,20 +986,20 @@ void edac_remove_sysfs_mci_device(struct mem_ctl_info *mci)
                 }
         }
 
-        debugf0("%s()  remove_link\n", __func__);
+        /* remove this mci instance's attribtes */
+        if (mci->mc_driver_sysfs_attributes) {
+                debugf4("%s()  unregister mci private attributes\n", __func__);
+                edac_remove_mci_instance_attributes(mci,
+                                                mci->mc_driver_sysfs_attributes,
+                                                &mci->edac_mci_kobj, 0);
+        }
 
         /* remove the symlink */
+        debugf4("%s()  remove_link\n", __func__);
         sysfs_remove_link(&mci->edac_mci_kobj, EDAC_DEVICE_SYMLINK);
 
-        debugf0("%s()  remove_mci_instance\n", __func__);
-
-        /* remove this mci instance's attribtes */
-        edac_remove_mci_instance_attributes(mci,
-                                            mci->mc_driver_sysfs_attributes,
-                                            &mci->edac_mci_kobj, 0);
-        debugf0("%s()  unregister this mci kobj\n", __func__);
-
         /* unregister this instance's kobject */
+        debugf4("%s()  remove_mci_instance\n", __func__);
         kobject_put(&mci->edac_mci_kobj);
 }
 
@@ -1011,13 +1020,13 @@ void edac_remove_sysfs_mci_device(struct mem_ctl_info *mci)
  */
 int edac_sysfs_setup_mc_kset(void)
 {
-        int err = 0;
+        int err = -EINVAL;
         struct sysdev_class *edac_class;
 
         debugf1("%s()\n", __func__);
 
         /* get the /sys/devices/system/edac class reference */
-        edac_class = edac_get_edac_class();
+        edac_class = edac_get_sysfs_class();
         if (edac_class == NULL) {
                 debugf1("%s() no edac_class error=%d\n", __func__, err);
                 goto fail_out;
@@ -1028,15 +1037,16 @@ int edac_sysfs_setup_mc_kset(void)
         if (!mc_kset) {
                 err = -ENOMEM;
                 debugf1("%s() Failed to register '.../edac/mc'\n", __func__);
-                goto fail_out;
+                goto fail_kset;
         }
 
         debugf1("%s() Registered '.../edac/mc' kobject\n", __func__);
 
         return 0;
 
+fail_kset:
+        edac_put_sysfs_class();
 
-        /* error unwind stack */
 fail_out:
         return err;
 }
@@ -1049,5 +1059,6 @@ fail_out:
 void edac_sysfs_teardown_mc_kset(void)
 {
         kset_unregister(mc_kset);
+        edac_put_sysfs_class();
 }
 
diff --git a/drivers/edac/edac_mce_amd.c b/drivers/edac/edac_mce_amd.c
deleted file mode 100644
index 9014df6f605d..000000000000
--- a/drivers/edac/edac_mce_amd.c
+++ /dev/null
@@ -1,452 +0,0 @@
-#include <linux/module.h>
-#include "edac_mce_amd.h"
-
-static bool report_gart_errors;
-static void (*nb_bus_decoder)(int node_id, struct err_regs *regs);
-
-void amd_report_gart_errors(bool v)
-{
-        report_gart_errors = v;
-}
-EXPORT_SYMBOL_GPL(amd_report_gart_errors);
-
-void amd_register_ecc_decoder(void (*f)(int, struct err_regs *))
-{
-        nb_bus_decoder = f;
-}
-EXPORT_SYMBOL_GPL(amd_register_ecc_decoder);
-
-void amd_unregister_ecc_decoder(void (*f)(int, struct err_regs *))
-{
-        if (nb_bus_decoder) {
-                WARN_ON(nb_bus_decoder != f);
-
-                nb_bus_decoder = NULL;
-        }
-}
-EXPORT_SYMBOL_GPL(amd_unregister_ecc_decoder);
-
-/*
- * string representation for the different MCA reported error types, see F3x48
- * or MSR0000_0411.
- */
-const char *tt_msgs[] = {        /* transaction type */
-        "instruction",
-        "data",
-        "generic",
-        "reserved"
-};
-EXPORT_SYMBOL_GPL(tt_msgs);
-
-const char *ll_msgs[] = {       /* cache level */
-        "L0",
-        "L1",
-        "L2",
-        "L3/generic"
-};
-EXPORT_SYMBOL_GPL(ll_msgs);
-
-const char *rrrr_msgs[] = {
-        "generic",
-        "generic read",
-        "generic write",
-        "data read",
-        "data write",
-        "inst fetch",
-        "prefetch",
-        "evict",
-        "snoop",
-        "reserved RRRR= 9",
-        "reserved RRRR= 10",
-        "reserved RRRR= 11",
-        "reserved RRRR= 12",
-        "reserved RRRR= 13",
-        "reserved RRRR= 14",
-        "reserved RRRR= 15"
-};
-EXPORT_SYMBOL_GPL(rrrr_msgs);
-
-const char *pp_msgs[] = {       /* participating processor */
-        "local node originated (SRC)",
-        "local node responded to request (RES)",
-        "local node observed as 3rd party (OBS)",
-        "generic"
-};
-EXPORT_SYMBOL_GPL(pp_msgs);
-
-const char *to_msgs[] = {
-        "no timeout",
-        "timed out"
-};
-EXPORT_SYMBOL_GPL(to_msgs);
-
-const char *ii_msgs[] = {       /* memory or i/o */
-        "mem access",
-        "reserved",
-        "i/o access",
-        "generic"
-};
-EXPORT_SYMBOL_GPL(ii_msgs);
-
-/*
- * Map the 4 or 5 (family-specific) bits of Extended Error code to the
- * string table.
- */
-const char *ext_msgs[] = {
-        "K8 ECC error",                                 /* 0_0000b */
-        "CRC error on link",                            /* 0_0001b */
-        "Sync error packets on link",                   /* 0_0010b */
-        "Master Abort during link operation",           /* 0_0011b */
-        "Target Abort during link operation",           /* 0_0100b */
-        "Invalid GART PTE entry during table walk",     /* 0_0101b */
-        "Unsupported atomic RMW command received",      /* 0_0110b */
-        "WDT error: NB transaction timeout",            /* 0_0111b */
-        "ECC/ChipKill ECC error",                       /* 0_1000b */
-        "SVM DEV Error",                                /* 0_1001b */
-        "Link Data error",                              /* 0_1010b */
-        "Link/L3/Probe Filter Protocol error",          /* 0_1011b */
-        "NB Internal Arrays Parity error",              /* 0_1100b */
-        "DRAM Address/Control Parity error",            /* 0_1101b */
-        "Link Transmission error",                      /* 0_1110b */
-        "GART/DEV Table Walk Data error"                /* 0_1111b */
-        "Res 0x100 error",                              /* 1_0000b */
-        "Res 0x101 error",                              /* 1_0001b */
-        "Res 0x102 error",                              /* 1_0010b */
-        "Res 0x103 error",                              /* 1_0011b */
-        "Res 0x104 error",                              /* 1_0100b */
-        "Res 0x105 error",                              /* 1_0101b */
-        "Res 0x106 error",                              /* 1_0110b */
-        "Res 0x107 error",                              /* 1_0111b */
-        "Res 0x108 error",                              /* 1_1000b */
-        "Res 0x109 error",                              /* 1_1001b */
-        "Res 0x10A error",                              /* 1_1010b */
-        "Res 0x10B error",                              /* 1_1011b */
-        "ECC error in L3 Cache Data",                   /* 1_1100b */
-        "L3 Cache Tag error",                           /* 1_1101b */
-        "L3 Cache LRU Parity error",                    /* 1_1110b */
-        "Probe Filter error"                            /* 1_1111b */
-};
-EXPORT_SYMBOL_GPL(ext_msgs);
-
-static void amd_decode_dc_mce(u64 mc0_status)
-{
-        u32 ec  = mc0_status & 0xffff;
-        u32 xec = (mc0_status >> 16) & 0xf;
-
-        pr_emerg("Data Cache Error");
-
-        if (xec == 1 && TLB_ERROR(ec))
-                pr_cont(": %s TLB multimatch.\n", LL_MSG(ec));
-        else if (xec == 0) {
-                if (mc0_status & (1ULL << 40))
-                        pr_cont(" during Data Scrub.\n");
-                else if (TLB_ERROR(ec))
-                        pr_cont(": %s TLB parity error.\n", LL_MSG(ec));
-                else if (MEM_ERROR(ec)) {
-                        u8 ll   = ec & 0x3;
-                        u8 tt   = (ec >> 2) & 0x3;
-                        u8 rrrr = (ec >> 4) & 0xf;
-
-                        /* see F10h BKDG (31116), Table 92. */
-                        if (ll == 0x1) {
-                                if (tt != 0x1)
-                                        goto wrong_dc_mce;
-
-                                pr_cont(": Data/Tag %s error.\n", RRRR_MSG(ec));
-
-                        } else if (ll == 0x2 && rrrr == 0x3)
-                                pr_cont(" during L1 linefill from L2.\n");
-                        else
-                                goto wrong_dc_mce;
-                } else if (BUS_ERROR(ec) && boot_cpu_data.x86 == 0xf)
-                        pr_cont(" during system linefill.\n");
-                else
-                        goto wrong_dc_mce;
-        } else
-                goto wrong_dc_mce;
-
-        return;
-
-wrong_dc_mce:
-        pr_warning("Corrupted DC MCE info?\n");
-}
-
-static void amd_decode_ic_mce(u64 mc1_status)
-{
-        u32 ec  = mc1_status & 0xffff;
-        u32 xec = (mc1_status >> 16) & 0xf;
-
-        pr_emerg("Instruction Cache Error");
-
-        if (xec == 1 && TLB_ERROR(ec))
-                pr_cont(": %s TLB multimatch.\n", LL_MSG(ec));
-        else if (xec == 0) {
-                if (TLB_ERROR(ec))
-                        pr_cont(": %s TLB Parity error.\n", LL_MSG(ec));
-                else if (BUS_ERROR(ec)) {
-                        if (boot_cpu_data.x86 == 0xf &&
-                            (mc1_status & (1ULL << 58)))
-                                pr_cont(" during system linefill.\n");
-                        else
-                                pr_cont(" during attempted NB data read.\n");
-                } else if (MEM_ERROR(ec)) {
-                        u8 ll   = ec & 0x3;
-                        u8 rrrr = (ec >> 4) & 0xf;
-
-                        if (ll == 0x2)
-                                pr_cont(" during a linefill from L2.\n");
-                        else if (ll == 0x1) {
-
-                                switch (rrrr) {
-                                case 0x5:
-                                        pr_cont(": Parity error during "
-                                               "data load.\n");
-                                        break;
-
-                                case 0x7:
-                                        pr_cont(": Copyback Parity/Victim"
-                                                " error.\n");
-                                        break;
-
-                                case 0x8:
-                                        pr_cont(": Tag Snoop error.\n");
-                                        break;
-
-                                default:
-                                        goto wrong_ic_mce;
-                                        break;
-                                }
-                        }
-                } else
-                        goto wrong_ic_mce;
-        } else
-                goto wrong_ic_mce;
-
-        return;
-
-wrong_ic_mce:
-        pr_warning("Corrupted IC MCE info?\n");
-}
-
-static void amd_decode_bu_mce(u64 mc2_status)
-{
-        u32 ec = mc2_status & 0xffff;
-        u32 xec = (mc2_status >> 16) & 0xf;
-
-        pr_emerg("Bus Unit Error");
-
-        if (xec == 0x1)
-                pr_cont(" in the write data buffers.\n");
-        else if (xec == 0x3)
-                pr_cont(" in the victim data buffers.\n");
-        else if (xec == 0x2 && MEM_ERROR(ec))
-                pr_cont(": %s error in the L2 cache tags.\n", RRRR_MSG(ec));
-        else if (xec == 0x0) {
-                if (TLB_ERROR(ec))
-                        pr_cont(": %s error in a Page Descriptor Cache or "
-                                "Guest TLB.\n", TT_MSG(ec));
-                else if (BUS_ERROR(ec))
-                        pr_cont(": %s/ECC error in data read from NB: %s.\n",
-                                RRRR_MSG(ec), PP_MSG(ec));
-                else if (MEM_ERROR(ec)) {
-                        u8 rrrr = (ec >> 4) & 0xf;
-
-                        if (rrrr >= 0x7)
-                                pr_cont(": %s error during data copyback.\n",
-                                        RRRR_MSG(ec));
-                        else if (rrrr <= 0x1)
-                                pr_cont(": %s parity/ECC error during data "
-                                        "access from L2.\n", RRRR_MSG(ec));
-                        else
-                                goto wrong_bu_mce;
-                } else
-                        goto wrong_bu_mce;
-        } else
-                goto wrong_bu_mce;
-
-        return;
-
-wrong_bu_mce:
-        pr_warning("Corrupted BU MCE info?\n");
-}
-
-static void amd_decode_ls_mce(u64 mc3_status)
-{
-        u32 ec  = mc3_status & 0xffff;
-        u32 xec = (mc3_status >> 16) & 0xf;
-
-        pr_emerg("Load Store Error");
-
-        if (xec == 0x0) {
-                u8 rrrr = (ec >> 4) & 0xf;
-
-                if (!BUS_ERROR(ec) || (rrrr != 0x3 && rrrr != 0x4))
-                        goto wrong_ls_mce;
-
-                pr_cont(" during %s.\n", RRRR_MSG(ec));
-        }
-        return;
-
-wrong_ls_mce:
-        pr_warning("Corrupted LS MCE info?\n");
-}
-
-void amd_decode_nb_mce(int node_id, struct err_regs *regs, int handle_errors)
-{
-        u32 ec  = ERROR_CODE(regs->nbsl);
-
-        if (!handle_errors)
-                return;
-
-        /*
-         * GART TLB error reporting is disabled by default. Bail out early.
-         */
-        if (TLB_ERROR(ec) && !report_gart_errors)
-                return;
-
-        pr_emerg("Northbridge Error, node %d", node_id);
-
-        /*
-         * F10h, revD can disable ErrCpu[3:0] so check that first and also the
-         * value encoding has changed so interpret those differently
-         */
-        if ((boot_cpu_data.x86 == 0x10) &&
-            (boot_cpu_data.x86_model > 7)) {
-                if (regs->nbsh & K8_NBSH_ERR_CPU_VAL)
-                        pr_cont(", core: %u\n", (u8)(regs->nbsh & 0xf));
-        } else {
-                u8 assoc_cpus = regs->nbsh & 0xf;
-
-                if (assoc_cpus > 0)
-                        pr_cont(", core: %d", fls(assoc_cpus) - 1);
-
-                pr_cont("\n");
-        }
-
-        pr_emerg("%s.\n", EXT_ERR_MSG(regs->nbsl));
-
-        if (BUS_ERROR(ec) && nb_bus_decoder)
-                nb_bus_decoder(node_id, regs);
-}
-EXPORT_SYMBOL_GPL(amd_decode_nb_mce);
-
-static void amd_decode_fr_mce(u64 mc5_status)
-{
-        /* we have only one error signature so match all fields at once. */
-        if ((mc5_status & 0xffff) == 0x0f0f)
-                pr_emerg(" FR Error: CPU Watchdog timer expire.\n");
-        else
-                pr_warning("Corrupted FR MCE info?\n");
-}
-
-static inline void amd_decode_err_code(unsigned int ec)
-{
-        if (TLB_ERROR(ec)) {
-                pr_emerg("Transaction: %s, Cache Level %s\n",
-                         TT_MSG(ec), LL_MSG(ec));
-        } else if (MEM_ERROR(ec)) {
-                pr_emerg("Transaction: %s, Type: %s, Cache Level: %s",
-                         RRRR_MSG(ec), TT_MSG(ec), LL_MSG(ec));
-        } else if (BUS_ERROR(ec)) {
-                pr_emerg("Transaction type: %s(%s), %s, Cache Level: %s, "
-                         "Participating Processor: %s\n",
-                          RRRR_MSG(ec), II_MSG(ec), TO_MSG(ec), LL_MSG(ec),
-                          PP_MSG(ec));
-        } else
-                pr_warning("Huh? Unknown MCE error 0x%x\n", ec);
-}
-
-static int amd_decode_mce(struct notifier_block *nb, unsigned long val,
-                           void *data)
-{
-        struct mce *m = (struct mce *)data;
-        struct err_regs regs;
-        int node, ecc;
-
-        pr_emerg("MC%d_STATUS: ", m->bank);
-
-        pr_cont("%sorrected error, other errors lost: %s, "
-                 "CPU context corrupt: %s",
-                 ((m->status & MCI_STATUS_UC) ? "Unc"  : "C"),
-                 ((m->status & MCI_STATUS_OVER) ? "yes"  : "no"),
-                 ((m->status & MCI_STATUS_PCC) ? "yes" : "no"));
-
-        /* do the two bits[14:13] together */
-        ecc = (m->status >> 45) & 0x3;
-        if (ecc)
-                pr_cont(", %sECC Error", ((ecc == 2) ? "C" : "U"));
-
-        pr_cont("\n");
-
-        switch (m->bank) {
-        case 0:
-                amd_decode_dc_mce(m->status);
-                break;
-
-        case 1:
-                amd_decode_ic_mce(m->status);
-                break;
-
-        case 2:
-                amd_decode_bu_mce(m->status);
-                break;
-
-        case 3:
-                amd_decode_ls_mce(m->status);
-                break;
-
-        case 4:
-                regs.nbsl  = (u32) m->status;
-                regs.nbsh  = (u32)(m->status >> 32);
-                regs.nbeal = (u32) m->addr;
-                regs.nbeah = (u32)(m->addr >> 32);
-                node       = amd_get_nb_id(m->extcpu);
-
-                amd_decode_nb_mce(node, &regs, 1);
-                break;
-
-        case 5:
-                amd_decode_fr_mce(m->status);
-                break;
-
-        default:
-                break;
-        }
-
-        amd_decode_err_code(m->status & 0xffff);
-
-        return NOTIFY_STOP;
-}
-
-static struct notifier_block amd_mce_dec_nb = {
-        .notifier_call  = amd_decode_mce,
-};
-
-static int __init mce_amd_init(void)
-{
-        /*
-         * We can decode MCEs for K8, F10h and F11h CPUs:
-         */
-        if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
-                return 0;
-
-        if (boot_cpu_data.x86 < 0xf || boot_cpu_data.x86 > 0x11)
-                return 0;
-
-        atomic_notifier_chain_register(&x86_mce_decoder_chain, &amd_mce_dec_nb);
-
-        return 0;
-}
-early_initcall(mce_amd_init);
-
-#ifdef MODULE
-static void __exit mce_amd_exit(void)
-{
-        atomic_notifier_chain_unregister(&x86_mce_decoder_chain, &amd_mce_dec_nb);
-}
-
-MODULE_DESCRIPTION("AMD MCE decoder");
-MODULE_ALIAS("edac-mce-amd");
-MODULE_LICENSE("GPL");
-module_exit(mce_amd_exit);
-#endif
diff --git a/drivers/edac/edac_mce_amd.h b/drivers/edac/edac_mce_amd.h
deleted file mode 100644
index df23ee065f79..000000000000
--- a/drivers/edac/edac_mce_amd.h
+++ /dev/null
@@ -1,69 +0,0 @@
-#ifndef _EDAC_MCE_AMD_H
-#define _EDAC_MCE_AMD_H
-
-#include <asm/mce.h>
-
-#define ERROR_CODE(x)                   ((x) & 0xffff)
-#define EXT_ERROR_CODE(x)               (((x) >> 16) & 0x1f)
-#define EXT_ERR_MSG(x)                  ext_msgs[EXT_ERROR_CODE(x)]
-
-#define LOW_SYNDROME(x)                 (((x) >> 15) & 0xff)
-#define HIGH_SYNDROME(x)                (((x) >> 24) & 0xff)
-
-#define TLB_ERROR(x)                    (((x) & 0xFFF0) == 0x0010)
-#define MEM_ERROR(x)                    (((x) & 0xFF00) == 0x0100)
-#define BUS_ERROR(x)                    (((x) & 0xF800) == 0x0800)
-
-#define TT(x)                           (((x) >> 2) & 0x3)
-#define TT_MSG(x)                       tt_msgs[TT(x)]
-#define II(x)                           (((x) >> 2) & 0x3)
-#define II_MSG(x)                       ii_msgs[II(x)]
-#define LL(x)                           (((x) >> 0) & 0x3)
-#define LL_MSG(x)                       ll_msgs[LL(x)]
-#define RRRR(x)                         (((x) >> 4) & 0xf)
-#define RRRR_MSG(x)                     rrrr_msgs[RRRR(x)]
-#define TO(x)                           (((x) >> 8) & 0x1)
-#define TO_MSG(x)                       to_msgs[TO(x)]
-#define PP(x)                           (((x) >> 9) & 0x3)
-#define PP_MSG(x)                       pp_msgs[PP(x)]
-
-#define K8_NBSH                         0x4C
-
-#define K8_NBSH_VALID_BIT               BIT(31)
-#define K8_NBSH_OVERFLOW                BIT(30)
-#define K8_NBSH_UC_ERR                  BIT(29)
-#define K8_NBSH_ERR_EN                  BIT(28)
-#define K8_NBSH_MISCV                   BIT(27)
-#define K8_NBSH_VALID_ERROR_ADDR        BIT(26)
-#define K8_NBSH_PCC                     BIT(25)
-#define K8_NBSH_ERR_CPU_VAL             BIT(24)
-#define K8_NBSH_CECC                    BIT(14)
-#define K8_NBSH_UECC                    BIT(13)
-#define K8_NBSH_ERR_SCRUBER             BIT(8)
-
-extern const char *tt_msgs[];
-extern const char *ll_msgs[];
-extern const char *rrrr_msgs[];
-extern const char *pp_msgs[];
-extern const char *to_msgs[];
-extern const char *ii_msgs[];
-extern const char *ext_msgs[];
-
-/*
- * relevant NB regs
- */
-struct err_regs {
-        u32 nbcfg;
-        u32 nbsh;
-        u32 nbsl;
-        u32 nbeah;
-        u32 nbeal;
-};
-
-
-void amd_report_gart_errors(bool);
-void amd_register_ecc_decoder(void (*f)(int, struct err_regs *));
-void amd_unregister_ecc_decoder(void (*f)(int, struct err_regs *));
-void amd_decode_nb_mce(int, struct err_regs *, int);
-
-#endif /* _EDAC_MCE_AMD_H */
diff --git a/drivers/edac/edac_module.c b/drivers/edac/edac_module.c
index 7e1374afd967..5ddaa86d6a6e 100644
--- a/drivers/edac/edac_module.c
+++ b/drivers/edac/edac_module.c
@@ -15,7 +15,7 @@
 #include "edac_core.h"
 #include "edac_module.h"
 
-#define EDAC_VERSION "Ver: 2.1.0 " __DATE__
+#define EDAC_VERSION "Ver: 2.1.0"
 
 #ifdef CONFIG_EDAC_DEBUG
 /* Values of 0 to 4 will generate output */
@@ -27,15 +27,6 @@ EXPORT_SYMBOL_GPL(edac_debug_level);
 struct workqueue_struct *edac_workqueue;
 
 /*
- * sysfs object: /sys/devices/system/edac
- *      need to export to other files in this modules
- */
-static struct sysdev_class edac_class = {
-        .name = "edac",
-};
-static int edac_class_valid;
-
-/*
  * edac_op_state_to_string()
  */
 char *edac_op_state_to_string(int opstate)
@@ -55,60 +46,6 @@ char *edac_op_state_to_string(int opstate)
 }
 
 /*
- * edac_get_edac_class()
- *
- *      return pointer to the edac class of 'edac'
- */
-struct sysdev_class *edac_get_edac_class(void)
-{
-        struct sysdev_class *classptr = NULL;
-
-        if (edac_class_valid)
-                classptr = &edac_class;
-
-        return classptr;
-}
-
-/*
- * edac_register_sysfs_edac_name()
- *
- *      register the 'edac' into /sys/devices/system
- *
- * return:
- *      0  success
- *      !0 error
- */
-static int edac_register_sysfs_edac_name(void)
-{
-        int err;
-
-        /* create the /sys/devices/system/edac directory */
-        err = sysdev_class_register(&edac_class);
-
-        if (err) {
-                debugf1("%s() error=%d\n", __func__, err);
-                return err;
-        }
-
-        edac_class_valid = 1;
-        return 0;
-}
-
-/*
- * sysdev_class_unregister()
- *
- *      unregister the 'edac' from /sys/devices/system
- */
-static void edac_unregister_sysfs_edac_name(void)
-{
-        /* only if currently registered, then unregister it */
-        if (edac_class_valid)
-                sysdev_class_unregister(&edac_class);
-
-        edac_class_valid = 0;
-}
-
-/*
  * edac_workqueue_setup
  *      initialize the edac work queue for polling operations
  */
@@ -154,21 +91,11 @@ static int __init edac_init(void)
         edac_pci_clear_parity_errors();
 
         /*
-         * perform the registration of the /sys/devices/system/edac class object
-         */
-        if (edac_register_sysfs_edac_name()) {
-                edac_printk(KERN_ERR, EDAC_MC,
-                        "Error initializing 'edac' kobject\n");
-                err = -ENODEV;
-                goto error;
-        }
-
-        /*
          * now set up the mc_kset under the edac class object
          */
         err = edac_sysfs_setup_mc_kset();
         if (err)
-                goto sysfs_setup_fail;
+                goto error;
 
         /* Setup/Initialize the workq for this core */
         err = edac_workqueue_setup();
@@ -183,9 +110,6 @@ static int __init edac_init(void)
 workq_fail:
         edac_sysfs_teardown_mc_kset();
 
-sysfs_setup_fail:
-        edac_unregister_sysfs_edac_name();
-
 error:
         return err;
 }
@@ -201,7 +125,6 @@ static void __exit edac_exit(void)
         /* tear down the various subsystems */
         edac_workqueue_teardown();
         edac_sysfs_teardown_mc_kset();
-        edac_unregister_sysfs_edac_name();
 }
 
 /*
diff --git a/drivers/edac/edac_module.h b/drivers/edac/edac_module.h
index 233d4798c3aa..17aabb7b90ec 100644
--- a/drivers/edac/edac_module.h
+++ b/drivers/edac/edac_module.h
@@ -42,7 +42,6 @@ extern void edac_device_unregister_sysfs_main_kobj(
                                 struct edac_device_ctl_info *edac_dev);
 extern int edac_device_create_sysfs(struct edac_device_ctl_info *edac_dev);
 extern void edac_device_remove_sysfs(struct edac_device_ctl_info *edac_dev);
-extern struct sysdev_class *edac_get_edac_class(void);
 
 /* edac core workqueue: single CPU mode */
 extern struct workqueue_struct *edac_workqueue;
diff --git a/drivers/edac/edac_pci.c b/drivers/edac/edac_pci.c
index efb5d5650783..2b378207d571 100644
--- a/drivers/edac/edac_pci.c
+++ b/drivers/edac/edac_pci.c
@@ -164,19 +164,6 @@ fail1:
 }
 
 /*
- * complete_edac_pci_list_del
- *
- *      RCU completion callback to indicate item is deleted
- */
-static void complete_edac_pci_list_del(struct rcu_head *head)
-{
-        struct edac_pci_ctl_info *pci;
-
-        pci = container_of(head, struct edac_pci_ctl_info, rcu);
-        INIT_LIST_HEAD(&pci->link);
-}
-
-/*
  * del_edac_pci_from_global_list
  *
  *      remove the PCI control struct from the global list
@@ -184,8 +171,12 @@ static void complete_edac_pci_list_del(struct rcu_head *head)
 static void del_edac_pci_from_global_list(struct edac_pci_ctl_info *pci)
 {
         list_del_rcu(&pci->link);
-        call_rcu(&pci->rcu, complete_edac_pci_list_del);
-        rcu_barrier();
+
+        /* these are for safe removal of devices from global list while
+         * NMI handlers may be traversing list
+         */
+        synchronize_rcu();
+        INIT_LIST_HEAD(&pci->link);
 }
 
 #if 0
diff --git a/drivers/edac/edac_pci_sysfs.c b/drivers/edac/edac_pci_sysfs.c
index c39697df9cb4..495198ad059c 100644
--- a/drivers/edac/edac_pci_sysfs.c
+++ b/drivers/edac/edac_pci_sysfs.c
@@ -7,7 +7,7 @@
  *
  */
 #include <linux/module.h>
-#include <linux/sysdev.h>
+#include <linux/edac.h>
 #include <linux/slab.h>
 #include <linux/ctype.h>
 
@@ -352,9 +352,9 @@ static int edac_pci_main_kobj_setup(void)
                 return 0;
 
         /* First time, so create the main kobject and its
-         * controls and atributes
+         * controls and attributes
          */
-        edac_class = edac_get_edac_class();
+        edac_class = edac_get_sysfs_class();
         if (edac_class == NULL) {
                 debugf1("%s() no edac_class\n", __func__);
                 err = -ENODEV;
@@ -368,7 +368,7 @@ static int edac_pci_main_kobj_setup(void)
         if (!try_module_get(THIS_MODULE)) {
                 debugf1("%s() try_module_get() failed\n", __func__);
                 err = -ENODEV;
-                goto decrement_count_fail;
+                goto mod_get_fail;
         }
 
         edac_pci_top_main_kobj = kzalloc(sizeof(struct kobject), GFP_KERNEL);
@@ -403,6 +403,9 @@ kobject_init_and_add_fail:
 kzalloc_fail:
         module_put(THIS_MODULE);
 
+mod_get_fail:
+        edac_put_sysfs_class();
+
 decrement_count_fail:
         /* if are on this error exit, nothing to tear down */
         atomic_dec(&edac_pci_sysfs_refcount);
@@ -429,6 +432,7 @@ static void edac_pci_main_kobj_teardown(void)
                         __func__);
                 kobject_put(edac_pci_top_main_kobj);
         }
+        edac_put_sysfs_class();
 }
 
 /*
@@ -547,7 +551,7 @@ static void edac_pci_dev_parity_clear(struct pci_dev *dev)
 /*
  *  PCI Parity polling
  *
- *      Fucntion to retrieve the current parity status
+ *      Function to retrieve the current parity status
  *      and decode it
  *
  */
diff --git a/drivers/edac/edac_stub.c b/drivers/edac/edac_stub.c
index 20b428aa155e..aab970760b75 100644
--- a/drivers/edac/edac_stub.c
+++ b/drivers/edac/edac_stub.c
@@ -3,10 +3,13 @@
  *
  * Author: Dave Jiang <djiang@mvista.com>
  *
- * 2007 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
+ * 2007 (c) MontaVista Software, Inc.
+ * 2010 (c) Advanced Micro Devices Inc.
+ *          Borislav Petkov <borislav.petkov@amd.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
  *
  */
 #include <linux/module.h>
@@ -23,6 +26,8 @@ EXPORT_SYMBOL_GPL(edac_handlers);
 int edac_err_assert = 0;
 EXPORT_SYMBOL_GPL(edac_err_assert);
 
+static atomic_t edac_class_valid = ATOMIC_INIT(0);
+
 /*
  * called to determine if there is an EDAC driver interested in
  * knowing an event (such as NMI) occurred
@@ -44,3 +49,41 @@ void edac_atomic_assert_error(void)
         edac_err_assert++;
 }
 EXPORT_SYMBOL_GPL(edac_atomic_assert_error);
+
+/*
+ * sysfs object: /sys/devices/system/edac
+ *      need to export to other files
+ */
+struct sysdev_class edac_class = {
+        .name = "edac",
+};
+EXPORT_SYMBOL_GPL(edac_class);
+
+/* return pointer to the 'edac' node in sysfs */
+struct sysdev_class *edac_get_sysfs_class(void)
+{
+        int err = 0;
+
+        if (atomic_read(&edac_class_valid))
+                goto out;
+
+        /* create the /sys/devices/system/edac directory */
+        err = sysdev_class_register(&edac_class);
+        if (err) {
+                printk(KERN_ERR "Error registering toplevel EDAC sysfs dir\n");
+                return NULL;
+        }
+
+out:
+        atomic_inc(&edac_class_valid);
+        return &edac_class;
+}
+EXPORT_SYMBOL_GPL(edac_get_sysfs_class);
+
+void edac_put_sysfs_class(void)
+{
+        /* last user unregisters it */
+        if (atomic_dec_and_test(&edac_class_valid))
+                sysdev_class_unregister(&edac_class);
+}
+EXPORT_SYMBOL_GPL(edac_put_sysfs_class);
diff --git a/drivers/edac/i3200_edac.c b/drivers/edac/i3200_edac.c
index d41f9002da45..aa08497a075a 100644
--- a/drivers/edac/i3200_edac.c
+++ b/drivers/edac/i3200_edac.c
@@ -101,6 +101,19 @@ struct i3200_priv {
 
 static int nr_channels;
 
+#ifndef readq
+static inline __u64 readq(const volatile void __iomem *addr)
+{
+        const volatile u32 __iomem *p = addr;
+        u32 low, high;
+
+        low = readl(p);
+        high = readl(p + 1);
+
+        return low + ((u64)high << 32);
+}
+#endif
+
 static int how_many_channels(struct pci_dev *pdev)
 {
         unsigned char capid0_8b; /* 8th byte of CAPID0 */
diff --git a/drivers/edac/i5000_edac.c b/drivers/edac/i5000_edac.c
index a5cefab8d65d..4dc3ac25a422 100644
--- a/drivers/edac/i5000_edac.c
+++ b/drivers/edac/i5000_edac.c
@@ -27,7 +27,7 @@
 /*
  * Alter this version for the I5000 module when modifications are made
  */
-#define I5000_REVISION    " Ver: 2.0.12 " __DATE__
+#define I5000_REVISION    " Ver: 2.0.12"
 #define EDAC_MOD_STR      "i5000_edac"
 
 #define i5000_printk(level, fmt, arg...) \
@@ -1372,7 +1372,7 @@ static int i5000_probe1(struct pci_dev *pdev, int dev_idx)
          * actual number of slots/dimms per channel, we thus utilize the
          * resource as specified by the chipset. Thus, we might have
          * have more DIMMs per channel than actually on the mobo, but this
-         * allows the driver to support upto the chipset max, without
+         * allows the driver to support up to the chipset max, without
          * some fancy mobo determination.
          */
         i5000_get_dimm_and_channel_counts(pdev, &num_dimms_per_channel,
diff --git a/drivers/edac/i5100_edac.c b/drivers/edac/i5100_edac.c
index f459a6c0886b..bcbdeeca48b8 100644
--- a/drivers/edac/i5100_edac.c
+++ b/drivers/edac/i5100_edac.c
@@ -11,7 +11,7 @@
  *
  * The intel 5100 has two independent channels. EDAC core currently
  * can not reflect this configuration so instead the chip-select
- * rows for each respective channel are layed out one after another,
+ * rows for each respective channel are laid out one after another,
  * the first half belonging to channel 0, the second half belonging
  * to channel 1.
  */
@@ -611,20 +611,17 @@ static int i5100_set_scrub_rate(struct mem_ctl_info *mci, u32 bandwidth)
 
         bandwidth = 5900000 * i5100_mc_scrben(dw);
 
-        return 0;
+        return bandwidth;
 }
 
-static int i5100_get_scrub_rate(struct mem_ctl_info *mci,
-                                u32 *bandwidth)
+static int i5100_get_scrub_rate(struct mem_ctl_info *mci)
 {
         struct i5100_priv *priv = mci->pvt_info;
         u32 dw;
 
         pci_read_config_dword(priv->mc, I5100_MC, &dw);
 
-        *bandwidth = 5900000 * i5100_mc_scrben(dw);
-
-        return 0;
+        return 5900000 * i5100_mc_scrben(dw);
 }
 
 static struct pci_dev *pci_get_device_func(unsigned vendor,
diff --git a/drivers/edac/i5400_edac.c b/drivers/edac/i5400_edac.c
index 38a9be9e1c7c..74d6ec342afb 100644
--- a/drivers/edac/i5400_edac.c
+++ b/drivers/edac/i5400_edac.c
@@ -33,7 +33,7 @@
 /*
  * Alter this version for the I5400 module when modifications are made
  */
-#define I5400_REVISION    " Ver: 1.0.0 " __DATE__
+#define I5400_REVISION    " Ver: 1.0.0"
 
 #define EDAC_MOD_STR      "i5400_edac"
 
@@ -648,7 +648,7 @@ static void i5400_process_nonfatal_error_info(struct mem_ctl_info *mci,
                 return;
         }
 
-        /* Miscelaneous errors */
+        /* Miscellaneous errors */
         errnum = find_first_bit(&allErrors, ARRAY_SIZE(error_name));
 
         branch = extract_fbdchan_indx(info->ferr_nf_fbd);
@@ -1240,7 +1240,7 @@ static int i5400_probe1(struct pci_dev *pdev, int dev_idx)
          * actual number of slots/dimms per channel, we thus utilize the
          * resource as specified by the chipset. Thus, we might have
          * have more DIMMs per channel than actually on the mobo, but this
-         * allows the driver to support upto the chipset max, without
+         * allows the driver to support up to the chipset max, without
          * some fancy mobo determination.
          */
         num_dimms_per_channel = MAX_DIMMS_PER_CHANNEL;
diff --git a/drivers/edac/i7300_edac.c b/drivers/edac/i7300_edac.c
new file mode 100644
index 000000000000..a76fe8366b68
--- /dev/null
+++ b/drivers/edac/i7300_edac.c
@@ -0,0 +1,1247 @@
+/*
+ * Intel 7300 class Memory Controllers kernel module (Clarksboro)
+ *
+ * This file may be distributed under the terms of the
+ * GNU General Public License version 2 only.
+ *
+ * Copyright (c) 2010 by:
+ *       Mauro Carvalho Chehab <mchehab@redhat.com>
+ *
+ * Red Hat Inc. http://www.redhat.com
+ *
+ * Intel 7300 Chipset Memory Controller Hub (MCH) - Datasheet
+ *      http://www.intel.com/Assets/PDF/datasheet/318082.pdf
+ *
+ * TODO: The chipset allow checking for PCI Express errors also. Currently,
+ *       the driver covers only memory error errors
+ *
+ * This driver uses "csrows" EDAC attribute to represent DIMM slot#
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/pci.h>
+#include <linux/pci_ids.h>
+#include <linux/slab.h>
+#include <linux/edac.h>
+#include <linux/mmzone.h>
+
+#include "edac_core.h"
+
+/*
+ * Alter this version for the I7300 module when modifications are made
+ */
+#define I7300_REVISION    " Ver: 1.0.0"
+
+#define EDAC_MOD_STR      "i7300_edac"
+
+#define i7300_printk(level, fmt, arg...) \
+        edac_printk(level, "i7300", fmt, ##arg)
+
+#define i7300_mc_printk(mci, level, fmt, arg...) \
+        edac_mc_chipset_printk(mci, level, "i7300", fmt, ##arg)
+
+/***********************************************
+ * i7300 Limit constants Structs and static vars
+ ***********************************************/
+
+/*
+ * Memory topology is organized as:
+ *      Branch 0 - 2 channels: channels 0 and 1 (FDB0 PCI dev 21.0)
+ *      Branch 1 - 2 channels: channels 2 and 3 (FDB1 PCI dev 22.0)
+ * Each channel can have to 8 DIMM sets (called as SLOTS)
+ * Slots should generally be filled in pairs
+ *      Except on Single Channel mode of operation
+ *              just slot 0/channel0 filled on this mode
+ *      On normal operation mode, the two channels on a branch should be
+ *              filled together for the same SLOT#
+ * When in mirrored mode, Branch 1 replicate memory at Branch 0, so, the four
+ *              channels on both branches should be filled
+ */
+
+/* Limits for i7300 */
+#define MAX_SLOTS               8
+#define MAX_BRANCHES            2
+#define MAX_CH_PER_BRANCH       2
+#define MAX_CHANNELS            (MAX_CH_PER_BRANCH * MAX_BRANCHES)
+#define MAX_MIR                 3
+
+#define to_channel(ch, branch)  ((((branch)) << 1) | (ch))
+
+#define to_csrow(slot, ch, branch)                                      \
+                (to_channel(ch, branch) | ((slot) << 2))
+
+/* Device name and register DID (Device ID) */
+struct i7300_dev_info {
+        const char *ctl_name;   /* name for this device */
+        u16 fsb_mapping_errors; /* DID for the branchmap,control */
+};
+
+/* Table of devices attributes supported by this driver */
+static const struct i7300_dev_info i7300_devs[] = {
+        {
+                .ctl_name = "I7300",
+                .fsb_mapping_errors = PCI_DEVICE_ID_INTEL_I7300_MCH_ERR,
+        },
+};
+
+struct i7300_dimm_info {
+        int megabytes;          /* size, 0 means not present  */
+};
+
+/* driver private data structure */
+struct i7300_pvt {
+        struct pci_dev *pci_dev_16_0_fsb_ctlr;          /* 16.0 */
+        struct pci_dev *pci_dev_16_1_fsb_addr_map;      /* 16.1 */
+        struct pci_dev *pci_dev_16_2_fsb_err_regs;      /* 16.2 */
+        struct pci_dev *pci_dev_2x_0_fbd_branch[MAX_BRANCHES];  /* 21.0  and 22.0 */
+
+        u16 tolm;                               /* top of low memory */
+        u64 ambase;                             /* AMB BAR */
+
+        u32 mc_settings;                        /* Report several settings */
+        u32 mc_settings_a;
+
+        u16 mir[MAX_MIR];                       /* Memory Interleave Reg*/
+
+        u16 mtr[MAX_SLOTS][MAX_BRANCHES];       /* Memory Technlogy Reg */
+        u16 ambpresent[MAX_CHANNELS];           /* AMB present regs */
+
+        /* DIMM information matrix, allocating architecture maximums */
+        struct i7300_dimm_info dimm_info[MAX_SLOTS][MAX_CHANNELS];
+
+        /* Temporary buffer for use when preparing error messages */
+        char *tmp_prt_buffer;
+};
+
+/* FIXME: Why do we need to have this static? */
+static struct edac_pci_ctl_info *i7300_pci;
+
+/***************************************************
+ * i7300 Register definitions for memory enumeration
+ ***************************************************/
+
+/*
+ * Device 16,
+ * Function 0: System Address (not documented)
+ * Function 1: Memory Branch Map, Control, Errors Register
+ */
+
+        /* OFFSETS for Function 0 */
+#define AMBASE                  0x48 /* AMB Mem Mapped Reg Region Base */
+#define MAXCH                   0x56 /* Max Channel Number */
+#define MAXDIMMPERCH            0x57 /* Max DIMM PER Channel Number */
+
+        /* OFFSETS for Function 1 */
+#define MC_SETTINGS             0x40
+  #define IS_MIRRORED(mc)               ((mc) & (1 << 16))
+  #define IS_ECC_ENABLED(mc)            ((mc) & (1 << 5))
+  #define IS_RETRY_ENABLED(mc)          ((mc) & (1 << 31))
+  #define IS_SCRBALGO_ENHANCED(mc)      ((mc) & (1 << 8))
+
+#define MC_SETTINGS_A           0x58
+  #define IS_SINGLE_MODE(mca)           ((mca) & (1 << 14))
+
+#define TOLM                    0x6C
+
+#define MIR0                    0x80
+#define MIR1                    0x84
+#define MIR2                    0x88
+
+/*
+ * Note: Other Intel EDAC drivers use AMBPRESENT to identify if the available
+ * memory. From datasheet item 7.3.1 (FB-DIMM technology & organization), it
+ * seems that we cannot use this information directly for the same usage.
+ * Each memory slot may have up to 2 AMB interfaces, one for income and another
+ * for outcome interface to the next slot.
+ * For now, the driver just stores the AMB present registers, but rely only at
+ * the MTR info to detect memory.
+ * Datasheet is also not clear about how to map each AMBPRESENT registers to
+ * one of the 4 available channels.
+ */
+#define AMBPRESENT_0    0x64
+#define AMBPRESENT_1    0x66
+
+static const u16 mtr_regs[MAX_SLOTS] = {
+        0x80, 0x84, 0x88, 0x8c,
+        0x82, 0x86, 0x8a, 0x8e
+};
+
+/*
+ * Defines to extract the vaious fields from the
+ *      MTRx - Memory Technology Registers
+ */
+#define MTR_DIMMS_PRESENT(mtr)          ((mtr) & (1 << 8))
+#define MTR_DIMMS_ETHROTTLE(mtr)        ((mtr) & (1 << 7))
+#define MTR_DRAM_WIDTH(mtr)             (((mtr) & (1 << 6)) ? 8 : 4)
+#define MTR_DRAM_BANKS(mtr)             (((mtr) & (1 << 5)) ? 8 : 4)
+#define MTR_DIMM_RANKS(mtr)             (((mtr) & (1 << 4)) ? 1 : 0)
+#define MTR_DIMM_ROWS(mtr)              (((mtr) >> 2) & 0x3)
+#define MTR_DRAM_BANKS_ADDR_BITS        2
+#define MTR_DIMM_ROWS_ADDR_BITS(mtr)    (MTR_DIMM_ROWS(mtr) + 13)
+#define MTR_DIMM_COLS(mtr)              ((mtr) & 0x3)
+#define MTR_DIMM_COLS_ADDR_BITS(mtr)    (MTR_DIMM_COLS(mtr) + 10)
+
+#ifdef CONFIG_EDAC_DEBUG
+/* MTR NUMROW */
+static const char *numrow_toString[] = {
+        "8,192 - 13 rows",
+        "16,384 - 14 rows",
+        "32,768 - 15 rows",
+        "65,536 - 16 rows"
+};
+
+/* MTR NUMCOL */
+static const char *numcol_toString[] = {
+        "1,024 - 10 columns",
+        "2,048 - 11 columns",
+        "4,096 - 12 columns",
+        "reserved"
+};
+#endif
+
+/************************************************
+ * i7300 Register definitions for error detection
+ ************************************************/
+
+/*
+ * Device 16.1: FBD Error Registers
+ */
+#define FERR_FAT_FBD    0x98
+static const char *ferr_fat_fbd_name[] = {
+        [22] = "Non-Redundant Fast Reset Timeout",
+        [2]  = ">Tmid Thermal event with intelligent throttling disabled",
+        [1]  = "Memory or FBD configuration CRC read error",
+        [0]  = "Memory Write error on non-redundant retry or "
+               "FBD configuration Write error on retry",
+};
+#define GET_FBD_FAT_IDX(fbderr) (fbderr & (3 << 28))
+#define FERR_FAT_FBD_ERR_MASK ((1 << 0) | (1 << 1) | (1 << 2) | (1 << 3))
+
+#define FERR_NF_FBD     0xa0
+static const char *ferr_nf_fbd_name[] = {
+        [24] = "DIMM-Spare Copy Completed",
+        [23] = "DIMM-Spare Copy Initiated",
+        [22] = "Redundant Fast Reset Timeout",
+        [21] = "Memory Write error on redundant retry",
+        [18] = "SPD protocol Error",
+        [17] = "FBD Northbound parity error on FBD Sync Status",
+        [16] = "Correctable Patrol Data ECC",
+        [15] = "Correctable Resilver- or Spare-Copy Data ECC",
+        [14] = "Correctable Mirrored Demand Data ECC",
+        [13] = "Correctable Non-Mirrored Demand Data ECC",
+        [11] = "Memory or FBD configuration CRC read error",
+        [10] = "FBD Configuration Write error on first attempt",
+        [9]  = "Memory Write error on first attempt",
+        [8]  = "Non-Aliased Uncorrectable Patrol Data ECC",
+        [7]  = "Non-Aliased Uncorrectable Resilver- or Spare-Copy Data ECC",
+        [6]  = "Non-Aliased Uncorrectable Mirrored Demand Data ECC",
+        [5]  = "Non-Aliased Uncorrectable Non-Mirrored Demand Data ECC",
+        [4]  = "Aliased Uncorrectable Patrol Data ECC",
+        [3]  = "Aliased Uncorrectable Resilver- or Spare-Copy Data ECC",
+        [2]  = "Aliased Uncorrectable Mirrored Demand Data ECC",
+        [1]  = "Aliased Uncorrectable Non-Mirrored Demand Data ECC",
+        [0]  = "Uncorrectable Data ECC on Replay",
+};
+#define GET_FBD_NF_IDX(fbderr)  (fbderr & (3 << 28))
+#define FERR_NF_FBD_ERR_MASK ((1 << 24) | (1 << 23) | (1 << 22) | (1 << 21) |\
+                              (1 << 18) | (1 << 17) | (1 << 16) | (1 << 15) |\
+                              (1 << 14) | (1 << 13) | (1 << 11) | (1 << 10) |\
+                              (1 << 9)  | (1 << 8)  | (1 << 7)  | (1 << 6)  |\
+                              (1 << 5)  | (1 << 4)  | (1 << 3)  | (1 << 2)  |\
+                              (1 << 1)  | (1 << 0))
+
+#define EMASK_FBD       0xa8
+#define EMASK_FBD_ERR_MASK ((1 << 27) | (1 << 26) | (1 << 25) | (1 << 24) |\
+                            (1 << 22) | (1 << 21) | (1 << 20) | (1 << 19) |\
+                            (1 << 18) | (1 << 17) | (1 << 16) | (1 << 14) |\
+                            (1 << 13) | (1 << 12) | (1 << 11) | (1 << 10) |\
+                            (1 << 9)  | (1 << 8)  | (1 << 7)  | (1 << 6)  |\
+                            (1 << 5)  | (1 << 4)  | (1 << 3)  | (1 << 2)  |\
+                            (1 << 1)  | (1 << 0))
+
+/*
+ * Device 16.2: Global Error Registers
+ */
+
+#define FERR_GLOBAL_HI  0x48
+static const char *ferr_global_hi_name[] = {
+        [3] = "FSB 3 Fatal Error",
+        [2] = "FSB 2 Fatal Error",
+        [1] = "FSB 1 Fatal Error",
+        [0] = "FSB 0 Fatal Error",
+};
+#define ferr_global_hi_is_fatal(errno)  1
+
+#define FERR_GLOBAL_LO  0x40
+static const char *ferr_global_lo_name[] = {
+        [31] = "Internal MCH Fatal Error",
+        [30] = "Intel QuickData Technology Device Fatal Error",
+        [29] = "FSB1 Fatal Error",
+        [28] = "FSB0 Fatal Error",
+        [27] = "FBD Channel 3 Fatal Error",
+        [26] = "FBD Channel 2 Fatal Error",
+        [25] = "FBD Channel 1 Fatal Error",
+        [24] = "FBD Channel 0 Fatal Error",
+        [23] = "PCI Express Device 7Fatal Error",
+        [22] = "PCI Express Device 6 Fatal Error",
+        [21] = "PCI Express Device 5 Fatal Error",
+        [20] = "PCI Express Device 4 Fatal Error",
+        [19] = "PCI Express Device 3 Fatal Error",
+        [18] = "PCI Express Device 2 Fatal Error",
+        [17] = "PCI Express Device 1 Fatal Error",
+        [16] = "ESI Fatal Error",
+        [15] = "Internal MCH Non-Fatal Error",
+        [14] = "Intel QuickData Technology Device Non Fatal Error",
+        [13] = "FSB1 Non-Fatal Error",
+        [12] = "FSB 0 Non-Fatal Error",
+        [11] = "FBD Channel 3 Non-Fatal Error",
+        [10] = "FBD Channel 2 Non-Fatal Error",
+        [9]  = "FBD Channel 1 Non-Fatal Error",
+        [8]  = "FBD Channel 0 Non-Fatal Error",
+        [7]  = "PCI Express Device 7 Non-Fatal Error",
+        [6]  = "PCI Express Device 6 Non-Fatal Error",
+        [5]  = "PCI Express Device 5 Non-Fatal Error",
+        [4]  = "PCI Express Device 4 Non-Fatal Error",
+        [3]  = "PCI Express Device 3 Non-Fatal Error",
+        [2]  = "PCI Express Device 2 Non-Fatal Error",
+        [1]  = "PCI Express Device 1 Non-Fatal Error",
+        [0]  = "ESI Non-Fatal Error",
+};
+#define ferr_global_lo_is_fatal(errno)  ((errno < 16) ? 0 : 1)
+
+#define NRECMEMA        0xbe
+  #define NRECMEMA_BANK(v)      (((v) >> 12) & 7)
+  #define NRECMEMA_RANK(v)      (((v) >> 8) & 15)
+
+#define NRECMEMB        0xc0
+  #define NRECMEMB_IS_WR(v)     ((v) & (1 << 31))
+  #define NRECMEMB_CAS(v)       (((v) >> 16) & 0x1fff)
+  #define NRECMEMB_RAS(v)       ((v) & 0xffff)
+
+#define REDMEMA         0xdc
+
+#define REDMEMB         0x7c
+  #define IS_SECOND_CH(v)       ((v) * (1 << 17))
+
+#define RECMEMA         0xe0
+  #define RECMEMA_BANK(v)       (((v) >> 12) & 7)
+  #define RECMEMA_RANK(v)       (((v) >> 8) & 15)
+
+#define RECMEMB         0xe4
+  #define RECMEMB_IS_WR(v)      ((v) & (1 << 31))
+  #define RECMEMB_CAS(v)        (((v) >> 16) & 0x1fff)
+  #define RECMEMB_RAS(v)        ((v) & 0xffff)
+
+/********************************************
+ * i7300 Functions related to error detection
+ ********************************************/
+
+/**
+ * get_err_from_table() - Gets the error message from a table
+ * @table:      table name (array of char *)
+ * @size:       number of elements at the table
+ * @pos:        position of the element to be returned
+ *
+ * This is a small routine that gets the pos-th element of a table. If the
+ * element doesn't exist (or it is empty), it returns "reserved".
+ * Instead of calling it directly, the better is to call via the macro
+ * GET_ERR_FROM_TABLE(), that automatically checks the table size via
+ * ARRAY_SIZE() macro
+ */
+static const char *get_err_from_table(const char *table[], int size, int pos)
+{
+        if (unlikely(pos >= size))
+                return "Reserved";
+
+        if (unlikely(!table[pos]))
+                return "Reserved";
+
+        return table[pos];
+}
+
+#define GET_ERR_FROM_TABLE(table, pos)                          \
+        get_err_from_table(table, ARRAY_SIZE(table), pos)
+
+/**
+ * i7300_process_error_global() - Retrieve the hardware error information from
+ *                                the hardware global error registers and
+ *                                sends it to dmesg
+ * @mci: struct mem_ctl_info pointer
+ */
+static void i7300_process_error_global(struct mem_ctl_info *mci)
+{
+        struct i7300_pvt *pvt;
+        u32 errnum, value;
+        unsigned long errors;
+        const char *specific;
+        bool is_fatal;
+
+        pvt = mci->pvt_info;
+
+        /* read in the 1st FATAL error register */
+        pci_read_config_dword(pvt->pci_dev_16_2_fsb_err_regs,
+                              FERR_GLOBAL_HI, &value);
+        if (unlikely(value)) {
+                errors = value;
+                errnum = find_first_bit(&errors,
+                                        ARRAY_SIZE(ferr_global_hi_name));
+                specific = GET_ERR_FROM_TABLE(ferr_global_hi_name, errnum);
+                is_fatal = ferr_global_hi_is_fatal(errnum);
+
+                /* Clear the error bit */
+                pci_write_config_dword(pvt->pci_dev_16_2_fsb_err_regs,
+                                       FERR_GLOBAL_HI, value);
+
+                goto error_global;
+        }
+
+        pci_read_config_dword(pvt->pci_dev_16_2_fsb_err_regs,
+                              FERR_GLOBAL_LO, &value);
+        if (unlikely(value)) {
+                errors = value;
+                errnum = find_first_bit(&errors,
+                                        ARRAY_SIZE(ferr_global_lo_name));
+                specific = GET_ERR_FROM_TABLE(ferr_global_lo_name, errnum);
+                is_fatal = ferr_global_lo_is_fatal(errnum);
+
+                /* Clear the error bit */
+                pci_write_config_dword(pvt->pci_dev_16_2_fsb_err_regs,
+                                       FERR_GLOBAL_LO, value);
+
+                goto error_global;
+        }
+        return;
+
+error_global:
+        i7300_mc_printk(mci, KERN_EMERG, "%s misc error: %s\n",
+                        is_fatal ? "Fatal" : "NOT fatal", specific);
+}
+
+/**
+ * i7300_process_fbd_error() - Retrieve the hardware error information from
+ *                             the FBD error registers and sends it via
+ *                             EDAC error API calls
+ * @mci: struct mem_ctl_info pointer
+ */
+static void i7300_process_fbd_error(struct mem_ctl_info *mci)
+{
+        struct i7300_pvt *pvt;
+        u32 errnum, value;
+        u16 val16;
+        unsigned branch, channel, bank, rank, cas, ras;
+        u32 syndrome;
+
+        unsigned long errors;
+        const char *specific;
+        bool is_wr;
+
+        pvt = mci->pvt_info;
+
+        /* read in the 1st FATAL error register */
+        pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
+                              FERR_FAT_FBD, &value);
+        if (unlikely(value & FERR_FAT_FBD_ERR_MASK)) {
+                errors = value & FERR_FAT_FBD_ERR_MASK ;
+                errnum = find_first_bit(&errors,
+                                        ARRAY_SIZE(ferr_fat_fbd_name));
+                specific = GET_ERR_FROM_TABLE(ferr_fat_fbd_name, errnum);
+
+                branch = (GET_FBD_FAT_IDX(value) == 2) ? 1 : 0;
+                pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map,
+                                     NRECMEMA, &val16);
+                bank = NRECMEMA_BANK(val16);
+                rank = NRECMEMA_RANK(val16);
+
+                pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
+                                NRECMEMB, &value);
+
+                is_wr = NRECMEMB_IS_WR(value);
+                cas = NRECMEMB_CAS(value);
+                ras = NRECMEMB_RAS(value);
+
+                snprintf(pvt->tmp_prt_buffer, PAGE_SIZE,
+                        "FATAL (Branch=%d DRAM-Bank=%d %s "
+                        "RAS=%d CAS=%d Err=0x%lx (%s))",
+                        branch, bank,
+                        is_wr ? "RDWR" : "RD",
+                        ras, cas,
+                        errors, specific);
+
+                /* Call the helper to output message */
+                edac_mc_handle_fbd_ue(mci, rank, branch << 1,
+                                      (branch << 1) + 1,
+                                      pvt->tmp_prt_buffer);
+        }
+
+        /* read in the 1st NON-FATAL error register */
+        pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
+                              FERR_NF_FBD, &value);
+        if (unlikely(value & FERR_NF_FBD_ERR_MASK)) {
+                errors = value & FERR_NF_FBD_ERR_MASK;
+                errnum = find_first_bit(&errors,
+                                        ARRAY_SIZE(ferr_nf_fbd_name));
+                specific = GET_ERR_FROM_TABLE(ferr_nf_fbd_name, errnum);
+
+                /* Clear the error bit */
+                pci_write_config_dword(pvt->pci_dev_16_2_fsb_err_regs,
+                                       FERR_GLOBAL_LO, value);
+
+                pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
+                        REDMEMA, &syndrome);
+
+                branch = (GET_FBD_FAT_IDX(value) == 2) ? 1 : 0;
+                pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map,
+                                     RECMEMA, &val16);
+                bank = RECMEMA_BANK(val16);
+                rank = RECMEMA_RANK(val16);
+
+                pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
+                                RECMEMB, &value);
+
+                is_wr = RECMEMB_IS_WR(value);
+                cas = RECMEMB_CAS(value);
+                ras = RECMEMB_RAS(value);
+
+                pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
+                                     REDMEMB, &value);
+
+                channel = (branch << 1);
+                if (IS_SECOND_CH(value))
+                        channel++;
+
+                /* Form out message */
+                snprintf(pvt->tmp_prt_buffer, PAGE_SIZE,
+                        "Corrected error (Branch=%d, Channel %d), "
+                        " DRAM-Bank=%d %s "
+                        "RAS=%d CAS=%d, CE Err=0x%lx, Syndrome=0x%08x(%s))",
+                        branch, channel,
+                        bank,
+                        is_wr ? "RDWR" : "RD",
+                        ras, cas,
+                        errors, syndrome, specific);
+
+                /*
+                 * Call the helper to output message
+                 * NOTE: Errors are reported per-branch, and not per-channel
+                 *       Currently, we don't know how to identify the right
+                 *       channel.
+                 */
+                edac_mc_handle_fbd_ce(mci, rank, channel,
+                                      pvt->tmp_prt_buffer);
+        }
+        return;
+}
+
+/**
+ * i7300_check_error() - Calls the error checking subroutines
+ * @mci: struct mem_ctl_info pointer
+ */
+static void i7300_check_error(struct mem_ctl_info *mci)
+{
+        i7300_process_error_global(mci);
+        i7300_process_fbd_error(mci);
+};
+
+/**
+ * i7300_clear_error() - Clears the error registers
+ * @mci: struct mem_ctl_info pointer
+ */
+static void i7300_clear_error(struct mem_ctl_info *mci)
+{
+        struct i7300_pvt *pvt = mci->pvt_info;
+        u32 value;
+        /*
+         * All error values are RWC - we need to read and write 1 to the
+         * bit that we want to cleanup
+         */
+
+        /* Clear global error registers */
+        pci_read_config_dword(pvt->pci_dev_16_2_fsb_err_regs,
+                              FERR_GLOBAL_HI, &value);
+        pci_write_config_dword(pvt->pci_dev_16_2_fsb_err_regs,
+                              FERR_GLOBAL_HI, value);
+
+        pci_read_config_dword(pvt->pci_dev_16_2_fsb_err_regs,
+                              FERR_GLOBAL_LO, &value);
+        pci_write_config_dword(pvt->pci_dev_16_2_fsb_err_regs,
+                              FERR_GLOBAL_LO, value);
+
+        /* Clear FBD error registers */
+        pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
+                              FERR_FAT_FBD, &value);
+        pci_write_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
+                              FERR_FAT_FBD, value);
+
+        pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
+                              FERR_NF_FBD, &value);
+        pci_write_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
+                              FERR_NF_FBD, value);
+}
+
+/**
+ * i7300_enable_error_reporting() - Enable the memory reporting logic at the
+ *                                  hardware
+ * @mci: struct mem_ctl_info pointer
+ */
+static void i7300_enable_error_reporting(struct mem_ctl_info *mci)
+{
+        struct i7300_pvt *pvt = mci->pvt_info;
+        u32 fbd_error_mask;
+
+        /* Read the FBD Error Mask Register */
+        pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
+                              EMASK_FBD, &fbd_error_mask);
+
+        /* Enable with a '0' */
+        fbd_error_mask &= ~(EMASK_FBD_ERR_MASK);
+
+        pci_write_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
+                               EMASK_FBD, fbd_error_mask);
+}
+
+/************************************************
+ * i7300 Functions related to memory enumberation
+ ************************************************/
+
+/**
+ * decode_mtr() - Decodes the MTR descriptor, filling the edac structs
+ * @pvt: pointer to the private data struct used by i7300 driver
+ * @slot: DIMM slot (0 to 7)
+ * @ch: Channel number within the branch (0 or 1)
+ * @branch: Branch number (0 or 1)
+ * @dinfo: Pointer to DIMM info where dimm size is stored
+ * @p_csrow: Pointer to the struct csrow_info that corresponds to that element
+ */
+static int decode_mtr(struct i7300_pvt *pvt,
+                      int slot, int ch, int branch,
+                      struct i7300_dimm_info *dinfo,
+                      struct csrow_info *p_csrow,
+                      u32 *nr_pages)
+{
+        int mtr, ans, addrBits, channel;
+
+        channel = to_channel(ch, branch);
+
+        mtr = pvt->mtr[slot][branch];
+        ans = MTR_DIMMS_PRESENT(mtr) ? 1 : 0;
+
+        debugf2("\tMTR%d CH%d: DIMMs are %s (mtr)\n",
+                slot, channel,
+                ans ? "Present" : "NOT Present");
+
+        /* Determine if there is a DIMM present in this DIMM slot */
+        if (!ans)
+                return 0;
+
+        /* Start with the number of bits for a Bank
+        * on the DRAM */
+        addrBits = MTR_DRAM_BANKS_ADDR_BITS;
+        /* Add thenumber of ROW bits */
+        addrBits += MTR_DIMM_ROWS_ADDR_BITS(mtr);
+        /* add the number of COLUMN bits */
+        addrBits += MTR_DIMM_COLS_ADDR_BITS(mtr);
+        /* add the number of RANK bits */
+        addrBits += MTR_DIMM_RANKS(mtr);
+
+        addrBits += 6;  /* add 64 bits per DIMM */
+        addrBits -= 20; /* divide by 2^^20 */
+        addrBits -= 3;  /* 8 bits per bytes */
+
+        dinfo->megabytes = 1 << addrBits;
+        *nr_pages = dinfo->megabytes << 8;
+
+        debugf2("\t\tWIDTH: x%d\n", MTR_DRAM_WIDTH(mtr));
+
+        debugf2("\t\tELECTRICAL THROTTLING is %s\n",
+                MTR_DIMMS_ETHROTTLE(mtr) ? "enabled" : "disabled");
+
+        debugf2("\t\tNUMBANK: %d bank(s)\n", MTR_DRAM_BANKS(mtr));
+        debugf2("\t\tNUMRANK: %s\n", MTR_DIMM_RANKS(mtr) ? "double" : "single");
+        debugf2("\t\tNUMROW: %s\n", numrow_toString[MTR_DIMM_ROWS(mtr)]);
+        debugf2("\t\tNUMCOL: %s\n", numcol_toString[MTR_DIMM_COLS(mtr)]);
+        debugf2("\t\tSIZE: %d MB\n", dinfo->megabytes);
+
+        p_csrow->grain = 8;
+        p_csrow->mtype = MEM_FB_DDR2;
+        p_csrow->csrow_idx = slot;
+        p_csrow->page_mask = 0;
+
+        /*
+         * The type of error detection actually depends of the
+         * mode of operation. When it is just one single memory chip, at
+         * socket 0, channel 0, it uses 8-byte-over-32-byte SECDED+ code.
+         * In normal or mirrored mode, it uses Lockstep mode,
+         * with the possibility of using an extended algorithm for x8 memories
+         * See datasheet Sections 7.3.6 to 7.3.8
+         */
+
+        if (IS_SINGLE_MODE(pvt->mc_settings_a)) {
+                p_csrow->edac_mode = EDAC_SECDED;
+                debugf2("\t\tECC code is 8-byte-over-32-byte SECDED+ code\n");
+        } else {
+                debugf2("\t\tECC code is on Lockstep mode\n");
+                if (MTR_DRAM_WIDTH(mtr) == 8)
+                        p_csrow->edac_mode = EDAC_S8ECD8ED;
+                else
+                        p_csrow->edac_mode = EDAC_S4ECD4ED;
+        }
+
+        /* ask what device type on this row */
+        if (MTR_DRAM_WIDTH(mtr) == 8) {
+                debugf2("\t\tScrub algorithm for x8 is on %s mode\n",
+                        IS_SCRBALGO_ENHANCED(pvt->mc_settings) ?
+                                            "enhanced" : "normal");
+
+                p_csrow->dtype = DEV_X8;
+        } else
+                p_csrow->dtype = DEV_X4;
+
+        return mtr;
+}
+
+/**
+ * print_dimm_size() - Prints dump of the memory organization
+ * @pvt: pointer to the private data struct used by i7300 driver
+ *
+ * Useful for debug. If debug is disabled, this routine do nothing
+ */
+static void print_dimm_size(struct i7300_pvt *pvt)
+{
+#ifdef CONFIG_EDAC_DEBUG
+        struct i7300_dimm_info *dinfo;
+        char *p;
+        int space, n;
+        int channel, slot;
+
+        space = PAGE_SIZE;
+        p = pvt->tmp_prt_buffer;
+
+        n = snprintf(p, space, "              ");
+        p += n;
+        space -= n;
+        for (channel = 0; channel < MAX_CHANNELS; channel++) {
+                n = snprintf(p, space, "channel %d | ", channel);
+                p += n;
+                space -= n;
+        }
+        debugf2("%s\n", pvt->tmp_prt_buffer);
+        p = pvt->tmp_prt_buffer;
+        space = PAGE_SIZE;
+        n = snprintf(p, space, "-------------------------------"
+                               "------------------------------");
+        p += n;
+        space -= n;
+        debugf2("%s\n", pvt->tmp_prt_buffer);
+        p = pvt->tmp_prt_buffer;
+        space = PAGE_SIZE;
+
+        for (slot = 0; slot < MAX_SLOTS; slot++) {
+                n = snprintf(p, space, "csrow/SLOT %d  ", slot);
+                p += n;
+                space -= n;
+
+                for (channel = 0; channel < MAX_CHANNELS; channel++) {
+                        dinfo = &pvt->dimm_info[slot][channel];
+                        n = snprintf(p, space, "%4d MB   | ", dinfo->megabytes);
+                        p += n;
+                        space -= n;
+                }
+
+                debugf2("%s\n", pvt->tmp_prt_buffer);
+                p = pvt->tmp_prt_buffer;
+                space = PAGE_SIZE;
+        }
+
+        n = snprintf(p, space, "-------------------------------"
+                               "------------------------------");
+        p += n;
+        space -= n;
+        debugf2("%s\n", pvt->tmp_prt_buffer);
+        p = pvt->tmp_prt_buffer;
+        space = PAGE_SIZE;
+#endif
+}
+
+/**
+ * i7300_init_csrows() - Initialize the 'csrows' table within
+ *                       the mci control structure with the
+ *                       addressing of memory.
+ * @mci: struct mem_ctl_info pointer
+ */
+static int i7300_init_csrows(struct mem_ctl_info *mci)
+{
+        struct i7300_pvt *pvt;
+        struct i7300_dimm_info *dinfo;
+        struct csrow_info *p_csrow;
+        int rc = -ENODEV;
+        int mtr;
+        int ch, branch, slot, channel;
+        u32 last_page = 0, nr_pages;
+
+        pvt = mci->pvt_info;
+
+        debugf2("Memory Technology Registers:\n");
+
+        /* Get the AMB present registers for the four channels */
+        for (branch = 0; branch < MAX_BRANCHES; branch++) {
+                /* Read and dump branch 0's MTRs */
+                channel = to_channel(0, branch);
+                pci_read_config_word(pvt->pci_dev_2x_0_fbd_branch[branch],
+                                     AMBPRESENT_0,
+                                &pvt->ambpresent[channel]);
+                debugf2("\t\tAMB-present CH%d = 0x%x:\n",
+                        channel, pvt->ambpresent[channel]);
+
+                channel = to_channel(1, branch);
+                pci_read_config_word(pvt->pci_dev_2x_0_fbd_branch[branch],
+                                     AMBPRESENT_1,
+                                &pvt->ambpresent[channel]);
+                debugf2("\t\tAMB-present CH%d = 0x%x:\n",
+                        channel, pvt->ambpresent[channel]);
+        }
+
+        /* Get the set of MTR[0-7] regs by each branch */
+        for (slot = 0; slot < MAX_SLOTS; slot++) {
+                int where = mtr_regs[slot];
+                for (branch = 0; branch < MAX_BRANCHES; branch++) {
+                        pci_read_config_word(pvt->pci_dev_2x_0_fbd_branch[branch],
+                                        where,
+                                        &pvt->mtr[slot][branch]);
+                        for (ch = 0; ch < MAX_BRANCHES; ch++) {
+                                int channel = to_channel(ch, branch);
+
+                                dinfo = &pvt->dimm_info[slot][channel];
+                                p_csrow = &mci->csrows[slot];
+
+                                mtr = decode_mtr(pvt, slot, ch, branch,
+                                                 dinfo, p_csrow, &nr_pages);
+                                /* if no DIMMS on this row, continue */
+                                if (!MTR_DIMMS_PRESENT(mtr))
+                                        continue;
+
+                                /* Update per_csrow memory count */
+                                p_csrow->nr_pages += nr_pages;
+                                p_csrow->first_page = last_page;
+                                last_page += nr_pages;
+                                p_csrow->last_page = last_page;
+
+                                rc = 0;
+                        }
+                }
+        }
+
+        return rc;
+}
+
+/**
+ * decode_mir() - Decodes Memory Interleave Register (MIR) info
+ * @int mir_no: number of the MIR register to decode
+ * @mir: array with the MIR data cached on the driver
+ */
+static void decode_mir(int mir_no, u16 mir[MAX_MIR])
+{
+        if (mir[mir_no] & 3)
+                debugf2("MIR%d: limit= 0x%x Branch(es) that participate:"
+                        " %s %s\n",
+                        mir_no,
+                        (mir[mir_no] >> 4) & 0xfff,
+                        (mir[mir_no] & 1) ? "B0" : "",
+                        (mir[mir_no] & 2) ? "B1" : "");
+}
+
+/**
+ * i7300_get_mc_regs() - Get the contents of the MC enumeration registers
+ * @mci: struct mem_ctl_info pointer
+ *
+ * Data read is cached internally for its usage when needed
+ */
+static int i7300_get_mc_regs(struct mem_ctl_info *mci)
+{
+        struct i7300_pvt *pvt;
+        u32 actual_tolm;
+        int i, rc;
+
+        pvt = mci->pvt_info;
+
+        pci_read_config_dword(pvt->pci_dev_16_0_fsb_ctlr, AMBASE,
+                        (u32 *) &pvt->ambase);
+
+        debugf2("AMBASE= 0x%lx\n", (long unsigned int)pvt->ambase);
+
+        /* Get the Branch Map regs */
+        pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map, TOLM, &pvt->tolm);
+        pvt->tolm >>= 12;
+        debugf2("TOLM (number of 256M regions) =%u (0x%x)\n", pvt->tolm,
+                pvt->tolm);
+
+        actual_tolm = (u32) ((1000l * pvt->tolm) >> (30 - 28));
+        debugf2("Actual TOLM byte addr=%u.%03u GB (0x%x)\n",
+                actual_tolm/1000, actual_tolm % 1000, pvt->tolm << 28);
+
+        /* Get memory controller settings */
+        pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, MC_SETTINGS,
+                             &pvt->mc_settings);
+        pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, MC_SETTINGS_A,
+                             &pvt->mc_settings_a);
+
+        if (IS_SINGLE_MODE(pvt->mc_settings_a))
+                debugf0("Memory controller operating on single mode\n");
+        else
+                debugf0("Memory controller operating on %s mode\n",
+                IS_MIRRORED(pvt->mc_settings) ? "mirrored" : "non-mirrored");
+
+        debugf0("Error detection is %s\n",
+                IS_ECC_ENABLED(pvt->mc_settings) ? "enabled" : "disabled");
+        debugf0("Retry is %s\n",
+                IS_RETRY_ENABLED(pvt->mc_settings) ? "enabled" : "disabled");
+
+        /* Get Memory Interleave Range registers */
+        pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map, MIR0,
+                             &pvt->mir[0]);
+        pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map, MIR1,
+                             &pvt->mir[1]);
+        pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map, MIR2,
+                             &pvt->mir[2]);
+
+        /* Decode the MIR regs */
+        for (i = 0; i < MAX_MIR; i++)
+                decode_mir(i, pvt->mir);
+
+        rc = i7300_init_csrows(mci);
+        if (rc < 0)
+                return rc;
+
+        /* Go and determine the size of each DIMM and place in an
+         * orderly matrix */
+        print_dimm_size(pvt);
+
+        return 0;
+}
+
+/*************************************************
+ * i7300 Functions related to device probe/release
+ *************************************************/
+
+/**
+ * i7300_put_devices() - Release the PCI devices
+ * @mci: struct mem_ctl_info pointer
+ */
+static void i7300_put_devices(struct mem_ctl_info *mci)
+{
+        struct i7300_pvt *pvt;
+        int branch;
+
+        pvt = mci->pvt_info;
+
+        /* Decrement usage count for devices */
+        for (branch = 0; branch < MAX_CH_PER_BRANCH; branch++)
+                pci_dev_put(pvt->pci_dev_2x_0_fbd_branch[branch]);
+        pci_dev_put(pvt->pci_dev_16_2_fsb_err_regs);
+        pci_dev_put(pvt->pci_dev_16_1_fsb_addr_map);
+}
+
+/**
+ * i7300_get_devices() - Find and perform 'get' operation on the MCH's
+ *                       device/functions we want to reference for this driver
+ * @mci: struct mem_ctl_info pointer
+ *
+ * Access and prepare the several devices for usage:
+ * I7300 devices used by this driver:
+ *    Device 16, functions 0,1 and 2:   PCI_DEVICE_ID_INTEL_I7300_MCH_ERR
+ *    Device 21 function 0:             PCI_DEVICE_ID_INTEL_I7300_MCH_FB0
+ *    Device 22 function 0:             PCI_DEVICE_ID_INTEL_I7300_MCH_FB1
+ */
+static int __devinit i7300_get_devices(struct mem_ctl_info *mci)
+{
+        struct i7300_pvt *pvt;
+        struct pci_dev *pdev;
+
+        pvt = mci->pvt_info;
+
+        /* Attempt to 'get' the MCH register we want */
+        pdev = NULL;
+        while (!pvt->pci_dev_16_1_fsb_addr_map ||
+               !pvt->pci_dev_16_2_fsb_err_regs) {
+                pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
+                                      PCI_DEVICE_ID_INTEL_I7300_MCH_ERR, pdev);
+                if (!pdev) {
+                        /* End of list, leave */
+                        i7300_printk(KERN_ERR,
+                                "'system address,Process Bus' "
+                                "device not found:"
+                                "vendor 0x%x device 0x%x ERR funcs "
+                                "(broken BIOS?)\n",
+                                PCI_VENDOR_ID_INTEL,
+                                PCI_DEVICE_ID_INTEL_I7300_MCH_ERR);
+                        goto error;
+                }
+
+                /* Store device 16 funcs 1 and 2 */
+                switch (PCI_FUNC(pdev->devfn)) {
+                case 1:
+                        pvt->pci_dev_16_1_fsb_addr_map = pdev;
+                        break;
+                case 2:
+                        pvt->pci_dev_16_2_fsb_err_regs = pdev;
+                        break;
+                }
+        }
+
+        debugf1("System Address, processor bus- PCI Bus ID: %s  %x:%x\n",
+                pci_name(pvt->pci_dev_16_0_fsb_ctlr),
+                pvt->pci_dev_16_0_fsb_ctlr->vendor,
+                pvt->pci_dev_16_0_fsb_ctlr->device);
+        debugf1("Branchmap, control and errors - PCI Bus ID: %s  %x:%x\n",
+                pci_name(pvt->pci_dev_16_1_fsb_addr_map),
+                pvt->pci_dev_16_1_fsb_addr_map->vendor,
+                pvt->pci_dev_16_1_fsb_addr_map->device);
+        debugf1("FSB Error Regs - PCI Bus ID: %s  %x:%x\n",
+                pci_name(pvt->pci_dev_16_2_fsb_err_regs),
+                pvt->pci_dev_16_2_fsb_err_regs->vendor,
+                pvt->pci_dev_16_2_fsb_err_regs->device);
+
+        pvt->pci_dev_2x_0_fbd_branch[0] = pci_get_device(PCI_VENDOR_ID_INTEL,
+                                            PCI_DEVICE_ID_INTEL_I7300_MCH_FB0,
+                                            NULL);
+        if (!pvt->pci_dev_2x_0_fbd_branch[0]) {
+                i7300_printk(KERN_ERR,
+                        "MC: 'BRANCH 0' device not found:"
+                        "vendor 0x%x device 0x%x Func 0 (broken BIOS?)\n",
+                        PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I7300_MCH_FB0);
+                goto error;
+        }
+
+        pvt->pci_dev_2x_0_fbd_branch[1] = pci_get_device(PCI_VENDOR_ID_INTEL,
+                                            PCI_DEVICE_ID_INTEL_I7300_MCH_FB1,
+                                            NULL);
+        if (!pvt->pci_dev_2x_0_fbd_branch[1]) {
+                i7300_printk(KERN_ERR,
+                        "MC: 'BRANCH 1' device not found:"
+                        "vendor 0x%x device 0x%x Func 0 "
+                        "(broken BIOS?)\n",
+                        PCI_VENDOR_ID_INTEL,
+                        PCI_DEVICE_ID_INTEL_I7300_MCH_FB1);
+                goto error;
+        }
+
+        return 0;
+
+error:
+        i7300_put_devices(mci);
+        return -ENODEV;
+}
+
+/**
+ * i7300_init_one() - Probe for one instance of the device
+ * @pdev: struct pci_dev pointer
+ * @id: struct pci_device_id pointer - currently unused
+ */
+static int __devinit i7300_init_one(struct pci_dev *pdev,
+                                    const struct pci_device_id *id)
+{
+        struct mem_ctl_info *mci;
+        struct i7300_pvt *pvt;
+        int num_channels;
+        int num_dimms_per_channel;
+        int num_csrows;
+        int rc;
+
+        /* wake up device */
+        rc = pci_enable_device(pdev);
+        if (rc == -EIO)
+                return rc;
+
+        debugf0("MC: " __FILE__ ": %s(), pdev bus %u dev=0x%x fn=0x%x\n",
+                __func__,
+                pdev->bus->number,
+                PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
+
+        /* We only are looking for func 0 of the set */
+        if (PCI_FUNC(pdev->devfn) != 0)
+                return -ENODEV;
+
+        /* As we don't have a motherboard identification routine to determine
+         * actual number of slots/dimms per channel, we thus utilize the
+         * resource as specified by the chipset. Thus, we might have
+         * have more DIMMs per channel than actually on the mobo, but this
+         * allows the driver to support up to the chipset max, without
+         * some fancy mobo determination.
+         */
+        num_dimms_per_channel = MAX_SLOTS;
+        num_channels = MAX_CHANNELS;
+        num_csrows = MAX_SLOTS * MAX_CHANNELS;
+
+        debugf0("MC: %s(): Number of - Channels= %d  DIMMS= %d  CSROWS= %d\n",
+                __func__, num_channels, num_dimms_per_channel, num_csrows);
+
+        /* allocate a new MC control structure */
+        mci = edac_mc_alloc(sizeof(*pvt), num_csrows, num_channels, 0);
+
+        if (mci == NULL)
+                return -ENOMEM;
+
+        debugf0("MC: " __FILE__ ": %s(): mci = %p\n", __func__, mci);
+
+        mci->dev = &pdev->dev;  /* record ptr  to the generic device */
+
+        pvt = mci->pvt_info;
+        pvt->pci_dev_16_0_fsb_ctlr = pdev;      /* Record this device in our private */
+
+        pvt->tmp_prt_buffer = kmalloc(PAGE_SIZE, GFP_KERNEL);
+        if (!pvt->tmp_prt_buffer) {
+                edac_mc_free(mci);
+                return -ENOMEM;
+        }
+
+        /* 'get' the pci devices we want to reserve for our use */
+        if (i7300_get_devices(mci))
+                goto fail0;
+
+        mci->mc_idx = 0;
+        mci->mtype_cap = MEM_FLAG_FB_DDR2;
+        mci->edac_ctl_cap = EDAC_FLAG_NONE;
+        mci->edac_cap = EDAC_FLAG_NONE;
+        mci->mod_name = "i7300_edac.c";
+        mci->mod_ver = I7300_REVISION;
+        mci->ctl_name = i7300_devs[0].ctl_name;
+        mci->dev_name = pci_name(pdev);
+        mci->ctl_page_to_phys = NULL;
+
+        /* Set the function pointer to an actual operation function */
+        mci->edac_check = i7300_check_error;
+
+        /* initialize the MC control structure 'csrows' table
+         * with the mapping and control information */
+        if (i7300_get_mc_regs(mci)) {
+                debugf0("MC: Setting mci->edac_cap to EDAC_FLAG_NONE\n"
+                        "    because i7300_init_csrows() returned nonzero "
+                        "value\n");
+                mci->edac_cap = EDAC_FLAG_NONE; /* no csrows found */
+        } else {
+                debugf1("MC: Enable error reporting now\n");
+                i7300_enable_error_reporting(mci);
+        }
+
+        /* add this new MC control structure to EDAC's list of MCs */
+        if (edac_mc_add_mc(mci)) {
+                debugf0("MC: " __FILE__
+                        ": %s(): failed edac_mc_add_mc()\n", __func__);
+                /* FIXME: perhaps some code should go here that disables error
+                 * reporting if we just enabled it
+                 */
+                goto fail1;
+        }
+
+        i7300_clear_error(mci);
+
+        /* allocating generic PCI control info */
+        i7300_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
+        if (!i7300_pci) {
+                printk(KERN_WARNING
+                        "%s(): Unable to create PCI control\n",
+                        __func__);
+                printk(KERN_WARNING
+                        "%s(): PCI error report via EDAC not setup\n",
+                        __func__);
+        }
+
+        return 0;
+
+        /* Error exit unwinding stack */
+fail1:
+
+        i7300_put_devices(mci);
+
+fail0:
+        kfree(pvt->tmp_prt_buffer);
+        edac_mc_free(mci);
+        return -ENODEV;
+}
+
+/**
+ * i7300_remove_one() - Remove the driver
+ * @pdev: struct pci_dev pointer
+ */
+static void __devexit i7300_remove_one(struct pci_dev *pdev)
+{
+        struct mem_ctl_info *mci;
+        char *tmp;
+
+        debugf0(__FILE__ ": %s()\n", __func__);
+
+        if (i7300_pci)
+                edac_pci_release_generic_ctl(i7300_pci);
+
+        mci = edac_mc_del_mc(&pdev->dev);
+        if (!mci)
+                return;
+
+        tmp = ((struct i7300_pvt *)mci->pvt_info)->tmp_prt_buffer;
+
+        /* retrieve references to resources, and free those resources */
+        i7300_put_devices(mci);
+
+        kfree(tmp);
+        edac_mc_free(mci);
+}
+
+/*
+ * pci_device_id: table for which devices we are looking for
+ *
+ * Has only 8086:360c PCI ID
+ */
+static const struct pci_device_id i7300_pci_tbl[] __devinitdata = {
+        {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I7300_MCH_ERR)},
+        {0,}                    /* 0 terminated list. */
+};
+
+MODULE_DEVICE_TABLE(pci, i7300_pci_tbl);
+
+/*
+ * i7300_driver: pci_driver structure for this module
+ */
+static struct pci_driver i7300_driver = {
+        .name = "i7300_edac",
+        .probe = i7300_init_one,
+        .remove = __devexit_p(i7300_remove_one),
+        .id_table = i7300_pci_tbl,
+};
+
+/**
+ * i7300_init() - Registers the driver
+ */
+static int __init i7300_init(void)
+{
+        int pci_rc;
+
+        debugf2("MC: " __FILE__ ": %s()\n", __func__);
+
+        /* Ensure that the OPSTATE is set correctly for POLL or NMI */
+        opstate_init();
+
+        pci_rc = pci_register_driver(&i7300_driver);
+
+        return (pci_rc < 0) ? pci_rc : 0;
+}
+
+/**
+ * i7300_init() - Unregisters the driver
+ */
+static void __exit i7300_exit(void)
+{
+        debugf2("MC: " __FILE__ ": %s()\n", __func__);
+        pci_unregister_driver(&i7300_driver);
+}
+
+module_init(i7300_init);
+module_exit(i7300_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>");
+MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)");
+MODULE_DESCRIPTION("MC Driver for Intel I7300 memory controllers - "
+                   I7300_REVISION);
+
+module_param(edac_op_state, int, 0444);
+MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
diff --git a/drivers/edac/i7core_edac.c b/drivers/edac/i7core_edac.c
index 0fd5b85a0f75..04f1e7ce02b1 100644
--- a/drivers/edac/i7core_edac.c
+++ b/drivers/edac/i7core_edac.c
@@ -1,6 +1,6 @@
 /* Intel i7 core/Nehalem Memory Controller kernel module
  *
- * This driver supports yhe memory controllers found on the Intel
+ * This driver supports the memory controllers found on the Intel
  * processor families i7core, i7core 7xx/8xx, i5core, Xeon 35xx,
  * Xeon 55xx and Xeon 56xx also known as Nehalem, Nehalem-EP, Lynnfield
  * and Westmere-EP.
@@ -39,6 +39,14 @@
 
 #include "edac_core.h"
 
+/* Static vars */
+static LIST_HEAD(i7core_edac_list);
+static DEFINE_MUTEX(i7core_edac_lock);
+static int probed;
+
+static int use_pci_fixup;
+module_param(use_pci_fixup, int, 0444);
+MODULE_PARM_DESC(use_pci_fixup, "Enable PCI fixup to seek for hidden devices");
 /*
  * This is used for Nehalem-EP and Nehalem-EX devices, where the non-core
  * registers start at bus 255, and are not reported by BIOS.
@@ -51,7 +59,7 @@
 /*
  * Alter this version for the module when modifications are made
  */
-#define I7CORE_REVISION    " Ver: 1.0.0 " __DATE__
+#define I7CORE_REVISION    " Ver: 1.0.0"
 #define EDAC_MOD_STR      "i7core_edac"
 
 /*
@@ -212,8 +220,8 @@ struct pci_id_descr {
 };
 
 struct pci_id_table {
-        struct pci_id_descr     *descr;
-        int                     n_devs;
+        const struct pci_id_descr       *descr;
+        int                             n_devs;
 };
 
 struct i7core_dev {
@@ -235,8 +243,6 @@ struct i7core_pvt {
         struct i7core_inject    inject;
         struct i7core_channel   channel[NUM_CHANS];
 
-        int             channels; /* Number of active channels */
-
         int             ce_count_available;
         int             csrow_map[NUM_CHANS][MAX_DIMMS];
 
@@ -261,22 +267,22 @@ struct i7core_pvt {
 
         /* Count indicator to show errors not got */
         unsigned                mce_overrun;
-};
 
-/* Static vars */
-static LIST_HEAD(i7core_edac_list);
-static DEFINE_MUTEX(i7core_edac_lock);
+        /* Struct to control EDAC polling */
+        struct edac_pci_ctl_info *i7core_pci;
+};
 
 #define PCI_DESCR(device, function, device_id)  \
         .dev = (device),                        \
         .func = (function),                     \
         .dev_id = (device_id)
 
-struct pci_id_descr pci_dev_descr_i7core_nehalem[] = {
+static const struct pci_id_descr pci_dev_descr_i7core_nehalem[] = {
                 /* Memory controller */
         { PCI_DESCR(3, 0, PCI_DEVICE_ID_INTEL_I7_MCR)     },
         { PCI_DESCR(3, 1, PCI_DEVICE_ID_INTEL_I7_MC_TAD)  },
-                        /* Exists only for RDIMM */
+
+                /* Exists only for RDIMM */
         { PCI_DESCR(3, 2, PCI_DEVICE_ID_INTEL_I7_MC_RAS), .optional = 1  },
         { PCI_DESCR(3, 4, PCI_DEVICE_ID_INTEL_I7_MC_TEST) },
 
@@ -297,19 +303,9 @@ struct pci_id_descr pci_dev_descr_i7core_nehalem[] = {
         { PCI_DESCR(6, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH2_ADDR) },
         { PCI_DESCR(6, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH2_RANK) },
         { PCI_DESCR(6, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH2_TC)   },
-
-                /* Generic Non-core registers */
-        /*
-         * This is the PCI device on i7core and on Xeon 35xx (8086:2c41)
-         * On Xeon 55xx, however, it has a different id (8086:2c40). So,
-         * the probing code needs to test for the other address in case of
-         * failure of this one
-         */
-        { PCI_DESCR(0, 0, PCI_DEVICE_ID_INTEL_I7_NONCORE)  },
-
 };
 
-struct pci_id_descr pci_dev_descr_lynnfield[] = {
+static const struct pci_id_descr pci_dev_descr_lynnfield[] = {
         { PCI_DESCR( 3, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MCR)         },
         { PCI_DESCR( 3, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TAD)      },
         { PCI_DESCR( 3, 4, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TEST)     },
@@ -323,15 +319,9 @@ struct pci_id_descr pci_dev_descr_lynnfield[] = {
         { PCI_DESCR( 5, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_ADDR) },
         { PCI_DESCR( 5, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_RANK) },
         { PCI_DESCR( 5, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_TC)   },
-
-        /*
-         * This is the PCI device has an alternate address on some
-         * processors like Core i7 860
-         */
-        { PCI_DESCR( 0, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE)     },
 };
 
-struct pci_id_descr pci_dev_descr_i7core_westmere[] = {
+static const struct pci_id_descr pci_dev_descr_i7core_westmere[] = {
                 /* Memory controller */
         { PCI_DESCR(3, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MCR_REV2)     },
         { PCI_DESCR(3, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TAD_REV2)  },
@@ -356,17 +346,14 @@ struct pci_id_descr pci_dev_descr_i7core_westmere[] = {
         { PCI_DESCR(6, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_ADDR_REV2) },
         { PCI_DESCR(6, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_RANK_REV2) },
         { PCI_DESCR(6, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_TC_REV2)   },
-
-                /* Generic Non-core registers */
-        { PCI_DESCR(0, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE_REV2)  },
-
 };
 
-#define PCI_ID_TABLE_ENTRY(A) { A, ARRAY_SIZE(A) }
-struct pci_id_table pci_dev_table[] = {
+#define PCI_ID_TABLE_ENTRY(A) { .descr=A, .n_devs = ARRAY_SIZE(A) }
+static const struct pci_id_table pci_dev_table[] = {
         PCI_ID_TABLE_ENTRY(pci_dev_descr_i7core_nehalem),
         PCI_ID_TABLE_ENTRY(pci_dev_descr_lynnfield),
         PCI_ID_TABLE_ENTRY(pci_dev_descr_i7core_westmere),
+        {0,}                    /* 0 terminated list. */
 };
 
 /*
@@ -378,8 +365,6 @@ static const struct pci_device_id i7core_pci_tbl[] __devinitdata = {
         {0,}                    /* 0 terminated list. */
 };
 
-static struct edac_pci_ctl_info *i7core_pci;
-
 /****************************************************************************
                         Anciliary status routines
  ****************************************************************************/
@@ -442,6 +427,36 @@ static struct i7core_dev *get_i7core_dev(u8 socket)
         return NULL;
 }
 
+static struct i7core_dev *alloc_i7core_dev(u8 socket,
+                                           const struct pci_id_table *table)
+{
+        struct i7core_dev *i7core_dev;
+
+        i7core_dev = kzalloc(sizeof(*i7core_dev), GFP_KERNEL);
+        if (!i7core_dev)
+                return NULL;
+
+        i7core_dev->pdev = kzalloc(sizeof(*i7core_dev->pdev) * table->n_devs,
+                                   GFP_KERNEL);
+        if (!i7core_dev->pdev) {
+                kfree(i7core_dev);
+                return NULL;
+        }
+
+        i7core_dev->socket = socket;
+        i7core_dev->n_devs = table->n_devs;
+        list_add_tail(&i7core_dev->list, &i7core_edac_list);
+
+        return i7core_dev;
+}
+
+static void free_i7core_dev(struct i7core_dev *i7core_dev)
+{
+        list_del(&i7core_dev->list);
+        kfree(i7core_dev->pdev);
+        kfree(i7core_dev);
+}
+
 /****************************************************************************
                         Memory check routines
  ****************************************************************************/
@@ -484,7 +499,7 @@ static struct pci_dev *get_pdev_slot_func(u8 socket, unsigned slot,
  * to add a fake description for csrows.
  * So, this driver is attributing one DIMM memory for one csrow.
  */
-static int i7core_get_active_channels(u8 socket, unsigned *channels,
+static int i7core_get_active_channels(const u8 socket, unsigned *channels,
                                       unsigned *csrows)
 {
         struct pci_dev *pdev = NULL;
@@ -545,12 +560,13 @@ static int i7core_get_active_channels(u8 socket, unsigned *channels,
         return 0;
 }
 
-static int get_dimm_config(struct mem_ctl_info *mci, int *csrow)
+static int get_dimm_config(const struct mem_ctl_info *mci)
 {
         struct i7core_pvt *pvt = mci->pvt_info;
         struct csrow_info *csr;
         struct pci_dev *pdev;
         int i, j;
+        int csrow = 0;
         unsigned long last_page = 0;
         enum edac_type mode;
         enum mem_type mtype;
@@ -664,13 +680,9 @@ static int get_dimm_config(struct mem_ctl_info *mci, int *csrow)
                                 RANKOFFSET(dimm_dod[j]),
                                 banks, ranks, rows, cols);
 
-#if PAGE_SHIFT > 20
-                        npages = size >> (PAGE_SHIFT - 20);
-#else
-                        npages = size << (20 - PAGE_SHIFT);
-#endif
+                        npages = MiB_TO_PAGES(size);
 
-                        csr = &mci->csrows[*csrow];
+                        csr = &mci->csrows[csrow];
                         csr->first_page = last_page + 1;
                         last_page += npages;
                         csr->last_page = last_page;
@@ -678,13 +690,13 @@ static int get_dimm_config(struct mem_ctl_info *mci, int *csrow)
 
                         csr->page_mask = 0;
                         csr->grain = 8;
-                        csr->csrow_idx = *csrow;
+                        csr->csrow_idx = csrow;
                         csr->nr_channels = 1;
 
                         csr->channels[0].chan_idx = i;
                         csr->channels[0].ce_count = 0;
 
-                        pvt->csrow_map[i][j] = *csrow;
+                        pvt->csrow_map[i][j] = csrow;
 
                         switch (banks) {
                         case 4:
@@ -703,7 +715,7 @@ static int get_dimm_config(struct mem_ctl_info *mci, int *csrow)
                         csr->edac_mode = mode;
                         csr->mtype = mtype;
 
-                        (*csrow)++;
+                        csrow++;
                 }
 
                 pci_read_config_dword(pdev, MC_SAG_CH_0, &value[0]);
@@ -736,7 +748,7 @@ static int get_dimm_config(struct mem_ctl_info *mci, int *csrow)
    we're disabling error injection on all write calls to the sysfs nodes that
    controls the error code injection.
  */
-static int disable_inject(struct mem_ctl_info *mci)
+static int disable_inject(const struct mem_ctl_info *mci)
 {
         struct i7core_pvt *pvt = mci->pvt_info;
 
@@ -921,7 +933,7 @@ DECLARE_ADDR_MATCH(bank, 32);
 DECLARE_ADDR_MATCH(page, 0x10000);
 DECLARE_ADDR_MATCH(col, 0x4000);
 
-static int write_and_test(struct pci_dev *dev, int where, u32 val)
+static int write_and_test(struct pci_dev *dev, const int where, const u32 val)
 {
         u32 read;
         int count;
@@ -1120,35 +1132,34 @@ DECLARE_COUNTER(2);
  * Sysfs struct
  */
 
-
-static struct mcidev_sysfs_attribute i7core_addrmatch_attrs[] = {
+static const struct mcidev_sysfs_attribute i7core_addrmatch_attrs[] = {
         ATTR_ADDR_MATCH(channel),
         ATTR_ADDR_MATCH(dimm),
         ATTR_ADDR_MATCH(rank),
         ATTR_ADDR_MATCH(bank),
         ATTR_ADDR_MATCH(page),
         ATTR_ADDR_MATCH(col),
-        { .attr = { .name = NULL } }
+        { } /* End of list */
 };
 
-static struct mcidev_sysfs_group i7core_inject_addrmatch = {
+static const struct mcidev_sysfs_group i7core_inject_addrmatch = {
         .name  = "inject_addrmatch",
         .mcidev_attr = i7core_addrmatch_attrs,
 };
 
-static struct mcidev_sysfs_attribute i7core_udimm_counters_attrs[] = {
+static const struct mcidev_sysfs_attribute i7core_udimm_counters_attrs[] = {
         ATTR_COUNTER(0),
         ATTR_COUNTER(1),
         ATTR_COUNTER(2),
         { .attr = { .name = NULL } }
 };
 
-static struct mcidev_sysfs_group i7core_udimm_counters = {
+static const struct mcidev_sysfs_group i7core_udimm_counters = {
         .name  = "all_channel_counts",
         .mcidev_attr = i7core_udimm_counters_attrs,
 };
 
-static struct mcidev_sysfs_attribute i7core_sysfs_attrs[] = {
+static const struct mcidev_sysfs_attribute i7core_sysfs_rdimm_attrs[] = {
         {
                 .attr = {
                         .name = "inject_section",
@@ -1180,8 +1191,44 @@ static struct mcidev_sysfs_attribute i7core_sysfs_attrs[] = {
                 .show  = i7core_inject_enable_show,
                 .store = i7core_inject_enable_store,
         },
-        { .attr = { .name = NULL } },   /* Reserved for udimm counters */
-        { .attr = { .name = NULL } }
+        { }     /* End of list */
+};
+
+static const struct mcidev_sysfs_attribute i7core_sysfs_udimm_attrs[] = {
+        {
+                .attr = {
+                        .name = "inject_section",
+                        .mode = (S_IRUGO | S_IWUSR)
+                },
+                .show  = i7core_inject_section_show,
+                .store = i7core_inject_section_store,
+        }, {
+                .attr = {
+                        .name = "inject_type",
+                        .mode = (S_IRUGO | S_IWUSR)
+                },
+                .show  = i7core_inject_type_show,
+                .store = i7core_inject_type_store,
+        }, {
+                .attr = {
+                        .name = "inject_eccmask",
+                        .mode = (S_IRUGO | S_IWUSR)
+                },
+                .show  = i7core_inject_eccmask_show,
+                .store = i7core_inject_eccmask_store,
+        }, {
+                .grp = &i7core_inject_addrmatch,
+        }, {
+                .attr = {
+                        .name = "inject_enable",
+                        .mode = (S_IRUGO | S_IWUSR)
+                },
+                .show  = i7core_inject_enable_show,
+                .store = i7core_inject_enable_store,
+        }, {
+                .grp = &i7core_udimm_counters,
+        },
+        { }     /* End of list */
 };
 
 /****************************************************************************
@@ -1189,7 +1236,7 @@ static struct mcidev_sysfs_attribute i7core_sysfs_attrs[] = {
  ****************************************************************************/
 
 /*
- *      i7core_put_devices      'put' all the devices that we have
+ *      i7core_put_all_devices  'put' all the devices that we have
  *                              reserved via 'get'
  */
 static void i7core_put_devices(struct i7core_dev *i7core_dev)
@@ -1206,25 +1253,25 @@ static void i7core_put_devices(struct i7core_dev *i7core_dev)
                         PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
                 pci_dev_put(pdev);
         }
-        kfree(i7core_dev->pdev);
-        list_del(&i7core_dev->list);
-        kfree(i7core_dev);
 }
 
 static void i7core_put_all_devices(void)
 {
         struct i7core_dev *i7core_dev, *tmp;
 
-        list_for_each_entry_safe(i7core_dev, tmp, &i7core_edac_list, list)
+        list_for_each_entry_safe(i7core_dev, tmp, &i7core_edac_list, list) {
                 i7core_put_devices(i7core_dev);
+                free_i7core_dev(i7core_dev);
+        }
 }
 
-static void __init i7core_xeon_pci_fixup(struct pci_id_table *table)
+static void __init i7core_xeon_pci_fixup(const struct pci_id_table *table)
 {
         struct pci_dev *pdev = NULL;
         int i;
+
         /*
-         * On Xeon 55xx, the Intel Quckpath Arch Generic Non-core pci buses
+         * On Xeon 55xx, the Intel Quick Path Arch Generic Non-core pci buses
          * aren't announced by acpi. So, we need to use a legacy scan probing
          * to detect them
          */
@@ -1257,16 +1304,18 @@ static unsigned i7core_pci_lastbus(void)
 }
 
 /*
- *      i7core_get_devices      Find and perform 'get' operation on the MCH's
+ *      i7core_get_all_devices  Find and perform 'get' operation on the MCH's
  *                      device/functions we want to reference for this driver
  *
  *                      Need to 'get' device 16 func 1 and func 2
  */
-int i7core_get_onedevice(struct pci_dev **prev, int devno,
-                         struct pci_id_descr *dev_descr, unsigned n_devs,
-                         unsigned last_bus)
+static int i7core_get_onedevice(struct pci_dev **prev,
+                                const struct pci_id_table *table,
+                                const unsigned devno,
+                                const unsigned last_bus)
 {
         struct i7core_dev *i7core_dev;
+        const struct pci_id_descr *dev_descr = &table->descr[devno];
 
         struct pci_dev *pdev = NULL;
         u8 bus = 0;
@@ -1275,20 +1324,6 @@ int i7core_get_onedevice(struct pci_dev **prev, int devno,
         pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
                               dev_descr->dev_id, *prev);
 
-        /*
-         * On Xeon 55xx, the Intel Quckpath Arch Generic Non-core regs
-         * is at addr 8086:2c40, instead of 8086:2c41. So, we need
-         * to probe for the alternate address in case of failure
-         */
-        if (dev_descr->dev_id == PCI_DEVICE_ID_INTEL_I7_NONCORE && !pdev)
-                pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
-                                      PCI_DEVICE_ID_INTEL_I7_NONCORE_ALT, *prev);
-
-        if (dev_descr->dev_id == PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE && !pdev)
-                pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
-                                      PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE_ALT,
-                                      *prev);
-
         if (!pdev) {
                 if (*prev) {
                         *prev = pdev;
@@ -1315,18 +1350,11 @@ int i7core_get_onedevice(struct pci_dev **prev, int devno,
 
         i7core_dev = get_i7core_dev(socket);
         if (!i7core_dev) {
-                i7core_dev = kzalloc(sizeof(*i7core_dev), GFP_KERNEL);
-                if (!i7core_dev)
-                        return -ENOMEM;
-                i7core_dev->pdev = kzalloc(sizeof(*i7core_dev->pdev) * n_devs,
-                                           GFP_KERNEL);
-                if (!i7core_dev->pdev) {
-                        kfree(i7core_dev);
+                i7core_dev = alloc_i7core_dev(socket, table);
+                if (!i7core_dev) {
+                        pci_dev_put(pdev);
                         return -ENOMEM;
                 }
-                i7core_dev->socket = socket;
-                i7core_dev->n_devs = n_devs;
-                list_add_tail(&i7core_dev->list, &i7core_edac_list);
         }
 
         if (i7core_dev->pdev[devno]) {
@@ -1368,27 +1396,31 @@ int i7core_get_onedevice(struct pci_dev **prev, int devno,
                 dev_descr->func,
                 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
 
+        /*
+         * As stated on drivers/pci/search.c, the reference count for
+         * @from is always decremented if it is not %NULL. So, as we need
+         * to get all devices up to null, we need to do a get for the device
+         */
+        pci_dev_get(pdev);
+
         *prev = pdev;
 
         return 0;
 }
 
-static int i7core_get_devices(struct pci_id_table *table)
+static int i7core_get_all_devices(void)
 {
         int i, rc, last_bus;
         struct pci_dev *pdev = NULL;
-        struct pci_id_descr *dev_descr;
+        const struct pci_id_table *table = pci_dev_table;
 
         last_bus = i7core_pci_lastbus();
 
         while (table && table->descr) {
-                dev_descr = table->descr;
                 for (i = 0; i < table->n_devs; i++) {
                         pdev = NULL;
                         do {
-                                rc = i7core_get_onedevice(&pdev, i,
-                                                          &dev_descr[i],
-                                                          table->n_devs,
+                                rc = i7core_get_onedevice(&pdev, table, i,
                                                           last_bus);
                                 if (rc < 0) {
                                         if (i == 0) {
@@ -1404,7 +1436,6 @@ static int i7core_get_devices(struct pci_id_table *table)
         }
 
         return 0;
-        return 0;
 }
 
 static int mci_bind_devs(struct mem_ctl_info *mci,
@@ -1414,10 +1445,6 @@ static int mci_bind_devs(struct mem_ctl_info *mci,
         struct pci_dev *pdev;
         int i, func, slot;
 
-        /* Associates i7core_dev and mci for future usage */
-        pvt->i7core_dev = i7core_dev;
-        i7core_dev->mci = mci;
-
         pvt->is_registered = 0;
         for (i = 0; i < i7core_dev->n_devs; i++) {
                 pdev = i7core_dev->pdev[i];
@@ -1448,15 +1475,6 @@ static int mci_bind_devs(struct mem_ctl_info *mci,
                         pvt->is_registered = 1;
         }
 
-        /*
-         * Add extra nodes to count errors on udimm
-         * For registered memory, this is not needed, since the counters
-         * are already displayed at the standard locations
-         */
-        if (!pvt->is_registered)
-                i7core_sysfs_attrs[ARRAY_SIZE(i7core_sysfs_attrs)-2].grp =
-                        &i7core_udimm_counters;
-
         return 0;
 
 error:
@@ -1470,7 +1488,9 @@ error:
                         Error check routines
  ****************************************************************************/
 static void i7core_rdimm_update_csrow(struct mem_ctl_info *mci,
-                                         int chan, int dimm, int add)
+                                      const int chan,
+                                      const int dimm,
+                                      const int add)
 {
         char *msg;
         struct i7core_pvt *pvt = mci->pvt_info;
@@ -1487,7 +1507,10 @@ static void i7core_rdimm_update_csrow(struct mem_ctl_info *mci,
 }
 
 static void i7core_rdimm_update_ce_count(struct mem_ctl_info *mci,
-                        int chan, int new0, int new1, int new2)
+                                         const int chan,
+                                         const int new0,
+                                         const int new1,
+                                         const int new2)
 {
         struct i7core_pvt *pvt = mci->pvt_info;
         int add0 = 0, add1 = 0, add2 = 0;
@@ -1641,7 +1664,7 @@ static void i7core_udimm_check_mc_ecc_err(struct mem_ctl_info *mci)
  * fields
  */
 static void i7core_mce_output_error(struct mem_ctl_info *mci,
-                                    struct mce *m)
+                                    const struct mce *m)
 {
         struct i7core_pvt *pvt = mci->pvt_info;
         char *type, *optype, *err, *msg;
@@ -1749,7 +1772,7 @@ static void i7core_check_error(struct mem_ctl_info *mci)
         /*
          * MCE first step: Copy all mce errors into a temporary buffer
          * We use a double buffering here, to reduce the risk of
-         * loosing an error.
+         * losing an error.
          */
         smp_rmb();
         count = (pvt->mce_out + MCE_LOG_LEN - pvt->mce_in)
@@ -1841,32 +1864,89 @@ static int i7core_mce_check_error(void *priv, struct mce *mce)
         if (mce->mcgstatus & 1)
                 i7core_check_error(mci);
 
-        /* Advice mcelog that the error were handled */
+        /* Advise mcelog that the errors were handled */
         return 1;
 }
 
-static int i7core_register_mci(struct i7core_dev *i7core_dev,
-                               int num_channels, int num_csrows)
+static void i7core_pci_ctl_create(struct i7core_pvt *pvt)
+{
+        pvt->i7core_pci = edac_pci_create_generic_ctl(
+                                                &pvt->i7core_dev->pdev[0]->dev,
+                                                EDAC_MOD_STR);
+        if (unlikely(!pvt->i7core_pci))
+                pr_warn("Unable to setup PCI error report via EDAC\n");
+}
+
+static void i7core_pci_ctl_release(struct i7core_pvt *pvt)
+{
+        if (likely(pvt->i7core_pci))
+                edac_pci_release_generic_ctl(pvt->i7core_pci);
+        else
+                i7core_printk(KERN_ERR,
+                                "Couldn't find mem_ctl_info for socket %d\n",
+                                pvt->i7core_dev->socket);
+        pvt->i7core_pci = NULL;
+}
+
+static void i7core_unregister_mci(struct i7core_dev *i7core_dev)
+{
+        struct mem_ctl_info *mci = i7core_dev->mci;
+        struct i7core_pvt *pvt;
+
+        if (unlikely(!mci || !mci->pvt_info)) {
+                debugf0("MC: " __FILE__ ": %s(): dev = %p\n",
+                        __func__, &i7core_dev->pdev[0]->dev);
+
+                i7core_printk(KERN_ERR, "Couldn't find mci handler\n");
+                return;
+        }
+
+        pvt = mci->pvt_info;
+
+        debugf0("MC: " __FILE__ ": %s(): mci = %p, dev = %p\n",
+                __func__, mci, &i7core_dev->pdev[0]->dev);
+
+        /* Disable MCE NMI handler */
+        edac_mce_unregister(&pvt->edac_mce);
+
+        /* Disable EDAC polling */
+        i7core_pci_ctl_release(pvt);
+
+        /* Remove MC sysfs nodes */
+        edac_mc_del_mc(mci->dev);
+
+        debugf1("%s: free mci struct\n", mci->ctl_name);
+        kfree(mci->ctl_name);
+        edac_mc_free(mci);
+        i7core_dev->mci = NULL;
+}
+
+static int i7core_register_mci(struct i7core_dev *i7core_dev)
 {
         struct mem_ctl_info *mci;
         struct i7core_pvt *pvt;
-        int csrow = 0;
-        int rc;
+        int rc, channels, csrows;
+
+        /* Check the number of active and not disabled channels */
+        rc = i7core_get_active_channels(i7core_dev->socket, &channels, &csrows);
+        if (unlikely(rc < 0))
+                return rc;
 
         /* allocate a new MC control structure */
-        mci = edac_mc_alloc(sizeof(*pvt), num_csrows, num_channels,
-                            i7core_dev->socket);
+        mci = edac_mc_alloc(sizeof(*pvt), csrows, channels, i7core_dev->socket);
         if (unlikely(!mci))
                 return -ENOMEM;
 
-        debugf0("MC: " __FILE__ ": %s(): mci = %p\n", __func__, mci);
-
-        /* record ptr to the generic device */
-        mci->dev = &i7core_dev->pdev[0]->dev;
+        debugf0("MC: " __FILE__ ": %s(): mci = %p, dev = %p\n",
+                __func__, mci, &i7core_dev->pdev[0]->dev);
 
         pvt = mci->pvt_info;
         memset(pvt, 0, sizeof(*pvt));
 
+        /* Associates i7core_dev and mci for future usage */
+        pvt->i7core_dev = i7core_dev;
+        i7core_dev->mci = mci;
+
         /*
          * FIXME: how to handle RDDR3 at MCI level? It is possible to have
          * Mixed RDDR3/UDDR3 with Nehalem, provided that they are on different
@@ -1881,17 +1961,23 @@ static int i7core_register_mci(struct i7core_dev *i7core_dev,
                                   i7core_dev->socket);
         mci->dev_name = pci_name(i7core_dev->pdev[0]);
         mci->ctl_page_to_phys = NULL;
-        mci->mc_driver_sysfs_attributes = i7core_sysfs_attrs;
-        /* Set the function pointer to an actual operation function */
-        mci->edac_check = i7core_check_error;
 
         /* Store pci devices at mci for faster access */
         rc = mci_bind_devs(mci, i7core_dev);
         if (unlikely(rc < 0))
-                goto fail;
+                goto fail0;
+
+        if (pvt->is_registered)
+                mci->mc_driver_sysfs_attributes = i7core_sysfs_rdimm_attrs;
+        else
+                mci->mc_driver_sysfs_attributes = i7core_sysfs_udimm_attrs;
 
         /* Get dimm basic config */
-        get_dimm_config(mci, &csrow);
+        get_dimm_config(mci);
+        /* record ptr to the generic device */
+        mci->dev = &i7core_dev->pdev[0]->dev;
+        /* Set the function pointer to an actual operation function */
+        mci->edac_check = i7core_check_error;
 
         /* add this new MC control structure to EDAC's list of MCs */
         if (unlikely(edac_mc_add_mc(mci))) {
@@ -1902,19 +1988,7 @@ static int i7core_register_mci(struct i7core_dev *i7core_dev,
                  */
 
                 rc = -EINVAL;
-                goto fail;
-        }
-
-        /* allocating generic PCI control info */
-        i7core_pci = edac_pci_create_generic_ctl(&i7core_dev->pdev[0]->dev,
-                                                 EDAC_MOD_STR);
-        if (unlikely(!i7core_pci)) {
-                printk(KERN_WARNING
-                        "%s(): Unable to create PCI control\n",
-                        __func__);
-                printk(KERN_WARNING
-                        "%s(): PCI error report via EDAC not setup\n",
-                        __func__);
+                goto fail0;
         }
 
         /* Default error mask is any memory */
@@ -1925,19 +1999,28 @@ static int i7core_register_mci(struct i7core_dev *i7core_dev,
         pvt->inject.page = -1;
         pvt->inject.col = -1;
 
+        /* allocating generic PCI control info */
+        i7core_pci_ctl_create(pvt);
+
         /* Registers on edac_mce in order to receive memory errors */
         pvt->edac_mce.priv = mci;
         pvt->edac_mce.check_error = i7core_mce_check_error;
-
         rc = edac_mce_register(&pvt->edac_mce);
         if (unlikely(rc < 0)) {
                 debugf0("MC: " __FILE__
                         ": %s(): failed edac_mce_register()\n", __func__);
+                goto fail1;
         }
 
-fail:
-        if (rc < 0)
-                edac_mc_free(mci);
+        return 0;
+
+fail1:
+        i7core_pci_ctl_release(pvt);
+        edac_mc_del_mc(mci->dev);
+fail0:
+        kfree(mci->ctl_name);
+        edac_mc_free(mci);
+        i7core_dev->mci = NULL;
         return rc;
 }
 
@@ -1949,8 +2032,6 @@ fail:
  *              < 0 for error code
  */
 
-static int probed = 0;
-
 static int __devinit i7core_probe(struct pci_dev *pdev,
                                   const struct pci_device_id *id)
 {
@@ -1965,25 +2046,16 @@ static int __devinit i7core_probe(struct pci_dev *pdev,
          */
         if (unlikely(probed >= 1)) {
                 mutex_unlock(&i7core_edac_lock);
-                return -EINVAL;
+                return -ENODEV;
         }
         probed++;
 
-        rc = i7core_get_devices(pci_dev_table);
+        rc = i7core_get_all_devices();
         if (unlikely(rc < 0))
                 goto fail0;
 
         list_for_each_entry(i7core_dev, &i7core_edac_list, list) {
-                int channels;
-                int csrows;
-
-                /* Check the number of active and not disabled channels */
-                rc = i7core_get_active_channels(i7core_dev->socket,
-                                                &channels, &csrows);
-                if (unlikely(rc < 0))
-                        goto fail1;
-
-                rc = i7core_register_mci(i7core_dev, channels, csrows);
+                rc = i7core_register_mci(i7core_dev);
                 if (unlikely(rc < 0))
                         goto fail1;
         }
@@ -1994,6 +2066,9 @@ static int __devinit i7core_probe(struct pci_dev *pdev,
         return 0;
 
 fail1:
+        list_for_each_entry(i7core_dev, &i7core_edac_list, list)
+                i7core_unregister_mci(i7core_dev);
+
         i7core_put_all_devices();
 fail0:
         mutex_unlock(&i7core_edac_lock);
@@ -2006,14 +2081,10 @@ fail0:
  */
 static void __devexit i7core_remove(struct pci_dev *pdev)
 {
-        struct mem_ctl_info *mci;
-        struct i7core_dev *i7core_dev, *tmp;
+        struct i7core_dev *i7core_dev;
 
         debugf0(__FILE__ ": %s()\n", __func__);
 
-        if (i7core_pci)
-                edac_pci_release_generic_ctl(i7core_pci);
-
         /*
          * we have a trouble here: pdev value for removal will be wrong, since
          * it will point to the X58 register used to detect that the machine
@@ -2023,22 +2094,18 @@ static void __devexit i7core_remove(struct pci_dev *pdev)
          */
 
         mutex_lock(&i7core_edac_lock);
-        list_for_each_entry_safe(i7core_dev, tmp, &i7core_edac_list, list) {
-                mci = edac_mc_del_mc(&i7core_dev->pdev[0]->dev);
-                if (mci) {
-                        struct i7core_pvt *pvt = mci->pvt_info;
-
-                        i7core_dev = pvt->i7core_dev;
-                        edac_mce_unregister(&pvt->edac_mce);
-                        kfree(mci->ctl_name);
-                        edac_mc_free(mci);
-                        i7core_put_devices(i7core_dev);
-                } else {
-                        i7core_printk(KERN_ERR,
-                                      "Couldn't find mci for socket %d\n",
-                                      i7core_dev->socket);
-                }
+
+        if (unlikely(!probed)) {
+                mutex_unlock(&i7core_edac_lock);
+                return;
         }
+
+        list_for_each_entry(i7core_dev, &i7core_edac_list, list)
+                i7core_unregister_mci(i7core_dev);
+
+        /* Release PCI resources */
+        i7core_put_all_devices();
+
         probed--;
 
         mutex_unlock(&i7core_edac_lock);
@@ -2070,7 +2137,8 @@ static int __init i7core_init(void)
         /* Ensure that the OPSTATE is set correctly for POLL or NMI */
         opstate_init();
 
-        i7core_xeon_pci_fixup(pci_dev_table);
+        if (use_pci_fixup)
+                i7core_xeon_pci_fixup(pci_dev_table);
 
         pci_rc = pci_register_driver(&i7core_driver);
 
diff --git a/drivers/edac/i82443bxgx_edac.c b/drivers/edac/i82443bxgx_edac.c
index a2fa1feed724..4329d39f902c 100644
--- a/drivers/edac/i82443bxgx_edac.c
+++ b/drivers/edac/i82443bxgx_edac.c
@@ -12,7 +12,7 @@
  * 440GX fix by Jason Uhlenkott <juhlenko@akamai.com>.
  *
  * Written with reference to 82443BX Host Bridge Datasheet:
- * http://www.intel.com/design/chipsets/440/documentation.htm
+ * http://download.intel.com/design/chipsets/datashts/29063301.pdf 
  * references to this document given in [].
  *
  * This module doesn't support the 440LX, but it may be possible to
@@ -203,7 +203,7 @@ static void i82443bxgx_init_csrows(struct mem_ctl_info *mci,
                 row_high_limit = ((u32) drbar << 23);
                 /* find the DRAM Chip Select Base address and mask */
                 debugf1("MC%d: %s: %s() Row=%d, "
-                        "Boundry Address=%#0x, Last = %#0x\n",
+                        "Boundary Address=%#0x, Last = %#0x\n",
                         mci->mc_idx, __FILE__, __func__, index, row_high_limit,
                         row_high_limit_last);
 
@@ -305,7 +305,7 @@ static int i82443bxgx_edacmc_probe1(struct pci_dev *pdev, int dev_idx)
         i82443bxgx_init_csrows(mci, pdev, edac_mode, mtype);
 
         /* Many BIOSes don't clear error flags on boot, so do this
-         * here, or we get "phantom" errors occuring at module-load
+         * here, or we get "phantom" errors occurring at module-load
          * time. */
         pci_write_bits32(pdev, I82443BXGX_EAP,
                         (I82443BXGX_EAP_OFFSET_SBE |
diff --git a/drivers/edac/i82860_edac.c b/drivers/edac/i82860_edac.c
index b8a95cf50718..931a05775049 100644
--- a/drivers/edac/i82860_edac.c
+++ b/drivers/edac/i82860_edac.c
@@ -16,7 +16,7 @@
 #include <linux/edac.h>
 #include "edac_core.h"
 
-#define  I82860_REVISION " Ver: 2.0.2 " __DATE__
+#define  I82860_REVISION " Ver: 2.0.2"
 #define EDAC_MOD_STR    "i82860_edac"
 
 #define i82860_printk(level, fmt, arg...) \
diff --git a/drivers/edac/i82875p_edac.c b/drivers/edac/i82875p_edac.c
index b2fd1e899142..33864c63c684 100644
--- a/drivers/edac/i82875p_edac.c
+++ b/drivers/edac/i82875p_edac.c
@@ -20,7 +20,7 @@
 #include <linux/edac.h>
 #include "edac_core.h"
 
-#define I82875P_REVISION        " Ver: 2.0.2 " __DATE__
+#define I82875P_REVISION        " Ver: 2.0.2"
 #define EDAC_MOD_STR            "i82875p_edac"
 
 #define i82875p_printk(level, fmt, arg...) \
diff --git a/drivers/edac/i82975x_edac.c b/drivers/edac/i82975x_edac.c
index 3218819b7286..a5da732fe5b2 100644
--- a/drivers/edac/i82975x_edac.c
+++ b/drivers/edac/i82975x_edac.c
@@ -16,7 +16,7 @@
 #include <linux/edac.h>
 #include "edac_core.h"
 
-#define I82975X_REVISION        " Ver: 1.0.0 " __DATE__
+#define I82975X_REVISION        " Ver: 1.0.0"
 #define EDAC_MOD_STR            "i82975x_edac"
 
 #define i82975x_printk(level, fmt, arg...) \
@@ -160,8 +160,8 @@ NOTE: Only ONE of the three must be enabled
                                          * 3:2  Rank 1 architecture
                                          * 1:0  Rank 0 architecture
                                          *
-                                         * 00 => x16 devices; i.e 4 banks
-                                         * 01 => x8  devices; i.e 8 banks
+                                         * 00 => 4 banks
+                                         * 01 => 8 banks
                                          */
 #define I82975X_C0BNKARC        0x10e
 #define I82975X_C1BNKARC        0x18e
@@ -278,6 +278,7 @@ static int i82975x_process_error_info(struct mem_ctl_info *mci,
                 struct i82975x_error_info *info, int handle_errors)
 {
         int row, multi_chan, chan;
+        unsigned long offst, page;
 
         multi_chan = mci->csrows[0].nr_channels - 1;
 
@@ -292,17 +293,19 @@ static int i82975x_process_error_info(struct mem_ctl_info *mci,
                 info->errsts = info->errsts2;
         }
 
-        chan = info->eap & 1;
-        info->eap >>= 1;
-        if (info->xeap )
-                info->eap |= 0x80000000;
-        info->eap >>= PAGE_SHIFT;
-        row = edac_mc_find_csrow_by_page(mci, info->eap);
+        page = (unsigned long) info->eap;
+        if (info->xeap & 1)
+                page |= 0x100000000ul;
+        chan = page & 1;
+        page >>= 1;
+        offst = page & ((1 << PAGE_SHIFT) - 1);
+        page >>= PAGE_SHIFT;
+        row = edac_mc_find_csrow_by_page(mci, page);
 
         if (info->errsts & 0x0002)
-                edac_mc_handle_ue(mci, info->eap, 0, row, "i82975x UE");
+                edac_mc_handle_ue(mci, page, offst , row, "i82975x UE");
         else
-                edac_mc_handle_ce(mci, info->eap, 0, info->derrsyn, row,
+                edac_mc_handle_ce(mci, page, offst, info->derrsyn, row,
                                 multi_chan ? chan : 0,
                                 "i82975x CE");
 
@@ -344,11 +347,7 @@ static int dual_channel_active(void __iomem *mch_window)
 static enum dev_type i82975x_dram_type(void __iomem *mch_window, int rank)
 {
         /*
-         * ASUS P5W DH either does not program this register or programs
-         * it wrong!
-         * ECC is possible on i92975x ONLY with DEV_X8 which should mean 'val'
-         * for each rank should be 01b - the LSB of the word should be 0x55;
-         * but it reads 0!
+         * ECC is possible on i92975x ONLY with DEV_X8
          */
         return DEV_X8;
 }
@@ -356,11 +355,15 @@ static enum dev_type i82975x_dram_type(void __iomem *mch_window, int rank)
 static void i82975x_init_csrows(struct mem_ctl_info *mci,
                 struct pci_dev *pdev, void __iomem *mch_window)
 {
+        static const char *labels[4] = {
+                                                        "DIMM A1", "DIMM A2",
+                                                        "DIMM B1", "DIMM B2"
+                                                };
         struct csrow_info *csrow;
         unsigned long last_cumul_size;
         u8 value;
         u32 cumul_size;
-        int index;
+        int index, chan;
 
         last_cumul_size = 0;
 
@@ -369,11 +372,7 @@ static void i82975x_init_csrows(struct mem_ctl_info *mci,
          * The dram row boundary (DRB) reg values are boundary address
          * for each DRAM row with a granularity of 32 or 64MB (single/dual
          * channel operation).  DRB regs are cumulative; therefore DRB7 will
-         * contain the total memory contained in all eight rows.
-         *
-         * FIXME:
-         *  EDAC currently works for Dual-channel Interleaved configuration.
-         *  Other configurations, which the chip supports, need fixing/testing.
+         * contain the total memory contained in all rows.
          *
          */
 
@@ -384,8 +383,26 @@ static void i82975x_init_csrows(struct mem_ctl_info *mci,
                                         ((index >= 4) ? 0x80 : 0));
                 cumul_size = value;
                 cumul_size <<= (I82975X_DRB_SHIFT - PAGE_SHIFT);
+                /*
+                 * Adjust cumul_size w.r.t number of channels
+                 *
+                 */
+                if (csrow->nr_channels > 1)
+                        cumul_size <<= 1;
                 debugf3("%s(): (%d) cumul_size 0x%x\n", __func__, index,
                         cumul_size);
+
+                /*
+                 * Initialise dram labels
+                 * index values:
+                 *   [0-7] for single-channel; i.e. csrow->nr_channels = 1
+                 *   [0-3] for dual-channel; i.e. csrow->nr_channels = 2
+                 */
+                for (chan = 0; chan < csrow->nr_channels; chan++)
+                        strncpy(csrow->channels[chan].label,
+                                        labels[(index >> 1) + (chan * 2)],
+                                        EDAC_MC_LABEL_LEN);
+
                 if (cumul_size == last_cumul_size)
                         continue;       /* not populated */
 
@@ -393,8 +410,8 @@ static void i82975x_init_csrows(struct mem_ctl_info *mci,
                 csrow->last_page = cumul_size - 1;
                 csrow->nr_pages = cumul_size - last_cumul_size;
                 last_cumul_size = cumul_size;
-                csrow->grain = 1 << 7;  /* I82975X_EAP has 128B resolution */
-                csrow->mtype = MEM_DDR; /* i82975x supports only DDR2 */
+                csrow->grain = 1 << 6;  /* I82975X_EAP has 64B resolution */
+                csrow->mtype = MEM_DDR2; /* I82975x supports only DDR2 */
                 csrow->dtype = i82975x_dram_type(mch_window, index);
                 csrow->edac_mode = EDAC_SECDED; /* only supported */
         }
@@ -515,18 +532,20 @@ static int i82975x_probe1(struct pci_dev *pdev, int dev_idx)
 
         debugf3("%s(): init mci\n", __func__);
         mci->dev = &pdev->dev;
-        mci->mtype_cap = MEM_FLAG_DDR;
+        mci->mtype_cap = MEM_FLAG_DDR2;
         mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
         mci->edac_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
         mci->mod_name = EDAC_MOD_STR;
         mci->mod_ver = I82975X_REVISION;
         mci->ctl_name = i82975x_devs[dev_idx].ctl_name;
+        mci->dev_name = pci_name(pdev);
         mci->edac_check = i82975x_check;
         mci->ctl_page_to_phys = NULL;
         debugf3("%s(): init pvt\n", __func__);
         pvt = (struct i82975x_pvt *) mci->pvt_info;
         pvt->mch_window = mch_window;
         i82975x_init_csrows(mci, pdev, mch_window);
+        mci->scrub_mode = SCRUB_HW_SRC;
         i82975x_get_error_info(mci, &discard);  /* clear counters */
 
         /* finalize this instance of memory controller with edac core */
@@ -664,7 +683,7 @@ module_init(i82975x_init);
 module_exit(i82975x_exit);
 
 MODULE_LICENSE("GPL");
-MODULE_AUTHOR("Arvind R. <arvind@acarlab.com>");
+MODULE_AUTHOR("Arvind R. <arvino55@gmail.com>");
 MODULE_DESCRIPTION("MC support for Intel 82975 memory hub controllers");
 
 module_param(edac_op_state, int, 0444);
diff --git a/drivers/edac/mce_amd.c b/drivers/edac/mce_amd.c
new file mode 100644
index 000000000000..795cfbc0bf50
--- /dev/null
+++ b/drivers/edac/mce_amd.c
@@ -0,0 +1,920 @@
+#include <linux/module.h>
+#include <linux/slab.h>
+
+#include "mce_amd.h"
+
+static struct amd_decoder_ops *fam_ops;
+
+static u8 xec_mask       = 0xf;
+static u8 nb_err_cpumask = 0xf;
+
+static bool report_gart_errors;
+static void (*nb_bus_decoder)(int node_id, struct mce *m, u32 nbcfg);
+
+void amd_report_gart_errors(bool v)
+{
+        report_gart_errors = v;
+}
+EXPORT_SYMBOL_GPL(amd_report_gart_errors);
+
+void amd_register_ecc_decoder(void (*f)(int, struct mce *, u32))
+{
+        nb_bus_decoder = f;
+}
+EXPORT_SYMBOL_GPL(amd_register_ecc_decoder);
+
+void amd_unregister_ecc_decoder(void (*f)(int, struct mce *, u32))
+{
+        if (nb_bus_decoder) {
+                WARN_ON(nb_bus_decoder != f);
+
+                nb_bus_decoder = NULL;
+        }
+}
+EXPORT_SYMBOL_GPL(amd_unregister_ecc_decoder);
+
+/*
+ * string representation for the different MCA reported error types, see F3x48
+ * or MSR0000_0411.
+ */
+
+/* transaction type */
+const char *tt_msgs[] = { "INSN", "DATA", "GEN", "RESV" };
+EXPORT_SYMBOL_GPL(tt_msgs);
+
+/* cache level */
+const char *ll_msgs[] = { "RESV", "L1", "L2", "L3/GEN" };
+EXPORT_SYMBOL_GPL(ll_msgs);
+
+/* memory transaction type */
+const char *rrrr_msgs[] = {
+       "GEN", "RD", "WR", "DRD", "DWR", "IRD", "PRF", "EV", "SNP"
+};
+EXPORT_SYMBOL_GPL(rrrr_msgs);
+
+/* participating processor */
+const char *pp_msgs[] = { "SRC", "RES", "OBS", "GEN" };
+EXPORT_SYMBOL_GPL(pp_msgs);
+
+/* request timeout */
+const char *to_msgs[] = { "no timeout", "timed out" };
+EXPORT_SYMBOL_GPL(to_msgs);
+
+/* memory or i/o */
+const char *ii_msgs[] = { "MEM", "RESV", "IO", "GEN" };
+EXPORT_SYMBOL_GPL(ii_msgs);
+
+static const char *f10h_nb_mce_desc[] = {
+        "HT link data error",
+        "Protocol error (link, L3, probe filter, etc.)",
+        "Parity error in NB-internal arrays",
+        "Link Retry due to IO link transmission error",
+        "L3 ECC data cache error",
+        "ECC error in L3 cache tag",
+        "L3 LRU parity bits error",
+        "ECC Error in the Probe Filter directory"
+};
+
+static const char * const f15h_ic_mce_desc[] = {
+        "UC during a demand linefill from L2",
+        "Parity error during data load from IC",
+        "Parity error for IC valid bit",
+        "Main tag parity error",
+        "Parity error in prediction queue",
+        "PFB data/address parity error",
+        "Parity error in the branch status reg",
+        "PFB promotion address error",
+        "Tag error during probe/victimization",
+        "Parity error for IC probe tag valid bit",
+        "PFB non-cacheable bit parity error",
+        "PFB valid bit parity error",                   /* xec = 0xd */
+        "patch RAM",                                    /* xec = 010 */
+        "uop queue",
+        "insn buffer",
+        "predecode buffer",
+        "fetch address FIFO"
+};
+
+static const char * const f15h_cu_mce_desc[] = {
+        "Fill ECC error on data fills",                 /* xec = 0x4 */
+        "Fill parity error on insn fills",
+        "Prefetcher request FIFO parity error",
+        "PRQ address parity error",
+        "PRQ data parity error",
+        "WCC Tag ECC error",
+        "WCC Data ECC error",
+        "WCB Data parity error",
+        "VB Data/ECC error",
+        "L2 Tag ECC error",                             /* xec = 0x10 */
+        "Hard L2 Tag ECC error",
+        "Multiple hits on L2 tag",
+        "XAB parity error",
+        "PRB address parity error"
+};
+
+static const char * const fr_ex_mce_desc[] = {
+        "CPU Watchdog timer expire",
+        "Wakeup array dest tag",
+        "AG payload array",
+        "EX payload array",
+        "IDRF array",
+        "Retire dispatch queue",
+        "Mapper checkpoint array",
+        "Physical register file EX0 port",
+        "Physical register file EX1 port",
+        "Physical register file AG0 port",
+        "Physical register file AG1 port",
+        "Flag register file",
+        "DE correctable error could not be corrected"
+};
+
+static bool f12h_dc_mce(u16 ec, u8 xec)
+{
+        bool ret = false;
+
+        if (MEM_ERROR(ec)) {
+                u8 ll = LL(ec);
+                ret = true;
+
+                if (ll == LL_L2)
+                        pr_cont("during L1 linefill from L2.\n");
+                else if (ll == LL_L1)
+                        pr_cont("Data/Tag %s error.\n", R4_MSG(ec));
+                else
+                        ret = false;
+        }
+        return ret;
+}
+
+static bool f10h_dc_mce(u16 ec, u8 xec)
+{
+        if (R4(ec) == R4_GEN && LL(ec) == LL_L1) {
+                pr_cont("during data scrub.\n");
+                return true;
+        }
+        return f12h_dc_mce(ec, xec);
+}
+
+static bool k8_dc_mce(u16 ec, u8 xec)
+{
+        if (BUS_ERROR(ec)) {
+                pr_cont("during system linefill.\n");
+                return true;
+        }
+
+        return f10h_dc_mce(ec, xec);
+}
+
+static bool f14h_dc_mce(u16 ec, u8 xec)
+{
+        u8 r4    = R4(ec);
+        bool ret = true;
+
+        if (MEM_ERROR(ec)) {
+
+                if (TT(ec) != TT_DATA || LL(ec) != LL_L1)
+                        return false;
+
+                switch (r4) {
+                case R4_DRD:
+                case R4_DWR:
+                        pr_cont("Data/Tag parity error due to %s.\n",
+                                (r4 == R4_DRD ? "load/hw prf" : "store"));
+                        break;
+                case R4_EVICT:
+                        pr_cont("Copyback parity error on a tag miss.\n");
+                        break;
+                case R4_SNOOP:
+                        pr_cont("Tag parity error during snoop.\n");
+                        break;
+                default:
+                        ret = false;
+                }
+        } else if (BUS_ERROR(ec)) {
+
+                if ((II(ec) != II_MEM && II(ec) != II_IO) || LL(ec) != LL_LG)
+                        return false;
+
+                pr_cont("System read data error on a ");
+
+                switch (r4) {
+                case R4_RD:
+                        pr_cont("TLB reload.\n");
+                        break;
+                case R4_DWR:
+                        pr_cont("store.\n");
+                        break;
+                case R4_DRD:
+                        pr_cont("load.\n");
+                        break;
+                default:
+                        ret = false;
+                }
+        } else {
+                ret = false;
+        }
+
+        return ret;
+}
+
+static bool f15h_dc_mce(u16 ec, u8 xec)
+{
+        bool ret = true;
+
+        if (MEM_ERROR(ec)) {
+
+                switch (xec) {
+                case 0x0:
+                        pr_cont("Data Array access error.\n");
+                        break;
+
+                case 0x1:
+                        pr_cont("UC error during a linefill from L2/NB.\n");
+                        break;
+
+                case 0x2:
+                case 0x11:
+                        pr_cont("STQ access error.\n");
+                        break;
+
+                case 0x3:
+                        pr_cont("SCB access error.\n");
+                        break;
+
+                case 0x10:
+                        pr_cont("Tag error.\n");
+                        break;
+
+                case 0x12:
+                        pr_cont("LDQ access error.\n");
+                        break;
+
+                default:
+                        ret = false;
+                }
+        } else if (BUS_ERROR(ec)) {
+
+                if (!xec)
+                        pr_cont("during system linefill.\n");
+                else
+                        pr_cont(" Internal %s condition.\n",
+                                ((xec == 1) ? "livelock" : "deadlock"));
+        } else
+                ret = false;
+
+        return ret;
+}
+
+static void amd_decode_dc_mce(struct mce *m)
+{
+        u16 ec = EC(m->status);
+        u8 xec = XEC(m->status, xec_mask);
+
+        pr_emerg(HW_ERR "Data Cache Error: ");
+
+        /* TLB error signatures are the same across families */
+        if (TLB_ERROR(ec)) {
+                if (TT(ec) == TT_DATA) {
+                        pr_cont("%s TLB %s.\n", LL_MSG(ec),
+                                ((xec == 2) ? "locked miss"
+                                            : (xec ? "multimatch" : "parity")));
+                        return;
+                }
+        } else if (fam_ops->dc_mce(ec, xec))
+                ;
+        else
+                pr_emerg(HW_ERR "Corrupted DC MCE info?\n");
+}
+
+static bool k8_ic_mce(u16 ec, u8 xec)
+{
+        u8 ll    = LL(ec);
+        bool ret = true;
+
+        if (!MEM_ERROR(ec))
+                return false;
+
+        if (ll == 0x2)
+                pr_cont("during a linefill from L2.\n");
+        else if (ll == 0x1) {
+                switch (R4(ec)) {
+                case R4_IRD:
+                        pr_cont("Parity error during data load.\n");
+                        break;
+
+                case R4_EVICT:
+                        pr_cont("Copyback Parity/Victim error.\n");
+                        break;
+
+                case R4_SNOOP:
+                        pr_cont("Tag Snoop error.\n");
+                        break;
+
+                default:
+                        ret = false;
+                        break;
+                }
+        } else
+                ret = false;
+
+        return ret;
+}
+
+static bool f14h_ic_mce(u16 ec, u8 xec)
+{
+        u8 r4    = R4(ec);
+        bool ret = true;
+
+        if (MEM_ERROR(ec)) {
+                if (TT(ec) != 0 || LL(ec) != 1)
+                        ret = false;
+
+                if (r4 == R4_IRD)
+                        pr_cont("Data/tag array parity error for a tag hit.\n");
+                else if (r4 == R4_SNOOP)
+                        pr_cont("Tag error during snoop/victimization.\n");
+                else
+                        ret = false;
+        }
+        return ret;
+}
+
+static bool f15h_ic_mce(u16 ec, u8 xec)
+{
+        bool ret = true;
+
+        if (!MEM_ERROR(ec))
+                return false;
+
+        switch (xec) {
+        case 0x0 ... 0xa:
+                pr_cont("%s.\n", f15h_ic_mce_desc[xec]);
+                break;
+
+        case 0xd:
+                pr_cont("%s.\n", f15h_ic_mce_desc[xec-2]);
+                break;
+
+        case 0x10 ... 0x14:
+                pr_cont("Decoder %s parity error.\n", f15h_ic_mce_desc[xec-4]);
+                break;
+
+        default:
+                ret = false;
+        }
+        return ret;
+}
+
+static void amd_decode_ic_mce(struct mce *m)
+{
+        u16 ec = EC(m->status);
+        u8 xec = XEC(m->status, xec_mask);
+
+        pr_emerg(HW_ERR "Instruction Cache Error: ");
+
+        if (TLB_ERROR(ec))
+                pr_cont("%s TLB %s.\n", LL_MSG(ec),
+                        (xec ? "multimatch" : "parity error"));
+        else if (BUS_ERROR(ec)) {
+                bool k8 = (boot_cpu_data.x86 == 0xf && (m->status & BIT_64(58)));
+
+                pr_cont("during %s.\n", (k8 ? "system linefill" : "NB data read"));
+        } else if (fam_ops->ic_mce(ec, xec))
+                ;
+        else
+                pr_emerg(HW_ERR "Corrupted IC MCE info?\n");
+}
+
+static void amd_decode_bu_mce(struct mce *m)
+{
+        u16 ec = EC(m->status);
+        u8 xec = XEC(m->status, xec_mask);
+
+        pr_emerg(HW_ERR "Bus Unit Error");
+
+        if (xec == 0x1)
+                pr_cont(" in the write data buffers.\n");
+        else if (xec == 0x3)
+                pr_cont(" in the victim data buffers.\n");
+        else if (xec == 0x2 && MEM_ERROR(ec))
+                pr_cont(": %s error in the L2 cache tags.\n", R4_MSG(ec));
+        else if (xec == 0x0) {
+                if (TLB_ERROR(ec))
+                        pr_cont(": %s error in a Page Descriptor Cache or "
+                                "Guest TLB.\n", TT_MSG(ec));
+                else if (BUS_ERROR(ec))
+                        pr_cont(": %s/ECC error in data read from NB: %s.\n",
+                                R4_MSG(ec), PP_MSG(ec));
+                else if (MEM_ERROR(ec)) {
+                        u8 r4 = R4(ec);
+
+                        if (r4 >= 0x7)
+                                pr_cont(": %s error during data copyback.\n",
+                                        R4_MSG(ec));
+                        else if (r4 <= 0x1)
+                                pr_cont(": %s parity/ECC error during data "
+                                        "access from L2.\n", R4_MSG(ec));
+                        else
+                                goto wrong_bu_mce;
+                } else
+                        goto wrong_bu_mce;
+        } else
+                goto wrong_bu_mce;
+
+        return;
+
+wrong_bu_mce:
+        pr_emerg(HW_ERR "Corrupted BU MCE info?\n");
+}
+
+static void amd_decode_cu_mce(struct mce *m)
+{
+        u16 ec = EC(m->status);
+        u8 xec = XEC(m->status, xec_mask);
+
+        pr_emerg(HW_ERR "Combined Unit Error: ");
+
+        if (TLB_ERROR(ec)) {
+                if (xec == 0x0)
+                        pr_cont("Data parity TLB read error.\n");
+                else if (xec == 0x1)
+                        pr_cont("Poison data provided for TLB fill.\n");
+                else
+                        goto wrong_cu_mce;
+        } else if (BUS_ERROR(ec)) {
+                if (xec > 2)
+                        goto wrong_cu_mce;
+
+                pr_cont("Error during attempted NB data read.\n");
+        } else if (MEM_ERROR(ec)) {
+                switch (xec) {
+                case 0x4 ... 0xc:
+                        pr_cont("%s.\n", f15h_cu_mce_desc[xec - 0x4]);
+                        break;
+
+                case 0x10 ... 0x14:
+                        pr_cont("%s.\n", f15h_cu_mce_desc[xec - 0x7]);
+                        break;
+
+                default:
+                        goto wrong_cu_mce;
+                }
+        }
+
+        return;
+
+wrong_cu_mce:
+        pr_emerg(HW_ERR "Corrupted CU MCE info?\n");
+}
+
+static void amd_decode_ls_mce(struct mce *m)
+{
+        u16 ec = EC(m->status);
+        u8 xec = XEC(m->status, xec_mask);
+
+        if (boot_cpu_data.x86 >= 0x14) {
+                pr_emerg("You shouldn't be seeing an LS MCE on this cpu family,"
+                         " please report on LKML.\n");
+                return;
+        }
+
+        pr_emerg(HW_ERR "Load Store Error");
+
+        if (xec == 0x0) {
+                u8 r4 = R4(ec);
+
+                if (!BUS_ERROR(ec) || (r4 != R4_DRD && r4 != R4_DWR))
+                        goto wrong_ls_mce;
+
+                pr_cont(" during %s.\n", R4_MSG(ec));
+        } else
+                goto wrong_ls_mce;
+
+        return;
+
+wrong_ls_mce:
+        pr_emerg(HW_ERR "Corrupted LS MCE info?\n");
+}
+
+static bool k8_nb_mce(u16 ec, u8 xec)
+{
+        bool ret = true;
+
+        switch (xec) {
+        case 0x1:
+                pr_cont("CRC error detected on HT link.\n");
+                break;
+
+        case 0x5:
+                pr_cont("Invalid GART PTE entry during GART table walk.\n");
+                break;
+
+        case 0x6:
+                pr_cont("Unsupported atomic RMW received from an IO link.\n");
+                break;
+
+        case 0x0:
+        case 0x8:
+                if (boot_cpu_data.x86 == 0x11)
+                        return false;
+
+                pr_cont("DRAM ECC error detected on the NB.\n");
+                break;
+
+        case 0xd:
+                pr_cont("Parity error on the DRAM addr/ctl signals.\n");
+                break;
+
+        default:
+                ret = false;
+                break;
+        }
+
+        return ret;
+}
+
+static bool f10h_nb_mce(u16 ec, u8 xec)
+{
+        bool ret = true;
+        u8 offset = 0;
+
+        if (k8_nb_mce(ec, xec))
+                return true;
+
+        switch(xec) {
+        case 0xa ... 0xc:
+                offset = 10;
+                break;
+
+        case 0xe:
+                offset = 11;
+                break;
+
+        case 0xf:
+                if (TLB_ERROR(ec))
+                        pr_cont("GART Table Walk data error.\n");
+                else if (BUS_ERROR(ec))
+                        pr_cont("DMA Exclusion Vector Table Walk error.\n");
+                else
+                        ret = false;
+
+                goto out;
+                break;
+
+        case 0x19:
+                if (boot_cpu_data.x86 == 0x15)
+                        pr_cont("Compute Unit Data Error.\n");
+                else
+                        ret = false;
+
+                goto out;
+                break;
+
+        case 0x1c ... 0x1f:
+                offset = 24;
+                break;
+
+        default:
+                ret = false;
+
+                goto out;
+                break;
+        }
+
+        pr_cont("%s.\n", f10h_nb_mce_desc[xec - offset]);
+
+out:
+        return ret;
+}
+
+static bool nb_noop_mce(u16 ec, u8 xec)
+{
+        return false;
+}
+
+void amd_decode_nb_mce(int node_id, struct mce *m, u32 nbcfg)
+{
+        struct cpuinfo_x86 *c = &boot_cpu_data;
+        u16 ec   = EC(m->status);
+        u8 xec   = XEC(m->status, 0x1f);
+        u32 nbsh = (u32)(m->status >> 32);
+        int core = -1;
+
+        pr_emerg(HW_ERR "Northbridge Error (node %d", node_id);
+
+        /* F10h, revD can disable ErrCpu[3:0] through ErrCpuVal */
+        if (c->x86 == 0x10 && c->x86_model > 7) {
+                if (nbsh & NBSH_ERR_CPU_VAL)
+                        core = nbsh & nb_err_cpumask;
+        } else {
+                u8 assoc_cpus = nbsh & nb_err_cpumask;
+
+                if (assoc_cpus > 0)
+                        core = fls(assoc_cpus) - 1;
+        }
+
+        if (core >= 0)
+                pr_cont(", core %d): ", core);
+        else
+                pr_cont("): ");
+
+        switch (xec) {
+        case 0x2:
+                pr_cont("Sync error (sync packets on HT link detected).\n");
+                return;
+
+        case 0x3:
+                pr_cont("HT Master abort.\n");
+                return;
+
+        case 0x4:
+                pr_cont("HT Target abort.\n");
+                return;
+
+        case 0x7:
+                pr_cont("NB Watchdog timeout.\n");
+                return;
+
+        case 0x9:
+                pr_cont("SVM DMA Exclusion Vector error.\n");
+                return;
+
+        default:
+                break;
+        }
+
+        if (!fam_ops->nb_mce(ec, xec))
+                goto wrong_nb_mce;
+
+        if (c->x86 == 0xf || c->x86 == 0x10 || c->x86 == 0x15)
+                if ((xec == 0x8 || xec == 0x0) && nb_bus_decoder)
+                        nb_bus_decoder(node_id, m, nbcfg);
+
+        return;
+
+wrong_nb_mce:
+        pr_emerg(HW_ERR "Corrupted NB MCE info?\n");
+}
+EXPORT_SYMBOL_GPL(amd_decode_nb_mce);
+
+static void amd_decode_fr_mce(struct mce *m)
+{
+        struct cpuinfo_x86 *c = &boot_cpu_data;
+        u8 xec = XEC(m->status, xec_mask);
+
+        if (c->x86 == 0xf || c->x86 == 0x11)
+                goto wrong_fr_mce;
+
+        if (c->x86 != 0x15 && xec != 0x0)
+                goto wrong_fr_mce;
+
+        pr_emerg(HW_ERR "%s Error: ",
+                 (c->x86 == 0x15 ? "Execution Unit" : "FIROB"));
+
+        if (xec == 0x0 || xec == 0xc)
+                pr_cont("%s.\n", fr_ex_mce_desc[xec]);
+        else if (xec < 0xd)
+                pr_cont("%s parity error.\n", fr_ex_mce_desc[xec]);
+        else
+                goto wrong_fr_mce;
+
+        return;
+
+wrong_fr_mce:
+        pr_emerg(HW_ERR "Corrupted FR MCE info?\n");
+}
+
+static void amd_decode_fp_mce(struct mce *m)
+{
+        u8 xec = XEC(m->status, xec_mask);
+
+        pr_emerg(HW_ERR "Floating Point Unit Error: ");
+
+        switch (xec) {
+        case 0x1:
+                pr_cont("Free List");
+                break;
+
+        case 0x2:
+                pr_cont("Physical Register File");
+                break;
+
+        case 0x3:
+                pr_cont("Retire Queue");
+                break;
+
+        case 0x4:
+                pr_cont("Scheduler table");
+                break;
+
+        case 0x5:
+                pr_cont("Status Register File");
+                break;
+
+        default:
+                goto wrong_fp_mce;
+                break;
+        }
+
+        pr_cont(" parity error.\n");
+
+        return;
+
+wrong_fp_mce:
+        pr_emerg(HW_ERR "Corrupted FP MCE info?\n");
+}
+
+static inline void amd_decode_err_code(u16 ec)
+{
+
+        pr_emerg(HW_ERR "cache level: %s", LL_MSG(ec));
+
+        if (BUS_ERROR(ec))
+                pr_cont(", mem/io: %s", II_MSG(ec));
+        else
+                pr_cont(", tx: %s", TT_MSG(ec));
+
+        if (MEM_ERROR(ec) || BUS_ERROR(ec)) {
+                pr_cont(", mem-tx: %s", R4_MSG(ec));
+
+                if (BUS_ERROR(ec))
+                        pr_cont(", part-proc: %s (%s)", PP_MSG(ec), TO_MSG(ec));
+        }
+
+        pr_cont("\n");
+}
+
+/*
+ * Filter out unwanted MCE signatures here.
+ */
+static bool amd_filter_mce(struct mce *m)
+{
+        u8 xec = (m->status >> 16) & 0x1f;
+
+        /*
+         * NB GART TLB error reporting is disabled by default.
+         */
+        if (m->bank == 4 && xec == 0x5 && !report_gart_errors)
+                return true;
+
+        return false;
+}
+
+int amd_decode_mce(struct notifier_block *nb, unsigned long val, void *data)
+{
+        struct mce *m = (struct mce *)data;
+        struct cpuinfo_x86 *c = &boot_cpu_data;
+        int node, ecc;
+
+        if (amd_filter_mce(m))
+                return NOTIFY_STOP;
+
+        pr_emerg(HW_ERR "MC%d_STATUS[%s|%s|%s|%s|%s",
+                m->bank,
+                ((m->status & MCI_STATUS_OVER)  ? "Over"  : "-"),
+                ((m->status & MCI_STATUS_UC)    ? "UE"    : "CE"),
+                ((m->status & MCI_STATUS_MISCV) ? "MiscV" : "-"),
+                ((m->status & MCI_STATUS_PCC)   ? "PCC"   : "-"),
+                ((m->status & MCI_STATUS_ADDRV) ? "AddrV" : "-"));
+
+        if (c->x86 == 0x15)
+                pr_cont("|%s|%s",
+                        ((m->status & BIT_64(44)) ? "Deferred" : "-"),
+                        ((m->status & BIT_64(43)) ? "Poison"   : "-"));
+
+        /* do the two bits[14:13] together */
+        ecc = (m->status >> 45) & 0x3;
+        if (ecc)
+                pr_cont("|%sECC", ((ecc == 2) ? "C" : "U"));
+
+        pr_cont("]: 0x%016llx\n", m->status);
+
+
+        switch (m->bank) {
+        case 0:
+                amd_decode_dc_mce(m);
+                break;
+
+        case 1:
+                amd_decode_ic_mce(m);
+                break;
+
+        case 2:
+                if (c->x86 == 0x15)
+                        amd_decode_cu_mce(m);
+                else
+                        amd_decode_bu_mce(m);
+                break;
+
+        case 3:
+                amd_decode_ls_mce(m);
+                break;
+
+        case 4:
+                node = amd_get_nb_id(m->extcpu);
+                amd_decode_nb_mce(node, m, 0);
+                break;
+
+        case 5:
+                amd_decode_fr_mce(m);
+                break;
+
+        case 6:
+                amd_decode_fp_mce(m);
+                break;
+
+        default:
+                break;
+        }
+
+        amd_decode_err_code(m->status & 0xffff);
+
+        return NOTIFY_STOP;
+}
+EXPORT_SYMBOL_GPL(amd_decode_mce);
+
+static struct notifier_block amd_mce_dec_nb = {
+        .notifier_call  = amd_decode_mce,
+};
+
+static int __init mce_amd_init(void)
+{
+        struct cpuinfo_x86 *c = &boot_cpu_data;
+
+        if (c->x86_vendor != X86_VENDOR_AMD)
+                return 0;
+
+        if ((c->x86 < 0xf || c->x86 > 0x12) &&
+            (c->x86 != 0x14 || c->x86_model > 0xf) &&
+            (c->x86 != 0x15 || c->x86_model > 0xf))
+                return 0;
+
+        fam_ops = kzalloc(sizeof(struct amd_decoder_ops), GFP_KERNEL);
+        if (!fam_ops)
+                return -ENOMEM;
+
+        switch (c->x86) {
+        case 0xf:
+                fam_ops->dc_mce = k8_dc_mce;
+                fam_ops->ic_mce = k8_ic_mce;
+                fam_ops->nb_mce = k8_nb_mce;
+                break;
+
+        case 0x10:
+                fam_ops->dc_mce = f10h_dc_mce;
+                fam_ops->ic_mce = k8_ic_mce;
+                fam_ops->nb_mce = f10h_nb_mce;
+                break;
+
+        case 0x11:
+                fam_ops->dc_mce = k8_dc_mce;
+                fam_ops->ic_mce = k8_ic_mce;
+                fam_ops->nb_mce = f10h_nb_mce;
+                break;
+
+        case 0x12:
+                fam_ops->dc_mce = f12h_dc_mce;
+                fam_ops->ic_mce = k8_ic_mce;
+                fam_ops->nb_mce = nb_noop_mce;
+                break;
+
+        case 0x14:
+                nb_err_cpumask  = 0x3;
+                fam_ops->dc_mce = f14h_dc_mce;
+                fam_ops->ic_mce = f14h_ic_mce;
+                fam_ops->nb_mce = nb_noop_mce;
+                break;
+
+        case 0x15:
+                xec_mask = 0x1f;
+                fam_ops->dc_mce = f15h_dc_mce;
+                fam_ops->ic_mce = f15h_ic_mce;
+                fam_ops->nb_mce = f10h_nb_mce;
+                break;
+
+        default:
+                printk(KERN_WARNING "Huh? What family is that: %d?!\n", c->x86);
+                kfree(fam_ops);
+                return -EINVAL;
+        }
+
+        pr_info("MCE: In-kernel MCE decoding enabled.\n");
+
+        atomic_notifier_chain_register(&x86_mce_decoder_chain, &amd_mce_dec_nb);
+
+        return 0;
+}
+early_initcall(mce_amd_init);
+
+#ifdef MODULE
+static void __exit mce_amd_exit(void)
+{
+        atomic_notifier_chain_unregister(&x86_mce_decoder_chain, &amd_mce_dec_nb);
+        kfree(fam_ops);
+}
+
+MODULE_DESCRIPTION("AMD MCE decoder");
+MODULE_ALIAS("edac-mce-amd");
+MODULE_LICENSE("GPL");
+module_exit(mce_amd_exit);
+#endif
diff --git a/drivers/edac/mce_amd.h b/drivers/edac/mce_amd.h
new file mode 100644
index 000000000000..795a3206acf5
--- /dev/null
+++ b/drivers/edac/mce_amd.h
@@ -0,0 +1,94 @@
+#ifndef _EDAC_MCE_AMD_H
+#define _EDAC_MCE_AMD_H
+
+#include <linux/notifier.h>
+
+#include <asm/mce.h>
+
+#define BIT_64(n)                       (U64_C(1) << (n))
+
+#define EC(x)                           ((x) & 0xffff)
+#define XEC(x, mask)                    (((x) >> 16) & mask)
+
+#define LOW_SYNDROME(x)                 (((x) >> 15) & 0xff)
+#define HIGH_SYNDROME(x)                (((x) >> 24) & 0xff)
+
+#define TLB_ERROR(x)                    (((x) & 0xFFF0) == 0x0010)
+#define MEM_ERROR(x)                    (((x) & 0xFF00) == 0x0100)
+#define BUS_ERROR(x)                    (((x) & 0xF800) == 0x0800)
+
+#define TT(x)                           (((x) >> 2) & 0x3)
+#define TT_MSG(x)                       tt_msgs[TT(x)]
+#define II(x)                           (((x) >> 2) & 0x3)
+#define II_MSG(x)                       ii_msgs[II(x)]
+#define LL(x)                           ((x) & 0x3)
+#define LL_MSG(x)                       ll_msgs[LL(x)]
+#define TO(x)                           (((x) >> 8) & 0x1)
+#define TO_MSG(x)                       to_msgs[TO(x)]
+#define PP(x)                           (((x) >> 9) & 0x3)
+#define PP_MSG(x)                       pp_msgs[PP(x)]
+
+#define R4(x)                           (((x) >> 4) & 0xf)
+#define R4_MSG(x)                       ((R4(x) < 9) ?  rrrr_msgs[R4(x)] : "Wrong R4!")
+
+/*
+ * F3x4C bits (MCi_STATUS' high half)
+ */
+#define NBSH_ERR_CPU_VAL                BIT(24)
+
+enum tt_ids {
+        TT_INSTR = 0,
+        TT_DATA,
+        TT_GEN,
+        TT_RESV,
+};
+
+enum ll_ids {
+        LL_RESV = 0,
+        LL_L1,
+        LL_L2,
+        LL_LG,
+};
+
+enum ii_ids {
+        II_MEM = 0,
+        II_RESV,
+        II_IO,
+        II_GEN,
+};
+
+enum rrrr_ids {
+        R4_GEN  = 0,
+        R4_RD,
+        R4_WR,
+        R4_DRD,
+        R4_DWR,
+        R4_IRD,
+        R4_PREF,
+        R4_EVICT,
+        R4_SNOOP,
+};
+
+extern const char *tt_msgs[];
+extern const char *ll_msgs[];
+extern const char *rrrr_msgs[];
+extern const char *pp_msgs[];
+extern const char *to_msgs[];
+extern const char *ii_msgs[];
+
+/*
+ * per-family decoder ops
+ */
+struct amd_decoder_ops {
+        bool (*dc_mce)(u16, u8);
+        bool (*ic_mce)(u16, u8);
+        bool (*nb_mce)(u16, u8);
+};
+
+void amd_report_gart_errors(bool);
+void amd_register_ecc_decoder(void (*f)(int, struct mce *, u32));
+void amd_unregister_ecc_decoder(void (*f)(int, struct mce *, u32));
+void amd_decode_nb_mce(int, struct mce *, u32);
+int amd_decode_mce(struct notifier_block *nb, unsigned long val, void *data);
+
+#endif /* _EDAC_MCE_AMD_H */
diff --git a/drivers/edac/mce_amd_inj.c b/drivers/edac/mce_amd_inj.c
new file mode 100644
index 000000000000..a4987e03f59e
--- /dev/null
+++ b/drivers/edac/mce_amd_inj.c
@@ -0,0 +1,172 @@
+/*
+ * A simple MCE injection facility for testing the MCE decoding code. This
+ * driver should be built as module so that it can be loaded on production
+ * kernels for testing purposes.
+ *
+ * This file may be distributed under the terms of the GNU General Public
+ * License version 2.
+ *
+ * Copyright (c) 2010:  Borislav Petkov <borislav.petkov@amd.com>
+ *                      Advanced Micro Devices Inc.
+ */
+
+#include <linux/kobject.h>
+#include <linux/sysdev.h>
+#include <linux/edac.h>
+#include <asm/mce.h>
+
+#include "mce_amd.h"
+
+struct edac_mce_attr {
+        struct attribute attr;
+        ssize_t (*show) (struct kobject *kobj, struct edac_mce_attr *attr, char *buf);
+        ssize_t (*store)(struct kobject *kobj, struct edac_mce_attr *attr,
+                         const char *buf, size_t count);
+};
+
+#define EDAC_MCE_ATTR(_name, _mode, _show, _store)                      \
+static struct edac_mce_attr mce_attr_##_name = __ATTR(_name, _mode, _show, _store)
+
+static struct kobject *mce_kobj;
+
+/*
+ * Collect all the MCi_XXX settings
+ */
+static struct mce i_mce;
+
+#define MCE_INJECT_STORE(reg)                                           \
+static ssize_t edac_inject_##reg##_store(struct kobject *kobj,          \
+                                         struct edac_mce_attr *attr,    \
+                                         const char *data, size_t count)\
+{                                                                       \
+        int ret = 0;                                                    \
+        unsigned long value;                                            \
+                                                                        \
+        ret = strict_strtoul(data, 16, &value);                         \
+        if (ret < 0)                                                    \
+                printk(KERN_ERR "Error writing MCE " #reg " field.\n"); \
+                                                                        \
+        i_mce.reg = value;                                              \
+                                                                        \
+        return count;                                                   \
+}
+
+MCE_INJECT_STORE(status);
+MCE_INJECT_STORE(misc);
+MCE_INJECT_STORE(addr);
+
+#define MCE_INJECT_SHOW(reg)                                            \
+static ssize_t edac_inject_##reg##_show(struct kobject *kobj,           \
+                                        struct edac_mce_attr *attr,     \
+                                        char *buf)                      \
+{                                                                       \
+        return sprintf(buf, "0x%016llx\n", i_mce.reg);                  \
+}
+
+MCE_INJECT_SHOW(status);
+MCE_INJECT_SHOW(misc);
+MCE_INJECT_SHOW(addr);
+
+EDAC_MCE_ATTR(status, 0644, edac_inject_status_show, edac_inject_status_store);
+EDAC_MCE_ATTR(misc, 0644, edac_inject_misc_show, edac_inject_misc_store);
+EDAC_MCE_ATTR(addr, 0644, edac_inject_addr_show, edac_inject_addr_store);
+
+/*
+ * This denotes into which bank we're injecting and triggers
+ * the injection, at the same time.
+ */
+static ssize_t edac_inject_bank_store(struct kobject *kobj,
+                                      struct edac_mce_attr *attr,
+                                      const char *data, size_t count)
+{
+        int ret = 0;
+        unsigned long value;
+
+        ret = strict_strtoul(data, 10, &value);
+        if (ret < 0) {
+                printk(KERN_ERR "Invalid bank value!\n");
+                return -EINVAL;
+        }
+
+        if (value > 5)
+                if (boot_cpu_data.x86 != 0x15 || value > 6) {
+                        printk(KERN_ERR "Non-existent MCE bank: %lu\n", value);
+                        return -EINVAL;
+                }
+
+        i_mce.bank = value;
+
+        amd_decode_mce(NULL, 0, &i_mce);
+
+        return count;
+}
+
+static ssize_t edac_inject_bank_show(struct kobject *kobj,
+                                     struct edac_mce_attr *attr, char *buf)
+{
+        return sprintf(buf, "%d\n", i_mce.bank);
+}
+
+EDAC_MCE_ATTR(bank, 0644, edac_inject_bank_show, edac_inject_bank_store);
+
+static struct edac_mce_attr *sysfs_attrs[] = { &mce_attr_status, &mce_attr_misc,
+                                               &mce_attr_addr, &mce_attr_bank
+};
+
+static int __init edac_init_mce_inject(void)
+{
+        struct sysdev_class *edac_class = NULL;
+        int i, err = 0;
+
+        edac_class = edac_get_sysfs_class();
+        if (!edac_class)
+                return -EINVAL;
+
+        mce_kobj = kobject_create_and_add("mce", &edac_class->kset.kobj);
+        if (!mce_kobj) {
+                printk(KERN_ERR "Error creating a mce kset.\n");
+                err = -ENOMEM;
+                goto err_mce_kobj;
+        }
+
+        for (i = 0; i < ARRAY_SIZE(sysfs_attrs); i++) {
+                err = sysfs_create_file(mce_kobj, &sysfs_attrs[i]->attr);
+                if (err) {
+                        printk(KERN_ERR "Error creating %s in sysfs.\n",
+                                        sysfs_attrs[i]->attr.name);
+                        goto err_sysfs_create;
+                }
+        }
+        return 0;
+
+err_sysfs_create:
+        while (--i >= 0)
+                sysfs_remove_file(mce_kobj, &sysfs_attrs[i]->attr);
+
+        kobject_del(mce_kobj);
+
+err_mce_kobj:
+        edac_put_sysfs_class();
+
+        return err;
+}
+
+static void __exit edac_exit_mce_inject(void)
+{
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(sysfs_attrs); i++)
+                sysfs_remove_file(mce_kobj, &sysfs_attrs[i]->attr);
+
+        kobject_del(mce_kobj);
+
+        edac_put_sysfs_class();
+}
+
+module_init(edac_init_mce_inject);
+module_exit(edac_exit_mce_inject);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Borislav Petkov <borislav.petkov@amd.com>");
+MODULE_AUTHOR("AMD Inc.");
+MODULE_DESCRIPTION("MCE injection facility for testing MCE decoding");
diff --git a/drivers/edac/mpc85xx_edac.c b/drivers/edac/mpc85xx_edac.c
index b123bb308a4a..38ab8e2cd7f4 100644
--- a/drivers/edac/mpc85xx_edac.c
+++ b/drivers/edac/mpc85xx_edac.c
@@ -200,8 +200,7 @@ static irqreturn_t mpc85xx_pci_isr(int irq, void *dev_id)
         return IRQ_HANDLED;
 }
 
-static int __devinit mpc85xx_pci_err_probe(struct platform_device *op,
-                                           const struct of_device_id *match)
+static int __devinit mpc85xx_pci_err_probe(struct platform_device *op)
 {
         struct edac_pci_ctl_info *pci;
         struct mpc85xx_pci_pdata *pdata;
@@ -338,7 +337,7 @@ static struct of_device_id mpc85xx_pci_err_of_match[] = {
 };
 MODULE_DEVICE_TABLE(of, mpc85xx_pci_err_of_match);
 
-static struct of_platform_driver mpc85xx_pci_err_driver = {
+static struct platform_driver mpc85xx_pci_err_driver = {
         .probe = mpc85xx_pci_err_probe,
         .remove = __devexit_p(mpc85xx_pci_err_remove),
         .driver = {
@@ -503,8 +502,7 @@ static irqreturn_t mpc85xx_l2_isr(int irq, void *dev_id)
         return IRQ_HANDLED;
 }
 
-static int __devinit mpc85xx_l2_err_probe(struct platform_device *op,
-                                          const struct of_device_id *match)
+static int __devinit mpc85xx_l2_err_probe(struct platform_device *op)
 {
         struct edac_device_ctl_info *edac_dev;
         struct mpc85xx_l2_pdata *pdata;
@@ -656,7 +654,7 @@ static struct of_device_id mpc85xx_l2_err_of_match[] = {
 };
 MODULE_DEVICE_TABLE(of, mpc85xx_l2_err_of_match);
 
-static struct of_platform_driver mpc85xx_l2_err_driver = {
+static struct platform_driver mpc85xx_l2_err_driver = {
         .probe = mpc85xx_l2_err_probe,
         .remove = mpc85xx_l2_err_remove,
         .driver = {
@@ -956,8 +954,7 @@ static void __devinit mpc85xx_init_csrows(struct mem_ctl_info *mci)
         }
 }
 
-static int __devinit mpc85xx_mc_err_probe(struct platform_device *op,
-                                          const struct of_device_id *match)
+static int __devinit mpc85xx_mc_err_probe(struct platform_device *op)
 {
         struct mem_ctl_info *mci;
         struct mpc85xx_mc_pdata *pdata;
@@ -1136,7 +1133,7 @@ static struct of_device_id mpc85xx_mc_err_of_match[] = {
 };
 MODULE_DEVICE_TABLE(of, mpc85xx_mc_err_of_match);
 
-static struct of_platform_driver mpc85xx_mc_err_driver = {
+static struct platform_driver mpc85xx_mc_err_driver = {
         .probe = mpc85xx_mc_err_probe,
         .remove = mpc85xx_mc_err_remove,
         .driver = {
@@ -1150,13 +1147,14 @@ static struct of_platform_driver mpc85xx_mc_err_driver = {
 static void __init mpc85xx_mc_clear_rfxe(void *data)
 {
         orig_hid1[smp_processor_id()] = mfspr(SPRN_HID1);
-        mtspr(SPRN_HID1, (orig_hid1[smp_processor_id()] & ~0x20000));
+        mtspr(SPRN_HID1, (orig_hid1[smp_processor_id()] & ~HID1_RFXE));
 }
 #endif
 
 static int __init mpc85xx_mc_init(void)
 {
         int res = 0;
+        u32 pvr = 0;
 
         printk(KERN_INFO "Freescale(R) MPC85xx EDAC driver, "
                "(C) 2006 Montavista Software\n");
@@ -1171,27 +1169,32 @@ static int __init mpc85xx_mc_init(void)
                 break;
         }
 
-        res = of_register_platform_driver(&mpc85xx_mc_err_driver);
+        res = platform_driver_register(&mpc85xx_mc_err_driver);
         if (res)
                 printk(KERN_WARNING EDAC_MOD_STR "MC fails to register\n");
 
-        res = of_register_platform_driver(&mpc85xx_l2_err_driver);
+        res = platform_driver_register(&mpc85xx_l2_err_driver);
         if (res)
                 printk(KERN_WARNING EDAC_MOD_STR "L2 fails to register\n");
 
 #ifdef CONFIG_PCI
-        res = of_register_platform_driver(&mpc85xx_pci_err_driver);
+        res = platform_driver_register(&mpc85xx_pci_err_driver);
         if (res)
                 printk(KERN_WARNING EDAC_MOD_STR "PCI fails to register\n");
 #endif
 
 #ifdef CONFIG_FSL_SOC_BOOKE
-        /*
-         * need to clear HID1[RFXE] to disable machine check int
-         * so we can catch it
-         */
-        if (edac_op_state == EDAC_OPSTATE_INT)
-                on_each_cpu(mpc85xx_mc_clear_rfxe, NULL, 0);
+        pvr = mfspr(SPRN_PVR);
+
+        if ((PVR_VER(pvr) == PVR_VER_E500V1) ||
+            (PVR_VER(pvr) == PVR_VER_E500V2)) {
+                /*
+                 * need to clear HID1[RFXE] to disable machine check int
+                 * so we can catch it
+                 */
+                if (edac_op_state == EDAC_OPSTATE_INT)
+                        on_each_cpu(mpc85xx_mc_clear_rfxe, NULL, 0);
+        }
 #endif
 
         return 0;
@@ -1209,13 +1212,18 @@ static void __exit mpc85xx_mc_restore_hid1(void *data)
 static void __exit mpc85xx_mc_exit(void)
 {
 #ifdef CONFIG_FSL_SOC_BOOKE
-        on_each_cpu(mpc85xx_mc_restore_hid1, NULL, 0);
+        u32 pvr = mfspr(SPRN_PVR);
+
+        if ((PVR_VER(pvr) == PVR_VER_E500V1) ||
+            (PVR_VER(pvr) == PVR_VER_E500V2)) {
+                on_each_cpu(mpc85xx_mc_restore_hid1, NULL, 0);
+        }
 #endif
 #ifdef CONFIG_PCI
-        of_unregister_platform_driver(&mpc85xx_pci_err_driver);
+        platform_driver_unregister(&mpc85xx_pci_err_driver);
 #endif
-        of_unregister_platform_driver(&mpc85xx_l2_err_driver);
-        of_unregister_platform_driver(&mpc85xx_mc_err_driver);
+        platform_driver_unregister(&mpc85xx_l2_err_driver);
+        platform_driver_unregister(&mpc85xx_mc_err_driver);
 }
 
 module_exit(mpc85xx_mc_exit);
diff --git a/drivers/edac/mpc85xx_edac.h b/drivers/edac/mpc85xx_edac.h
index cb24df839460..932016f2cf06 100644
--- a/drivers/edac/mpc85xx_edac.h
+++ b/drivers/edac/mpc85xx_edac.h
@@ -11,7 +11,7 @@
 #ifndef _MPC85XX_EDAC_H_
 #define _MPC85XX_EDAC_H_
 
-#define MPC85XX_REVISION " Ver: 2.0.0 " __DATE__
+#define MPC85XX_REVISION " Ver: 2.0.0"
 #define EDAC_MOD_STR    "MPC85xx_edac"
 
 #define mpc85xx_printk(level, fmt, arg...) \
diff --git a/drivers/edac/mv64x60_edac.h b/drivers/edac/mv64x60_edac.h
index e042e2daa8f4..c7f209c92a1a 100644
--- a/drivers/edac/mv64x60_edac.h
+++ b/drivers/edac/mv64x60_edac.h
@@ -12,7 +12,7 @@
 #ifndef _MV64X60_EDAC_H_
 #define _MV64X60_EDAC_H_
 
-#define MV64x60_REVISION " Ver: 2.0.0 " __DATE__
+#define MV64x60_REVISION " Ver: 2.0.0"
 #define EDAC_MOD_STR    "MV64x60_edac"
 
 #define mv64x60_printk(level, fmt, arg...) \
diff --git a/drivers/edac/ppc4xx_edac.c b/drivers/edac/ppc4xx_edac.c
index 070cea41b661..0de7d8770891 100644
--- a/drivers/edac/ppc4xx_edac.c
+++ b/drivers/edac/ppc4xx_edac.c
@@ -113,7 +113,7 @@
 #define EDAC_OPSTATE_UNKNOWN_STR        "unknown"
 
 #define PPC4XX_EDAC_MODULE_NAME         "ppc4xx_edac"
-#define PPC4XX_EDAC_MODULE_REVISION     "v1.0.0 " __DATE__
+#define PPC4XX_EDAC_MODULE_REVISION     "v1.0.0"
 
 #define PPC4XX_EDAC_MESSAGE_SIZE        256
 
@@ -184,8 +184,7 @@ struct ppc4xx_ecc_status {
 
 /* Function Prototypes */
 
-static int ppc4xx_edac_probe(struct platform_device *device,
-                             const struct of_device_id *device_id);
+static int ppc4xx_edac_probe(struct platform_device *device)
 static int ppc4xx_edac_remove(struct platform_device *device);
 
 /* Global Variables */
@@ -201,7 +200,7 @@ static struct of_device_id ppc4xx_edac_match[] = {
         { }
 };
 
-static struct of_platform_driver ppc4xx_edac_driver = {
+static struct platform_driver ppc4xx_edac_driver = {
         .probe                  = ppc4xx_edac_probe,
         .remove                 = ppc4xx_edac_remove,
         .driver = {
@@ -873,7 +872,7 @@ ppc4xx_edac_get_mtype(u32 mcopt1)
 }
 
 /**
- * ppc4xx_edac_init_csrows - intialize driver instance rows
+ * ppc4xx_edac_init_csrows - initialize driver instance rows
  * @mci: A pointer to the EDAC memory controller instance
  *       associated with the ibm,sdram-4xx-ddr2 controller for which
  *       the csrows (i.e. banks/ranks) are being initialized.
@@ -881,7 +880,7 @@ ppc4xx_edac_get_mtype(u32 mcopt1)
  *          currently set for the controller, from which bank width
  *          and memory typ information is derived.
  *
- * This routine intializes the virtual "chip select rows" associated
+ * This routine initializes the virtual "chip select rows" associated
  * with the EDAC memory controller instance. An ibm,sdram-4xx-ddr2
  * controller bank/rank is mapped to a row.
  *
@@ -992,14 +991,11 @@ ppc4xx_edac_init_csrows(struct mem_ctl_info *mci, u32 mcopt1)
 }
 
 /**
- * ppc4xx_edac_mc_init - intialize driver instance
+ * ppc4xx_edac_mc_init - initialize driver instance
  * @mci: A pointer to the EDAC memory controller instance being
  *       initialized.
  * @op: A pointer to the OpenFirmware device tree node associated
  *      with the controller this EDAC instance is bound to.
- * @match: A pointer to the OpenFirmware device tree match
- *         information associated with the controller this EDAC instance
- *         is bound to.
  * @dcr_host: A pointer to the DCR data containing the DCR mapping
  *            for this controller instance.
  * @mcopt1: The 32-bit Memory Controller Option 1 register value
@@ -1015,7 +1011,6 @@ ppc4xx_edac_init_csrows(struct mem_ctl_info *mci, u32 mcopt1)
 static int __devinit
 ppc4xx_edac_mc_init(struct mem_ctl_info *mci,
                     struct platform_device *op,
-                    const struct of_device_id *match,
                     const dcr_host_t *dcr_host,
                     u32 mcopt1)
 {
@@ -1024,7 +1019,7 @@ ppc4xx_edac_mc_init(struct mem_ctl_info *mci,
         struct ppc4xx_edac_pdata *pdata = NULL;
         const struct device_node *np = op->dev.of_node;
 
-        if (match == NULL)
+        if (of_match_device(ppc4xx_edac_match, &op->dev) == NULL)
                 return -EINVAL;
 
         /* Initial driver pointers and private data */
@@ -1227,9 +1222,6 @@ ppc4xx_edac_map_dcrs(const struct device_node *np, dcr_host_t *dcr_host)
  * ppc4xx_edac_probe - check controller and bind driver
  * @op: A pointer to the OpenFirmware device tree node associated
  *      with the controller being probed for driver binding.
- * @match: A pointer to the OpenFirmware device tree match
- *         information associated with the controller being probed
- *         for driver binding.
  *
  * This routine probes a specific ibm,sdram-4xx-ddr2 controller
  * instance for binding with the driver.
@@ -1237,8 +1229,7 @@ ppc4xx_edac_map_dcrs(const struct device_node *np, dcr_host_t *dcr_host)
  * Returns 0 if the controller instance was successfully bound to the
  * driver; otherwise, < 0 on error.
  */
-static int __devinit
-ppc4xx_edac_probe(struct platform_device *op, const struct of_device_id *match)
+static int __devinit ppc4xx_edac_probe(struct platform_device *op)
 {
         int status = 0;
         u32 mcopt1, memcheck;
@@ -1304,7 +1295,7 @@ ppc4xx_edac_probe(struct platform_device *op, const struct of_device_id *match)
                 goto done;
         }
 
-        status = ppc4xx_edac_mc_init(mci, op, match, &dcr_host, mcopt1);
+        status = ppc4xx_edac_mc_init(mci, op, &dcr_host, mcopt1);
 
         if (status) {
                 ppc4xx_edac_mc_printk(KERN_ERR, mci,
@@ -1421,7 +1412,7 @@ ppc4xx_edac_init(void)
 
         ppc4xx_edac_opstate_init();
 
-        return of_register_platform_driver(&ppc4xx_edac_driver);
+        return platform_driver_register(&ppc4xx_edac_driver);
 }
 
 /**
@@ -1434,7 +1425,7 @@ ppc4xx_edac_init(void)
 static void __exit
 ppc4xx_edac_exit(void)
 {
-        of_unregister_platform_driver(&ppc4xx_edac_driver);
+        platform_driver_unregister(&ppc4xx_edac_driver);
 }
 
 module_init(ppc4xx_edac_init);
diff --git a/drivers/edac/r82600_edac.c b/drivers/edac/r82600_edac.c
index 6a822c631ef5..b153674431f1 100644
--- a/drivers/edac/r82600_edac.c
+++ b/drivers/edac/r82600_edac.c
@@ -22,7 +22,7 @@
 #include <linux/edac.h>
 #include "edac_core.h"
 
-#define R82600_REVISION " Ver: 2.0.2 " __DATE__
+#define R82600_REVISION " Ver: 2.0.2"
 #define EDAC_MOD_STR    "r82600_edac"
 
 #define r82600_printk(level, fmt, arg...) \
@@ -120,7 +120,7 @@
                                  *        write 0=NOP
                                  */
 
-#define R82600_DRBA     0x60    /* + 0x60..0x63 SDRAM Row Boundry Address
+#define R82600_DRBA     0x60    /* + 0x60..0x63 SDRAM Row Boundary Address
                                  *  Registers
                                  *
                                  * 7:0  Address lines 30:24 - upper limit of
@@ -217,7 +217,7 @@ static void r82600_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev,
 {
         struct csrow_info *csrow;
         int index;
-        u8 drbar;               /* SDRAM Row Boundry Address Register */
+        u8 drbar;               /* SDRAM Row Boundary Address Register */
         u32 row_high_limit, row_high_limit_last;
         u32 reg_sdram, ecc_on, row_base;
 
@@ -236,7 +236,7 @@ static void r82600_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev,
                 row_high_limit = ((u32) drbar << 24);
 /*              row_high_limit = ((u32)drbar << 24) | 0xffffffUL; */
 
-                debugf1("%s() Row=%d, Boundry Address=%#0x, Last = %#0x\n",
+                debugf1("%s() Row=%d, Boundary Address=%#0x, Last = %#0x\n",
                         __func__, index, row_high_limit, row_high_limit_last);
 
                 /* Empty row [p.57] */
diff --git a/drivers/edac/tile_edac.c b/drivers/edac/tile_edac.c
new file mode 100644
index 000000000000..1d5cf06f6c6b
--- /dev/null
+++ b/drivers/edac/tile_edac.c
@@ -0,0 +1,254 @@
+/*
+ * Copyright 2011 Tilera Corporation. All Rights Reserved.
+ *
+ *   This program is free software; you can redistribute it and/or
+ *   modify it under the terms of the GNU General Public License
+ *   as published by the Free Software Foundation, version 2.
+ *
+ *   This program is distributed in the hope that it will be useful, but
+ *   WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ *   NON INFRINGEMENT.  See the GNU General Public License for
+ *   more details.
+ * Tilera-specific EDAC driver.
+ *
+ * This source code is derived from the following driver:
+ *
+ * Cell MIC driver for ECC counting
+ *
+ * Copyright 2007 Benjamin Herrenschmidt, IBM Corp.
+ *                <benh@kernel.crashing.org>
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/uaccess.h>
+#include <linux/edac.h>
+#include <hv/hypervisor.h>
+#include <hv/drv_mshim_intf.h>
+
+#include "edac_core.h"
+
+#define DRV_NAME        "tile-edac"
+
+/* Number of cs_rows needed per memory controller on TILEPro. */
+#define TILE_EDAC_NR_CSROWS     1
+
+/* Number of channels per memory controller on TILEPro. */
+#define TILE_EDAC_NR_CHANS      1
+
+/* Granularity of reported error in bytes on TILEPro. */
+#define TILE_EDAC_ERROR_GRAIN   8
+
+/* TILE processor has multiple independent memory controllers. */
+struct platform_device *mshim_pdev[TILE_MAX_MSHIMS];
+
+struct tile_edac_priv {
+        int             hv_devhdl;      /* Hypervisor device handle. */
+        int             node;           /* Memory controller instance #. */
+        unsigned int    ce_count;       /*
+                                         * Correctable-error counter
+                                         * kept by the driver.
+                                         */
+};
+
+static void tile_edac_check(struct mem_ctl_info *mci)
+{
+        struct tile_edac_priv   *priv = mci->pvt_info;
+        struct mshim_mem_error  mem_error;
+
+        if (hv_dev_pread(priv->hv_devhdl, 0, (HV_VirtAddr)&mem_error,
+                sizeof(struct mshim_mem_error), MSHIM_MEM_ERROR_OFF) !=
+                sizeof(struct mshim_mem_error)) {
+                pr_err(DRV_NAME ": MSHIM_MEM_ERROR_OFF pread failure.\n");
+                return;
+        }
+
+        /* Check if the current error count is different from the saved one. */
+        if (mem_error.sbe_count != priv->ce_count) {
+                dev_dbg(mci->dev, "ECC CE err on node %d\n", priv->node);
+                priv->ce_count = mem_error.sbe_count;
+                edac_mc_handle_ce(mci, 0, 0, 0, 0, 0, mci->ctl_name);
+        }
+}
+
+/*
+ * Initialize the 'csrows' table within the mci control structure with the
+ * addressing of memory.
+ */
+static int __devinit tile_edac_init_csrows(struct mem_ctl_info *mci)
+{
+        struct csrow_info       *csrow = &mci->csrows[0];
+        struct tile_edac_priv   *priv = mci->pvt_info;
+        struct mshim_mem_info   mem_info;
+
+        if (hv_dev_pread(priv->hv_devhdl, 0, (HV_VirtAddr)&mem_info,
+                sizeof(struct mshim_mem_info), MSHIM_MEM_INFO_OFF) !=
+                sizeof(struct mshim_mem_info)) {
+                pr_err(DRV_NAME ": MSHIM_MEM_INFO_OFF pread failure.\n");
+                return -1;
+        }
+
+        if (mem_info.mem_ecc)
+                csrow->edac_mode = EDAC_SECDED;
+        else
+                csrow->edac_mode = EDAC_NONE;
+        switch (mem_info.mem_type) {
+        case DDR2:
+                csrow->mtype = MEM_DDR2;
+                break;
+
+        case DDR3:
+                csrow->mtype = MEM_DDR3;
+                break;
+
+        default:
+                return -1;
+        }
+
+        csrow->first_page = 0;
+        csrow->nr_pages = mem_info.mem_size >> PAGE_SHIFT;
+        csrow->last_page = csrow->first_page + csrow->nr_pages - 1;
+        csrow->grain = TILE_EDAC_ERROR_GRAIN;
+        csrow->dtype = DEV_UNKNOWN;
+
+        return 0;
+}
+
+static int __devinit tile_edac_mc_probe(struct platform_device *pdev)
+{
+        char                    hv_file[32];
+        int                     hv_devhdl;
+        struct mem_ctl_info     *mci;
+        struct tile_edac_priv   *priv;
+        int                     rc;
+
+        sprintf(hv_file, "mshim/%d", pdev->id);
+        hv_devhdl = hv_dev_open((HV_VirtAddr)hv_file, 0);
+        if (hv_devhdl < 0)
+                return -EINVAL;
+
+        /* A TILE MC has a single channel and one chip-select row. */
+        mci = edac_mc_alloc(sizeof(struct tile_edac_priv),
+                TILE_EDAC_NR_CSROWS, TILE_EDAC_NR_CHANS, pdev->id);
+        if (mci == NULL)
+                return -ENOMEM;
+        priv = mci->pvt_info;
+        priv->node = pdev->id;
+        priv->hv_devhdl = hv_devhdl;
+
+        mci->dev = &pdev->dev;
+        mci->mtype_cap = MEM_FLAG_DDR2;
+        mci->edac_ctl_cap = EDAC_FLAG_SECDED;
+
+        mci->mod_name = DRV_NAME;
+        mci->ctl_name = "TILEPro_Memory_Controller";
+        mci->dev_name = dev_name(&pdev->dev);
+        mci->edac_check = tile_edac_check;
+
+        /*
+         * Initialize the MC control structure 'csrows' table
+         * with the mapping and control information.
+         */
+        if (tile_edac_init_csrows(mci)) {
+                /* No csrows found. */
+                mci->edac_cap = EDAC_FLAG_NONE;
+        } else {
+                mci->edac_cap = EDAC_FLAG_SECDED;
+        }
+
+        platform_set_drvdata(pdev, mci);
+
+        /* Register with EDAC core */
+        rc = edac_mc_add_mc(mci);
+        if (rc) {
+                dev_err(&pdev->dev, "failed to register with EDAC core\n");
+                edac_mc_free(mci);
+                return rc;
+        }
+
+        return 0;
+}
+
+static int __devexit tile_edac_mc_remove(struct platform_device *pdev)
+{
+        struct mem_ctl_info *mci = platform_get_drvdata(pdev);
+
+        edac_mc_del_mc(&pdev->dev);
+        if (mci)
+                edac_mc_free(mci);
+        return 0;
+}
+
+static struct platform_driver tile_edac_mc_driver = {
+        .driver         = {
+                .name   = DRV_NAME,
+                .owner  = THIS_MODULE,
+        },
+        .probe          = tile_edac_mc_probe,
+        .remove         = __devexit_p(tile_edac_mc_remove),
+};
+
+/*
+ * Driver init routine.
+ */
+static int __init tile_edac_init(void)
+{
+        char    hv_file[32];
+        struct platform_device *pdev;
+        int i, err, num = 0;
+
+        /* Only support POLL mode. */
+        edac_op_state = EDAC_OPSTATE_POLL;
+
+        err = platform_driver_register(&tile_edac_mc_driver);
+        if (err)
+                return err;
+
+        for (i = 0; i < TILE_MAX_MSHIMS; i++) {
+                /*
+                 * Not all memory controllers are configured such as in the
+                 * case of a simulator. So we register only those mshims
+                 * that are configured by the hypervisor.
+                 */
+                sprintf(hv_file, "mshim/%d", i);
+                if (hv_dev_open((HV_VirtAddr)hv_file, 0) < 0)
+                        continue;
+
+                pdev = platform_device_register_simple(DRV_NAME, i, NULL, 0);
+                if (IS_ERR(pdev))
+                        continue;
+                mshim_pdev[i] = pdev;
+                num++;
+        }
+
+        if (num == 0) {
+                platform_driver_unregister(&tile_edac_mc_driver);
+                return -ENODEV;
+        }
+        return 0;
+}
+
+/*
+ * Driver cleanup routine.
+ */
+static void __exit tile_edac_exit(void)
+{
+        int i;
+
+        for (i = 0; i < TILE_MAX_MSHIMS; i++) {
+                struct platform_device *pdev = mshim_pdev[i];
+                if (!pdev)
+                        continue;
+
+                platform_set_drvdata(pdev, NULL);
+                platform_device_unregister(pdev);
+        }
+        platform_driver_unregister(&tile_edac_mc_driver);
+}
+
+module_init(tile_edac_init);
+module_exit(tile_edac_exit);