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authorMauro Carvalho Chehab <mchehab@redhat.com>2013-01-10 11:31:43 -0500
committerMauro Carvalho Chehab <mchehab@redhat.com>2013-02-21 09:06:22 -0500
commit5f466cb0257998549058c16e9d44bb74804a273d (patch)
tree536824f929bc546ae0a9d0946ff52c4fc8a79919 /drivers/edac/i3200_edac.c
parent1339730e73f14673ad55bddda119982504633da9 (diff)
i3200_edac: Add more debug to the driver
Currently, it is not possible to know, when debug is enabled, if the driver is using 2 DIMMS per channel mode or not. It is not possible to know the values of the drbs registers, used to identify the memory rank sizes. Add debug for both, as it helps to track issues on the driver. Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'drivers/edac/i3200_edac.c')
-rw-r--r--drivers/edac/i3200_edac.c16
1 files changed, 14 insertions, 2 deletions
diff --git a/drivers/edac/i3200_edac.c b/drivers/edac/i3200_edac.c
index 4e8337602e78..20641925d313 100644
--- a/drivers/edac/i3200_edac.c
+++ b/drivers/edac/i3200_edac.c
@@ -106,16 +106,26 @@ static int nr_channels;
106 106
107static int how_many_channels(struct pci_dev *pdev) 107static int how_many_channels(struct pci_dev *pdev)
108{ 108{
109 int n_channels;
110
109 unsigned char capid0_8b; /* 8th byte of CAPID0 */ 111 unsigned char capid0_8b; /* 8th byte of CAPID0 */
110 112
111 pci_read_config_byte(pdev, I3200_CAPID0 + 8, &capid0_8b); 113 pci_read_config_byte(pdev, I3200_CAPID0 + 8, &capid0_8b);
114
112 if (capid0_8b & 0x20) { /* check DCD: Dual Channel Disable */ 115 if (capid0_8b & 0x20) { /* check DCD: Dual Channel Disable */
113 edac_dbg(0, "In single channel mode\n"); 116 edac_dbg(0, "In single channel mode\n");
114 return 1; 117 n_channels = 1;
115 } else { 118 } else {
116 edac_dbg(0, "In dual channel mode\n"); 119 edac_dbg(0, "In dual channel mode\n");
117 return 2; 120 n_channels = 2;
118 } 121 }
122
123 if (capid0_8b & 0x10) /* check if both channels are filled */
124 edac_dbg(0, "2 DIMMS per channel disabled\n");
125 else
126 edac_dbg(0, "2 DIMMS per channel enabled\n");
127
128 return n_channels;
119} 129}
120 130
121static unsigned long eccerrlog_syndrome(u64 log) 131static unsigned long eccerrlog_syndrome(u64 log)
@@ -290,6 +300,8 @@ static void i3200_get_drbs(void __iomem *window,
290 for (i = 0; i < I3200_RANKS_PER_CHANNEL; i++) { 300 for (i = 0; i < I3200_RANKS_PER_CHANNEL; i++) {
291 drbs[0][i] = readw(window + I3200_C0DRB + 2*i) & I3200_DRB_MASK; 301 drbs[0][i] = readw(window + I3200_C0DRB + 2*i) & I3200_DRB_MASK;
292 drbs[1][i] = readw(window + I3200_C1DRB + 2*i) & I3200_DRB_MASK; 302 drbs[1][i] = readw(window + I3200_C1DRB + 2*i) & I3200_DRB_MASK;
303
304 edac_dbg(0, "drb[0][%d] = %d, drb[1][%d] = %d\n", i, drbs[0][i], i, drbs[1][i]);
293 } 305 }
294} 306}
295 307