diff options
author | Dave Peterson <dsp@llnl.gov> | 2006-03-26 04:38:52 -0500 |
---|---|---|
committer | Linus Torvalds <torvalds@g5.osdl.org> | 2006-03-26 11:57:08 -0500 |
commit | e7ecd8910293564d357dbaf18eb179e06fa35fd0 (patch) | |
tree | 7ec33cd42783cc53dd3ce161802d1032cea869a7 /drivers/edac/amd76x_edac.c | |
parent | 54933dddc3e8ccd9db48966d8ada11951cb8a558 (diff) |
[PATCH] EDAC: formatting cleanup
Cosmetic indentation/formatting cleanup for EDAC code. Make sure we
are using tabs rather than spaces to indent, etc.
Signed-off-by: David S. Peterson <dsp@llnl.gov>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'drivers/edac/amd76x_edac.c')
-rw-r--r-- | drivers/edac/amd76x_edac.c | 91 |
1 files changed, 36 insertions, 55 deletions
diff --git a/drivers/edac/amd76x_edac.c b/drivers/edac/amd76x_edac.c index 87bd8b4d561f..53423ad6d4a3 100644 --- a/drivers/edac/amd76x_edac.c +++ b/drivers/edac/amd76x_edac.c | |||
@@ -12,33 +12,26 @@ | |||
12 | * | 12 | * |
13 | */ | 13 | */ |
14 | 14 | ||
15 | |||
16 | #include <linux/config.h> | 15 | #include <linux/config.h> |
17 | #include <linux/module.h> | 16 | #include <linux/module.h> |
18 | #include <linux/init.h> | 17 | #include <linux/init.h> |
19 | |||
20 | #include <linux/pci.h> | 18 | #include <linux/pci.h> |
21 | #include <linux/pci_ids.h> | 19 | #include <linux/pci_ids.h> |
22 | |||
23 | #include <linux/slab.h> | 20 | #include <linux/slab.h> |
24 | |||
25 | #include "edac_mc.h" | 21 | #include "edac_mc.h" |
26 | 22 | ||
27 | |||
28 | #define amd76x_printk(level, fmt, arg...) \ | 23 | #define amd76x_printk(level, fmt, arg...) \ |
29 | edac_printk(level, "amd76x", fmt, ##arg) | 24 | edac_printk(level, "amd76x", fmt, ##arg) |
30 | |||
31 | 25 | ||
32 | #define amd76x_mc_printk(mci, level, fmt, arg...) \ | 26 | #define amd76x_mc_printk(mci, level, fmt, arg...) \ |
33 | edac_mc_chipset_printk(mci, level, "amd76x", fmt, ##arg) | 27 | edac_mc_chipset_printk(mci, level, "amd76x", fmt, ##arg) |
34 | |||
35 | 28 | ||
36 | #define AMD76X_NR_CSROWS 8 | 29 | #define AMD76X_NR_CSROWS 8 |
37 | #define AMD76X_NR_CHANS 1 | 30 | #define AMD76X_NR_CHANS 1 |
38 | #define AMD76X_NR_DIMMS 4 | 31 | #define AMD76X_NR_DIMMS 4 |
39 | 32 | ||
40 | |||
41 | /* AMD 76x register addresses - device 0 function 0 - PCI bridge */ | 33 | /* AMD 76x register addresses - device 0 function 0 - PCI bridge */ |
34 | |||
42 | #define AMD76X_ECC_MODE_STATUS 0x48 /* Mode and status of ECC (32b) | 35 | #define AMD76X_ECC_MODE_STATUS 0x48 /* Mode and status of ECC (32b) |
43 | * | 36 | * |
44 | * 31:16 reserved | 37 | * 31:16 reserved |
@@ -50,6 +43,7 @@ | |||
50 | * 7:4 UE cs row | 43 | * 7:4 UE cs row |
51 | * 3:0 CE cs row | 44 | * 3:0 CE cs row |
52 | */ | 45 | */ |
46 | |||
53 | #define AMD76X_DRAM_MODE_STATUS 0x58 /* DRAM Mode and status (32b) | 47 | #define AMD76X_DRAM_MODE_STATUS 0x58 /* DRAM Mode and status (32b) |
54 | * | 48 | * |
55 | * 31:26 clock disable 5 - 0 | 49 | * 31:26 clock disable 5 - 0 |
@@ -64,6 +58,7 @@ | |||
64 | * 15:8 reserved | 58 | * 15:8 reserved |
65 | * 7:0 x4 mode enable 7 - 0 | 59 | * 7:0 x4 mode enable 7 - 0 |
66 | */ | 60 | */ |
61 | |||
67 | #define AMD76X_MEM_BASE_ADDR 0xC0 /* Memory base address (8 x 32b) | 62 | #define AMD76X_MEM_BASE_ADDR 0xC0 /* Memory base address (8 x 32b) |
68 | * | 63 | * |
69 | * 31:23 chip-select base | 64 | * 31:23 chip-select base |
@@ -74,29 +69,28 @@ | |||
74 | * 0 chip-select enable | 69 | * 0 chip-select enable |
75 | */ | 70 | */ |
76 | 71 | ||
77 | |||
78 | struct amd76x_error_info { | 72 | struct amd76x_error_info { |
79 | u32 ecc_mode_status; | 73 | u32 ecc_mode_status; |
80 | }; | 74 | }; |
81 | 75 | ||
82 | |||
83 | enum amd76x_chips { | 76 | enum amd76x_chips { |
84 | AMD761 = 0, | 77 | AMD761 = 0, |
85 | AMD762 | 78 | AMD762 |
86 | }; | 79 | }; |
87 | 80 | ||
88 | |||
89 | struct amd76x_dev_info { | 81 | struct amd76x_dev_info { |
90 | const char *ctl_name; | 82 | const char *ctl_name; |
91 | }; | 83 | }; |
92 | 84 | ||
93 | |||
94 | static const struct amd76x_dev_info amd76x_devs[] = { | 85 | static const struct amd76x_dev_info amd76x_devs[] = { |
95 | [AMD761] = {.ctl_name = "AMD761"}, | 86 | [AMD761] = { |
96 | [AMD762] = {.ctl_name = "AMD762"}, | 87 | .ctl_name = "AMD761" |
88 | }, | ||
89 | [AMD762] = { | ||
90 | .ctl_name = "AMD762" | ||
91 | }, | ||
97 | }; | 92 | }; |
98 | 93 | ||
99 | |||
100 | /** | 94 | /** |
101 | * amd76x_get_error_info - fetch error information | 95 | * amd76x_get_error_info - fetch error information |
102 | * @mci: Memory controller | 96 | * @mci: Memory controller |
@@ -105,23 +99,21 @@ static const struct amd76x_dev_info amd76x_devs[] = { | |||
105 | * Fetch and store the AMD76x ECC status. Clear pending status | 99 | * Fetch and store the AMD76x ECC status. Clear pending status |
106 | * on the chip so that further errors will be reported | 100 | * on the chip so that further errors will be reported |
107 | */ | 101 | */ |
108 | 102 | static void amd76x_get_error_info(struct mem_ctl_info *mci, | |
109 | static void amd76x_get_error_info (struct mem_ctl_info *mci, | 103 | struct amd76x_error_info *info) |
110 | struct amd76x_error_info *info) | ||
111 | { | 104 | { |
112 | pci_read_config_dword(mci->pdev, AMD76X_ECC_MODE_STATUS, | 105 | pci_read_config_dword(mci->pdev, AMD76X_ECC_MODE_STATUS, |
113 | &info->ecc_mode_status); | 106 | &info->ecc_mode_status); |
114 | 107 | ||
115 | if (info->ecc_mode_status & BIT(8)) | 108 | if (info->ecc_mode_status & BIT(8)) |
116 | pci_write_bits32(mci->pdev, AMD76X_ECC_MODE_STATUS, | 109 | pci_write_bits32(mci->pdev, AMD76X_ECC_MODE_STATUS, |
117 | (u32) BIT(8), (u32) BIT(8)); | 110 | (u32) BIT(8), (u32) BIT(8)); |
118 | 111 | ||
119 | if (info->ecc_mode_status & BIT(9)) | 112 | if (info->ecc_mode_status & BIT(9)) |
120 | pci_write_bits32(mci->pdev, AMD76X_ECC_MODE_STATUS, | 113 | pci_write_bits32(mci->pdev, AMD76X_ECC_MODE_STATUS, |
121 | (u32) BIT(9), (u32) BIT(9)); | 114 | (u32) BIT(9), (u32) BIT(9)); |
122 | } | 115 | } |
123 | 116 | ||
124 | |||
125 | /** | 117 | /** |
126 | * amd76x_process_error_info - Error check | 118 | * amd76x_process_error_info - Error check |
127 | * @mci: Memory controller | 119 | * @mci: Memory controller |
@@ -132,8 +124,7 @@ static void amd76x_get_error_info (struct mem_ctl_info *mci, | |||
132 | * A return of 1 indicates an error. Also if handle_errors is true | 124 | * A return of 1 indicates an error. Also if handle_errors is true |
133 | * then attempt to handle and clean up after the error | 125 | * then attempt to handle and clean up after the error |
134 | */ | 126 | */ |
135 | 127 | static int amd76x_process_error_info(struct mem_ctl_info *mci, | |
136 | static int amd76x_process_error_info (struct mem_ctl_info *mci, | ||
137 | struct amd76x_error_info *info, int handle_errors) | 128 | struct amd76x_error_info *info, int handle_errors) |
138 | { | 129 | { |
139 | int error_found; | 130 | int error_found; |
@@ -149,9 +140,8 @@ static int amd76x_process_error_info (struct mem_ctl_info *mci, | |||
149 | 140 | ||
150 | if (handle_errors) { | 141 | if (handle_errors) { |
151 | row = (info->ecc_mode_status >> 4) & 0xf; | 142 | row = (info->ecc_mode_status >> 4) & 0xf; |
152 | edac_mc_handle_ue(mci, | 143 | edac_mc_handle_ue(mci, mci->csrows[row].first_page, 0, |
153 | mci->csrows[row].first_page, 0, row, | 144 | row, mci->ctl_name); |
154 | mci->ctl_name); | ||
155 | } | 145 | } |
156 | } | 146 | } |
157 | 147 | ||
@@ -163,11 +153,11 @@ static int amd76x_process_error_info (struct mem_ctl_info *mci, | |||
163 | 153 | ||
164 | if (handle_errors) { | 154 | if (handle_errors) { |
165 | row = info->ecc_mode_status & 0xf; | 155 | row = info->ecc_mode_status & 0xf; |
166 | edac_mc_handle_ce(mci, | 156 | edac_mc_handle_ce(mci, mci->csrows[row].first_page, 0, |
167 | mci->csrows[row].first_page, 0, 0, row, 0, | 157 | 0, row, 0, mci->ctl_name); |
168 | mci->ctl_name); | ||
169 | } | 158 | } |
170 | } | 159 | } |
160 | |||
171 | return error_found; | 161 | return error_found; |
172 | } | 162 | } |
173 | 163 | ||
@@ -178,7 +168,6 @@ static int amd76x_process_error_info (struct mem_ctl_info *mci, | |||
178 | * Called by the poll handlers this function reads the status | 168 | * Called by the poll handlers this function reads the status |
179 | * from the controller and checks for errors. | 169 | * from the controller and checks for errors. |
180 | */ | 170 | */ |
181 | |||
182 | static void amd76x_check(struct mem_ctl_info *mci) | 171 | static void amd76x_check(struct mem_ctl_info *mci) |
183 | { | 172 | { |
184 | struct amd76x_error_info info; | 173 | struct amd76x_error_info info; |
@@ -187,7 +176,6 @@ static void amd76x_check(struct mem_ctl_info *mci) | |||
187 | amd76x_process_error_info(mci, &info, 1); | 176 | amd76x_process_error_info(mci, &info, 1); |
188 | } | 177 | } |
189 | 178 | ||
190 | |||
191 | /** | 179 | /** |
192 | * amd76x_probe1 - Perform set up for detected device | 180 | * amd76x_probe1 - Perform set up for detected device |
193 | * @pdev; PCI device detected | 181 | * @pdev; PCI device detected |
@@ -197,7 +185,6 @@ static void amd76x_check(struct mem_ctl_info *mci) | |||
197 | * controller status reporting. We configure and set up the | 185 | * controller status reporting. We configure and set up the |
198 | * memory controller reporting and claim the device. | 186 | * memory controller reporting and claim the device. |
199 | */ | 187 | */ |
200 | |||
201 | static int amd76x_probe1(struct pci_dev *pdev, int dev_idx) | 188 | static int amd76x_probe1(struct pci_dev *pdev, int dev_idx) |
202 | { | 189 | { |
203 | int rc = -ENODEV; | 190 | int rc = -ENODEV; |
@@ -214,10 +201,8 @@ static int amd76x_probe1(struct pci_dev *pdev, int dev_idx) | |||
214 | struct amd76x_error_info discard; | 201 | struct amd76x_error_info discard; |
215 | 202 | ||
216 | debugf0("%s()\n", __func__); | 203 | debugf0("%s()\n", __func__); |
217 | |||
218 | pci_read_config_dword(pdev, AMD76X_ECC_MODE_STATUS, &ems); | 204 | pci_read_config_dword(pdev, AMD76X_ECC_MODE_STATUS, &ems); |
219 | ems_mode = (ems >> 10) & 0x3; | 205 | ems_mode = (ems >> 10) & 0x3; |
220 | |||
221 | mci = edac_mc_alloc(0, AMD76X_NR_CSROWS, AMD76X_NR_CHANS); | 206 | mci = edac_mc_alloc(0, AMD76X_NR_CSROWS, AMD76X_NR_CHANS); |
222 | 207 | ||
223 | if (mci == NULL) { | 208 | if (mci == NULL) { |
@@ -226,14 +211,11 @@ static int amd76x_probe1(struct pci_dev *pdev, int dev_idx) | |||
226 | } | 211 | } |
227 | 212 | ||
228 | debugf0("%s(): mci = %p\n", __func__, mci); | 213 | debugf0("%s(): mci = %p\n", __func__, mci); |
229 | |||
230 | mci->pdev = pdev; | 214 | mci->pdev = pdev; |
231 | mci->mtype_cap = MEM_FLAG_RDDR; | 215 | mci->mtype_cap = MEM_FLAG_RDDR; |
232 | |||
233 | mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED; | 216 | mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED; |
234 | mci->edac_cap = ems_mode ? | 217 | mci->edac_cap = ems_mode ? |
235 | (EDAC_FLAG_EC | EDAC_FLAG_SECDED) : EDAC_FLAG_NONE; | 218 | (EDAC_FLAG_EC | EDAC_FLAG_SECDED) : EDAC_FLAG_NONE; |
236 | |||
237 | mci->mod_name = EDAC_MOD_STR; | 219 | mci->mod_name = EDAC_MOD_STR; |
238 | mci->mod_ver = "$Revision: 1.4.2.5 $"; | 220 | mci->mod_ver = "$Revision: 1.4.2.5 $"; |
239 | mci->ctl_name = amd76x_devs[dev_idx].ctl_name; | 221 | mci->ctl_name = amd76x_devs[dev_idx].ctl_name; |
@@ -249,18 +231,15 @@ static int amd76x_probe1(struct pci_dev *pdev, int dev_idx) | |||
249 | 231 | ||
250 | /* find the DRAM Chip Select Base address and mask */ | 232 | /* find the DRAM Chip Select Base address and mask */ |
251 | pci_read_config_dword(mci->pdev, | 233 | pci_read_config_dword(mci->pdev, |
252 | AMD76X_MEM_BASE_ADDR + (index * 4), | 234 | AMD76X_MEM_BASE_ADDR + (index * 4), &mba); |
253 | &mba); | ||
254 | 235 | ||
255 | if (!(mba & BIT(0))) | 236 | if (!(mba & BIT(0))) |
256 | continue; | 237 | continue; |
257 | 238 | ||
258 | mba_base = mba & 0xff800000UL; | 239 | mba_base = mba & 0xff800000UL; |
259 | mba_mask = ((mba & 0xff80) << 16) | 0x7fffffUL; | 240 | mba_mask = ((mba & 0xff80) << 16) | 0x7fffffUL; |
260 | |||
261 | pci_read_config_dword(mci->pdev, AMD76X_DRAM_MODE_STATUS, | 241 | pci_read_config_dword(mci->pdev, AMD76X_DRAM_MODE_STATUS, |
262 | &dms); | 242 | &dms); |
263 | |||
264 | csrow->first_page = mba_base >> PAGE_SHIFT; | 243 | csrow->first_page = mba_base >> PAGE_SHIFT; |
265 | csrow->nr_pages = (mba_mask + 1) >> PAGE_SHIFT; | 244 | csrow->nr_pages = (mba_mask + 1) >> PAGE_SHIFT; |
266 | csrow->last_page = csrow->first_page + csrow->nr_pages - 1; | 245 | csrow->last_page = csrow->first_page + csrow->nr_pages - 1; |
@@ -290,7 +269,7 @@ fail: | |||
290 | 269 | ||
291 | /* returns count (>= 0), or negative on error */ | 270 | /* returns count (>= 0), or negative on error */ |
292 | static int __devinit amd76x_init_one(struct pci_dev *pdev, | 271 | static int __devinit amd76x_init_one(struct pci_dev *pdev, |
293 | const struct pci_device_id *ent) | 272 | const struct pci_device_id *ent) |
294 | { | 273 | { |
295 | debugf0("%s()\n", __func__); | 274 | debugf0("%s()\n", __func__); |
296 | 275 | ||
@@ -298,7 +277,6 @@ static int __devinit amd76x_init_one(struct pci_dev *pdev, | |||
298 | return amd76x_probe1(pdev, ent->driver_data); | 277 | return amd76x_probe1(pdev, ent->driver_data); |
299 | } | 278 | } |
300 | 279 | ||
301 | |||
302 | /** | 280 | /** |
303 | * amd76x_remove_one - driver shutdown | 281 | * amd76x_remove_one - driver shutdown |
304 | * @pdev: PCI device being handed back | 282 | * @pdev: PCI device being handed back |
@@ -307,7 +285,6 @@ static int __devinit amd76x_init_one(struct pci_dev *pdev, | |||
307 | * structure for the device then delete the mci and free the | 285 | * structure for the device then delete the mci and free the |
308 | * resources. | 286 | * resources. |
309 | */ | 287 | */ |
310 | |||
311 | static void __devexit amd76x_remove_one(struct pci_dev *pdev) | 288 | static void __devexit amd76x_remove_one(struct pci_dev *pdev) |
312 | { | 289 | { |
313 | struct mem_ctl_info *mci; | 290 | struct mem_ctl_info *mci; |
@@ -320,18 +297,22 @@ static void __devexit amd76x_remove_one(struct pci_dev *pdev) | |||
320 | edac_mc_free(mci); | 297 | edac_mc_free(mci); |
321 | } | 298 | } |
322 | 299 | ||
323 | |||
324 | static const struct pci_device_id amd76x_pci_tbl[] __devinitdata = { | 300 | static const struct pci_device_id amd76x_pci_tbl[] __devinitdata = { |
325 | {PCI_VEND_DEV(AMD, FE_GATE_700C), PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 301 | { |
326 | AMD762}, | 302 | PCI_VEND_DEV(AMD, FE_GATE_700C), PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
327 | {PCI_VEND_DEV(AMD, FE_GATE_700E), PCI_ANY_ID, PCI_ANY_ID, 0, 0, | 303 | AMD762 |
328 | AMD761}, | 304 | }, |
329 | {0,} /* 0 terminated list. */ | 305 | { |
306 | PCI_VEND_DEV(AMD, FE_GATE_700E), PCI_ANY_ID, PCI_ANY_ID, 0, 0, | ||
307 | AMD761 | ||
308 | }, | ||
309 | { | ||
310 | 0, | ||
311 | } /* 0 terminated list. */ | ||
330 | }; | 312 | }; |
331 | 313 | ||
332 | MODULE_DEVICE_TABLE(pci, amd76x_pci_tbl); | 314 | MODULE_DEVICE_TABLE(pci, amd76x_pci_tbl); |
333 | 315 | ||
334 | |||
335 | static struct pci_driver amd76x_driver = { | 316 | static struct pci_driver amd76x_driver = { |
336 | .name = EDAC_MOD_STR, | 317 | .name = EDAC_MOD_STR, |
337 | .probe = amd76x_init_one, | 318 | .probe = amd76x_init_one, |