diff options
| author | Borislav Petkov <borislav.petkov@amd.com> | 2010-10-01 14:11:07 -0400 |
|---|---|---|
| committer | Borislav Petkov <borislav.petkov@amd.com> | 2011-01-07 05:33:54 -0500 |
| commit | 8d5b5d9c7b86e44fda29a367db3ccd2815a52f7c (patch) | |
| tree | 3444029260ba184d6726bd46c48d9fa87a2fc3a5 /drivers/edac/amd64_edac_inj.c | |
| parent | b8cfa02f833a614e80f851747c4ce14989a4cfd0 (diff) | |
amd64_edac: Rename CPU PCI devices
Rename variables representing PCI devices to their BKDG names for faster
search and shorter, clearer code.
Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
Diffstat (limited to 'drivers/edac/amd64_edac_inj.c')
| -rw-r--r-- | drivers/edac/amd64_edac_inj.c | 12 |
1 files changed, 4 insertions, 8 deletions
diff --git a/drivers/edac/amd64_edac_inj.c b/drivers/edac/amd64_edac_inj.c index 29f1f7a612d9..523ce4a6edc6 100644 --- a/drivers/edac/amd64_edac_inj.c +++ b/drivers/edac/amd64_edac_inj.c | |||
| @@ -122,15 +122,13 @@ static ssize_t amd64_inject_read_store(struct mem_ctl_info *mci, | |||
| 122 | /* Form value to choose 16-byte section of cacheline */ | 122 | /* Form value to choose 16-byte section of cacheline */ |
| 123 | section = F10_NB_ARRAY_DRAM_ECC | | 123 | section = F10_NB_ARRAY_DRAM_ECC | |
| 124 | SET_NB_ARRAY_ADDRESS(pvt->injection.section); | 124 | SET_NB_ARRAY_ADDRESS(pvt->injection.section); |
| 125 | pci_write_config_dword(pvt->misc_f3_ctl, | 125 | pci_write_config_dword(pvt->F3, F10_NB_ARRAY_ADDR, section); |
| 126 | F10_NB_ARRAY_ADDR, section); | ||
| 127 | 126 | ||
| 128 | word_bits = SET_NB_DRAM_INJECTION_READ(pvt->injection.word, | 127 | word_bits = SET_NB_DRAM_INJECTION_READ(pvt->injection.word, |
| 129 | pvt->injection.bit_map); | 128 | pvt->injection.bit_map); |
| 130 | 129 | ||
| 131 | /* Issue 'word' and 'bit' along with the READ request */ | 130 | /* Issue 'word' and 'bit' along with the READ request */ |
| 132 | pci_write_config_dword(pvt->misc_f3_ctl, | 131 | pci_write_config_dword(pvt->F3, F10_NB_ARRAY_DATA, word_bits); |
| 133 | F10_NB_ARRAY_DATA, word_bits); | ||
| 134 | 132 | ||
| 135 | debugf0("section=0x%x word_bits=0x%x\n", section, word_bits); | 133 | debugf0("section=0x%x word_bits=0x%x\n", section, word_bits); |
| 136 | 134 | ||
| @@ -157,15 +155,13 @@ static ssize_t amd64_inject_write_store(struct mem_ctl_info *mci, | |||
| 157 | /* Form value to choose 16-byte section of cacheline */ | 155 | /* Form value to choose 16-byte section of cacheline */ |
| 158 | section = F10_NB_ARRAY_DRAM_ECC | | 156 | section = F10_NB_ARRAY_DRAM_ECC | |
| 159 | SET_NB_ARRAY_ADDRESS(pvt->injection.section); | 157 | SET_NB_ARRAY_ADDRESS(pvt->injection.section); |
| 160 | pci_write_config_dword(pvt->misc_f3_ctl, | 158 | pci_write_config_dword(pvt->F3, F10_NB_ARRAY_ADDR, section); |
| 161 | F10_NB_ARRAY_ADDR, section); | ||
| 162 | 159 | ||
| 163 | word_bits = SET_NB_DRAM_INJECTION_WRITE(pvt->injection.word, | 160 | word_bits = SET_NB_DRAM_INJECTION_WRITE(pvt->injection.word, |
| 164 | pvt->injection.bit_map); | 161 | pvt->injection.bit_map); |
| 165 | 162 | ||
| 166 | /* Issue 'word' and 'bit' along with the READ request */ | 163 | /* Issue 'word' and 'bit' along with the READ request */ |
| 167 | pci_write_config_dword(pvt->misc_f3_ctl, | 164 | pci_write_config_dword(pvt->F3, F10_NB_ARRAY_DATA, word_bits); |
| 168 | F10_NB_ARRAY_DATA, word_bits); | ||
| 169 | 165 | ||
| 170 | debugf0("section=0x%x word_bits=0x%x\n", section, word_bits); | 166 | debugf0("section=0x%x word_bits=0x%x\n", section, word_bits); |
| 171 | 167 | ||