diff options
author | Borislav Petkov <borislav.petkov@amd.com> | 2011-01-19 12:15:10 -0500 |
---|---|---|
committer | Borislav Petkov <borislav.petkov@amd.com> | 2011-03-17 09:46:26 -0400 |
commit | df71a053241548b728d3bf45b0c11ed092a20319 (patch) | |
tree | a82963dc5b4365b456a4b3054b052268291f5c37 /drivers/edac/amd64_edac.c | |
parent | a3b7db09a6d5a6b8d237766b0b320447bb609bc5 (diff) |
amd64_edac: Enable driver on F15h
Add the PCI device ids required for driver registration. Remove
pvt->ctl_name and use the family descriptor directly, instead. Then,
bump driver version and fixup its format. Finally, enable DRAM ECC
decoding on F15h.
Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
Diffstat (limited to 'drivers/edac/amd64_edac.c')
-rw-r--r-- | drivers/edac/amd64_edac.c | 30 |
1 files changed, 23 insertions, 7 deletions
diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index e4b2792062ea..70e0f84be0d8 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c | |||
@@ -1604,6 +1604,8 @@ static struct amd64_family_type amd64_family_types[] = { | |||
1604 | }, | 1604 | }, |
1605 | [F15_CPUS] = { | 1605 | [F15_CPUS] = { |
1606 | .ctl_name = "F15h", | 1606 | .ctl_name = "F15h", |
1607 | .f1_id = PCI_DEVICE_ID_AMD_15H_NB_F1, | ||
1608 | .f3_id = PCI_DEVICE_ID_AMD_15H_NB_F3, | ||
1607 | .ops = { | 1609 | .ops = { |
1608 | .early_channel_count = f1x_early_channel_count, | 1610 | .early_channel_count = f1x_early_channel_count, |
1609 | .map_sysaddr_to_csrow = f1x_map_sysaddr_to_csrow, | 1611 | .map_sysaddr_to_csrow = f1x_map_sysaddr_to_csrow, |
@@ -2363,7 +2365,8 @@ static void set_mc_sysfs_attrs(struct mem_ctl_info *mci) | |||
2363 | mci->mc_driver_sysfs_attributes = sysfs_attrs; | 2365 | mci->mc_driver_sysfs_attributes = sysfs_attrs; |
2364 | } | 2366 | } |
2365 | 2367 | ||
2366 | static void setup_mci_misc_attrs(struct mem_ctl_info *mci) | 2368 | static void setup_mci_misc_attrs(struct mem_ctl_info *mci, |
2369 | struct amd64_family_type *fam) | ||
2367 | { | 2370 | { |
2368 | struct amd64_pvt *pvt = mci->pvt_info; | 2371 | struct amd64_pvt *pvt = mci->pvt_info; |
2369 | 2372 | ||
@@ -2379,7 +2382,7 @@ static void setup_mci_misc_attrs(struct mem_ctl_info *mci) | |||
2379 | mci->edac_cap = amd64_determine_edac_cap(pvt); | 2382 | mci->edac_cap = amd64_determine_edac_cap(pvt); |
2380 | mci->mod_name = EDAC_MOD_STR; | 2383 | mci->mod_name = EDAC_MOD_STR; |
2381 | mci->mod_ver = EDAC_AMD64_VERSION; | 2384 | mci->mod_ver = EDAC_AMD64_VERSION; |
2382 | mci->ctl_name = pvt->ctl_name; | 2385 | mci->ctl_name = fam->ctl_name; |
2383 | mci->dev_name = pci_name(pvt->F2); | 2386 | mci->dev_name = pci_name(pvt->F2); |
2384 | mci->ctl_page_to_phys = NULL; | 2387 | mci->ctl_page_to_phys = NULL; |
2385 | 2388 | ||
@@ -2400,12 +2403,16 @@ static struct amd64_family_type *amd64_per_family_init(struct amd64_pvt *pvt) | |||
2400 | case 0xf: | 2403 | case 0xf: |
2401 | fam_type = &amd64_family_types[K8_CPUS]; | 2404 | fam_type = &amd64_family_types[K8_CPUS]; |
2402 | pvt->ops = &amd64_family_types[K8_CPUS].ops; | 2405 | pvt->ops = &amd64_family_types[K8_CPUS].ops; |
2403 | pvt->ctl_name = fam_type->ctl_name; | ||
2404 | break; | 2406 | break; |
2407 | |||
2405 | case 0x10: | 2408 | case 0x10: |
2406 | fam_type = &amd64_family_types[F10_CPUS]; | 2409 | fam_type = &amd64_family_types[F10_CPUS]; |
2407 | pvt->ops = &amd64_family_types[F10_CPUS].ops; | 2410 | pvt->ops = &amd64_family_types[F10_CPUS].ops; |
2408 | pvt->ctl_name = fam_type->ctl_name; | 2411 | break; |
2412 | |||
2413 | case 0x15: | ||
2414 | fam_type = &amd64_family_types[F15_CPUS]; | ||
2415 | pvt->ops = &amd64_family_types[F15_CPUS].ops; | ||
2409 | break; | 2416 | break; |
2410 | 2417 | ||
2411 | default: | 2418 | default: |
@@ -2415,7 +2422,7 @@ static struct amd64_family_type *amd64_per_family_init(struct amd64_pvt *pvt) | |||
2415 | 2422 | ||
2416 | pvt->ext_model = boot_cpu_data.x86_model >> 4; | 2423 | pvt->ext_model = boot_cpu_data.x86_model >> 4; |
2417 | 2424 | ||
2418 | amd64_info("%s %sdetected (node %d).\n", pvt->ctl_name, | 2425 | amd64_info("%s %sdetected (node %d).\n", fam_type->ctl_name, |
2419 | (fam == 0xf ? | 2426 | (fam == 0xf ? |
2420 | (pvt->ext_model >= K8_REV_F ? "revF or later " | 2427 | (pvt->ext_model >= K8_REV_F ? "revF or later " |
2421 | : "revE or earlier ") | 2428 | : "revE or earlier ") |
@@ -2469,7 +2476,7 @@ static int amd64_init_one_instance(struct pci_dev *F2) | |||
2469 | mci->pvt_info = pvt; | 2476 | mci->pvt_info = pvt; |
2470 | mci->dev = &pvt->F2->dev; | 2477 | mci->dev = &pvt->F2->dev; |
2471 | 2478 | ||
2472 | setup_mci_misc_attrs(mci); | 2479 | setup_mci_misc_attrs(mci, fam_type); |
2473 | 2480 | ||
2474 | if (init_csrows(mci)) | 2481 | if (init_csrows(mci)) |
2475 | mci->edac_cap = EDAC_FLAG_NONE; | 2482 | mci->edac_cap = EDAC_FLAG_NONE; |
@@ -2612,6 +2619,15 @@ static const struct pci_device_id amd64_pci_table[] __devinitdata = { | |||
2612 | .class = 0, | 2619 | .class = 0, |
2613 | .class_mask = 0, | 2620 | .class_mask = 0, |
2614 | }, | 2621 | }, |
2622 | { | ||
2623 | .vendor = PCI_VENDOR_ID_AMD, | ||
2624 | .device = PCI_DEVICE_ID_AMD_15H_NB_F2, | ||
2625 | .subvendor = PCI_ANY_ID, | ||
2626 | .subdevice = PCI_ANY_ID, | ||
2627 | .class = 0, | ||
2628 | .class_mask = 0, | ||
2629 | }, | ||
2630 | |||
2615 | {0, } | 2631 | {0, } |
2616 | }; | 2632 | }; |
2617 | MODULE_DEVICE_TABLE(pci, amd64_pci_table); | 2633 | MODULE_DEVICE_TABLE(pci, amd64_pci_table); |
@@ -2652,7 +2668,7 @@ static int __init amd64_edac_init(void) | |||
2652 | { | 2668 | { |
2653 | int err = -ENODEV; | 2669 | int err = -ENODEV; |
2654 | 2670 | ||
2655 | edac_printk(KERN_INFO, EDAC_MOD_STR, EDAC_AMD64_VERSION "\n"); | 2671 | printk(KERN_INFO "AMD64 EDAC driver v%s\n", EDAC_AMD64_VERSION); |
2656 | 2672 | ||
2657 | opstate_init(); | 2673 | opstate_init(); |
2658 | 2674 | ||