diff options
author | Robert Richter <robert.richter@amd.com> | 2010-10-25 10:28:14 -0400 |
---|---|---|
committer | Robert Richter <robert.richter@amd.com> | 2010-10-25 10:29:12 -0400 |
commit | dbd1e66e04558a582e673bc4a9cd933ce0228d93 (patch) | |
tree | 85f3633276282cde0a3ac558d988704eaa3e68af /drivers/edac/amd64_edac.c | |
parent | 328b8f1ba50b708a1b3c0acd7c41ee1b356822f6 (diff) | |
parent | 4a60cfa9457749f7987fd4f3c956dbba5a281129 (diff) |
Merge commit 'linux-2.6/master' (early part) into oprofile/core
This branch depends on these apic patches:
apic, x86: Use BIOS settings for IBS and MCE threshold interrupt LVT offsets
apic, x86: Check if EILVT APIC registers are available (AMD only)
Signed-off-by: Robert Richter <robert.richter@amd.com>
Diffstat (limited to 'drivers/edac/amd64_edac.c')
-rw-r--r-- | drivers/edac/amd64_edac.c | 17 |
1 files changed, 12 insertions, 5 deletions
diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index e7d5d6b5dcf6..8521401bbd75 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c | |||
@@ -1,5 +1,5 @@ | |||
1 | #include "amd64_edac.h" | 1 | #include "amd64_edac.h" |
2 | #include <asm/k8.h> | 2 | #include <asm/amd_nb.h> |
3 | 3 | ||
4 | static struct edac_pci_ctl_info *amd64_ctl_pci; | 4 | static struct edac_pci_ctl_info *amd64_ctl_pci; |
5 | 5 | ||
@@ -2073,11 +2073,18 @@ static inline void __amd64_decode_bus_error(struct mem_ctl_info *mci, | |||
2073 | amd64_handle_ue(mci, info); | 2073 | amd64_handle_ue(mci, info); |
2074 | } | 2074 | } |
2075 | 2075 | ||
2076 | void amd64_decode_bus_error(int node_id, struct err_regs *regs) | 2076 | void amd64_decode_bus_error(int node_id, struct mce *m, u32 nbcfg) |
2077 | { | 2077 | { |
2078 | struct mem_ctl_info *mci = mci_lookup[node_id]; | 2078 | struct mem_ctl_info *mci = mci_lookup[node_id]; |
2079 | struct err_regs regs; | ||
2079 | 2080 | ||
2080 | __amd64_decode_bus_error(mci, regs); | 2081 | regs.nbsl = (u32) m->status; |
2082 | regs.nbsh = (u32)(m->status >> 32); | ||
2083 | regs.nbeal = (u32) m->addr; | ||
2084 | regs.nbeah = (u32)(m->addr >> 32); | ||
2085 | regs.nbcfg = nbcfg; | ||
2086 | |||
2087 | __amd64_decode_bus_error(mci, ®s); | ||
2081 | 2088 | ||
2082 | /* | 2089 | /* |
2083 | * Check the UE bit of the NB status high register, if set generate some | 2090 | * Check the UE bit of the NB status high register, if set generate some |
@@ -2086,7 +2093,7 @@ void amd64_decode_bus_error(int node_id, struct err_regs *regs) | |||
2086 | * | 2093 | * |
2087 | * FIXME: this should go somewhere else, if at all. | 2094 | * FIXME: this should go somewhere else, if at all. |
2088 | */ | 2095 | */ |
2089 | if (regs->nbsh & K8_NBSH_UC_ERR && !report_gart_errors) | 2096 | if (regs.nbsh & K8_NBSH_UC_ERR && !report_gart_errors) |
2090 | edac_mc_handle_ue_no_info(mci, "UE bit is set"); | 2097 | edac_mc_handle_ue_no_info(mci, "UE bit is set"); |
2091 | 2098 | ||
2092 | } | 2099 | } |
@@ -2927,7 +2934,7 @@ static int __init amd64_edac_init(void) | |||
2927 | * to finish initialization of the MC instances. | 2934 | * to finish initialization of the MC instances. |
2928 | */ | 2935 | */ |
2929 | err = -ENODEV; | 2936 | err = -ENODEV; |
2930 | for (nb = 0; nb < num_k8_northbridges; nb++) { | 2937 | for (nb = 0; nb < k8_northbridges.num; nb++) { |
2931 | if (!pvt_lookup[nb]) | 2938 | if (!pvt_lookup[nb]) |
2932 | continue; | 2939 | continue; |
2933 | 2940 | ||