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authorGlenn Elliott <gelliott@cs.unc.edu>2012-03-04 19:47:13 -0500
committerGlenn Elliott <gelliott@cs.unc.edu>2012-03-04 19:47:13 -0500
commitc71c03bda1e86c9d5198c5d83f712e695c4f2a1e (patch)
treeecb166cb3e2b7e2adb3b5e292245fefd23381ac8 /drivers/dma/fsldma.h
parentea53c912f8a86a8567697115b6a0d8152beee5c8 (diff)
parent6a00f206debf8a5c8899055726ad127dbeeed098 (diff)
Merge branch 'mpi-master' into wip-k-fmlpwip-k-fmlp
Conflicts: litmus/sched_cedf.c
Diffstat (limited to 'drivers/dma/fsldma.h')
-rw-r--r--drivers/dma/fsldma.h15
1 files changed, 12 insertions, 3 deletions
diff --git a/drivers/dma/fsldma.h b/drivers/dma/fsldma.h
index cb4d6ff51597..9cb5aa57c677 100644
--- a/drivers/dma/fsldma.h
+++ b/drivers/dma/fsldma.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved. 2 * Copyright (C) 2007-2010 Freescale Semiconductor, Inc. All rights reserved.
3 * 3 *
4 * Author: 4 * Author:
5 * Zhang Wei <wei.zhang@freescale.com>, Jul 2007 5 * Zhang Wei <wei.zhang@freescale.com>, Jul 2007
@@ -36,6 +36,13 @@
36#define FSL_DMA_MR_DAHE 0x00002000 36#define FSL_DMA_MR_DAHE 0x00002000
37#define FSL_DMA_MR_SAHE 0x00001000 37#define FSL_DMA_MR_SAHE 0x00001000
38 38
39/*
40 * Bandwidth/pause control determines how many bytes a given
41 * channel is allowed to transfer before the DMA engine pauses
42 * the current channel and switches to the next channel
43 */
44#define FSL_DMA_MR_BWC 0x08000000
45
39/* Special MR definition for MPC8349 */ 46/* Special MR definition for MPC8349 */
40#define FSL_DMA_MR_EOTIE 0x00000080 47#define FSL_DMA_MR_EOTIE 0x00000080
41#define FSL_DMA_MR_PRC_RM 0x00000800 48#define FSL_DMA_MR_PRC_RM 0x00000800
@@ -95,8 +102,8 @@ struct fsl_desc_sw {
95} __attribute__((aligned(32))); 102} __attribute__((aligned(32)));
96 103
97struct fsldma_chan_regs { 104struct fsldma_chan_regs {
98 u32 mr; /* 0x00 - Mode Register */ 105 u32 mr; /* 0x00 - Mode Register */
99 u32 sr; /* 0x04 - Status Register */ 106 u32 sr; /* 0x04 - Status Register */
100 u64 cdar; /* 0x08 - Current descriptor address register */ 107 u64 cdar; /* 0x08 - Current descriptor address register */
101 u64 sar; /* 0x10 - Source Address Register */ 108 u64 sar; /* 0x10 - Source Address Register */
102 u64 dar; /* 0x18 - Destination Address Register */ 109 u64 dar; /* 0x18 - Destination Address Register */
@@ -128,6 +135,7 @@ struct fsldma_device {
128#define FSL_DMA_CHAN_START_EXT 0x00002000 135#define FSL_DMA_CHAN_START_EXT 0x00002000
129 136
130struct fsldma_chan { 137struct fsldma_chan {
138 char name[8]; /* Channel name */
131 struct fsldma_chan_regs __iomem *regs; 139 struct fsldma_chan_regs __iomem *regs;
132 dma_cookie_t completed_cookie; /* The maximum cookie completed */ 140 dma_cookie_t completed_cookie; /* The maximum cookie completed */
133 spinlock_t desc_lock; /* Descriptor operation lock */ 141 spinlock_t desc_lock; /* Descriptor operation lock */
@@ -140,6 +148,7 @@ struct fsldma_chan {
140 int id; /* Raw id of this channel */ 148 int id; /* Raw id of this channel */
141 struct tasklet_struct tasklet; 149 struct tasklet_struct tasklet;
142 u32 feature; 150 u32 feature;
151 bool idle; /* DMA controller is idle */
143 152
144 void (*toggle_ext_pause)(struct fsldma_chan *fsl_chan, int enable); 153 void (*toggle_ext_pause)(struct fsldma_chan *fsl_chan, int enable);
145 void (*toggle_ext_start)(struct fsldma_chan *fsl_chan, int enable); 154 void (*toggle_ext_start)(struct fsldma_chan *fsl_chan, int enable);