crypto: atmel-sha - add support for latest release of the IP (0x410)

Updates from IP release 0x320 to 0x400:
 - add DMA support (previous IP revision use PDC)
 - add DMA double input buffer support
 - add SHA224 support

Update from IP release 0x400 to 0x410:
 - add SHA384 and SHA512 support

Signed-off-by: Nicolas Royer <nicolas@eukrea.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: Eric Bénard <eric@eukrea.com>
Tested-by: Eric Bénard <eric@eukrea.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

3 files changed, 497 insertions, 104 deletions

diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
index 87ec4d027c25..e66fb0a332d4 100644
--- a/drivers/crypto/Kconfig
+++ b/drivers/crypto/Kconfig
@@ -361,15 +361,17 @@ config CRYPTO_DEV_ATMEL_TDES
           will be called atmel-tdes.
 
 config CRYPTO_DEV_ATMEL_SHA
-        tristate "Support for Atmel SHA1/SHA256 hw accelerator"
+        tristate "Support for Atmel SHA hw accelerator"
         depends on ARCH_AT91
         select CRYPTO_SHA1
         select CRYPTO_SHA256
+        select CRYPTO_SHA512
         select CRYPTO_ALGAPI
         help
-          Some Atmel processors have SHA1/SHA256 hw accelerator.
+          Some Atmel processors have SHA1/SHA224/SHA256/SHA384/SHA512
+          hw accelerator.
           Select this if you want to use the Atmel module for
-          SHA1/SHA256 algorithms.
+          SHA1/SHA224/SHA256/SHA384/SHA512 algorithms.
 
           To compile this driver as a module, choose M here: the module
           will be called atmel-sha.
diff --git a/drivers/crypto/atmel-sha-regs.h b/drivers/crypto/atmel-sha-regs.h
index dc53a20d7da1..83b2d7425666 100644
--- a/drivers/crypto/atmel-sha-regs.h
+++ b/drivers/crypto/atmel-sha-regs.h
@@ -14,10 +14,13 @@
 #define SHA_MR_MODE_MANUAL              0x0
 #define SHA_MR_MODE_AUTO                0x1
 #define SHA_MR_MODE_PDC                 0x2
-#define SHA_MR_DUALBUFF                 (1 << 3)
 #define SHA_MR_PROCDLY                  (1 << 4)
 #define SHA_MR_ALGO_SHA1                (0 << 8)
 #define SHA_MR_ALGO_SHA256              (1 << 8)
+#define SHA_MR_ALGO_SHA384              (2 << 8)
+#define SHA_MR_ALGO_SHA512              (3 << 8)
+#define SHA_MR_ALGO_SHA224              (4 << 8)
+#define SHA_MR_DUALBUFF                 (1 << 16)
 
 #define SHA_IER                         0x10
 #define SHA_IDR                         0x14
@@ -33,6 +36,8 @@
 #define SHA_ISR_URAT_MR                 (0x2 << 12)
 #define SHA_ISR_URAT_WO                 (0x5 << 12)
 
+#define SHA_HW_VERSION          0xFC
+
 #define SHA_TPR                         0x108
 #define SHA_TCR                         0x10C
 #define SHA_TNPR                        0x118
diff --git a/drivers/crypto/atmel-sha.c b/drivers/crypto/atmel-sha.c
index 4918e9424d31..eaed8bf183bc 100644
--- a/drivers/crypto/atmel-sha.c
+++ b/drivers/crypto/atmel-sha.c
@@ -38,6 +38,7 @@
 #include <crypto/sha.h>
 #include <crypto/hash.h>
 #include <crypto/internal/hash.h>
+#include <linux/platform_data/crypto-atmel.h>
 #include "atmel-sha-regs.h"
 
 /* SHA flags */
@@ -52,11 +53,12 @@
 #define SHA_FLAGS_FINUP         BIT(16)
 #define SHA_FLAGS_SG            BIT(17)
 #define SHA_FLAGS_SHA1          BIT(18)
-#define SHA_FLAGS_SHA256        BIT(19)
-#define SHA_FLAGS_ERROR         BIT(20)
-#define SHA_FLAGS_PAD           BIT(21)
-
-#define SHA_FLAGS_DUALBUFF      BIT(24)
+#define SHA_FLAGS_SHA224        BIT(19)
+#define SHA_FLAGS_SHA256        BIT(20)
+#define SHA_FLAGS_SHA384        BIT(21)
+#define SHA_FLAGS_SHA512        BIT(22)
+#define SHA_FLAGS_ERROR         BIT(23)
+#define SHA_FLAGS_PAD           BIT(24)
 
 #define SHA_OP_UPDATE   1
 #define SHA_OP_FINAL    2
@@ -65,6 +67,12 @@
 
 #define ATMEL_SHA_DMA_THRESHOLD         56
 
+struct atmel_sha_caps {
+        bool    has_dma;
+        bool    has_dualbuff;
+        bool    has_sha224;
+        bool    has_sha_384_512;
+};
 
 struct atmel_sha_dev;
 
@@ -73,8 +81,8 @@ struct atmel_sha_reqctx {
         unsigned long   flags;
         unsigned long   op;
 
-        u8      digest[SHA256_DIGEST_SIZE] __aligned(sizeof(u32));
-        size_t  digcnt;
+        u8      digest[SHA512_DIGEST_SIZE] __aligned(sizeof(u32));
+        u64     digcnt[2];
         size_t  bufcnt;
         size_t  buflen;
         dma_addr_t      dma_addr;
@@ -84,6 +92,8 @@ struct atmel_sha_reqctx {
         unsigned int    offset; /* offset in current sg */
         unsigned int    total;  /* total request */
 
+        size_t block_size;
+
         u8      buffer[0] __aligned(sizeof(u32));
 };
 
@@ -97,7 +107,12 @@ struct atmel_sha_ctx {
 
 };
 
-#define ATMEL_SHA_QUEUE_LENGTH  1
+#define ATMEL_SHA_QUEUE_LENGTH  50
+
+struct atmel_sha_dma {
+        struct dma_chan                 *chan;
+        struct dma_slave_config dma_conf;
+};
 
 struct atmel_sha_dev {
         struct list_head        list;
@@ -114,6 +129,12 @@ struct atmel_sha_dev {
         unsigned long           flags;
         struct crypto_queue     queue;
         struct ahash_request    *req;
+
+        struct atmel_sha_dma    dma_lch_in;
+
+        struct atmel_sha_caps   caps;
+
+        u32     hw_version;
 };
 
 struct atmel_sha_drv {
@@ -137,14 +158,6 @@ static inline void atmel_sha_write(struct atmel_sha_dev *dd,
         writel_relaxed(value, dd->io_base + offset);
 }
 
-static void atmel_sha_dualbuff_test(struct atmel_sha_dev *dd)
-{
-        atmel_sha_write(dd, SHA_MR, SHA_MR_DUALBUFF);
-
-        if (atmel_sha_read(dd, SHA_MR) & SHA_MR_DUALBUFF)
-                dd->flags |= SHA_FLAGS_DUALBUFF;
-}
-
 static size_t atmel_sha_append_sg(struct atmel_sha_reqctx *ctx)
 {
         size_t count;
@@ -176,31 +189,58 @@ static size_t atmel_sha_append_sg(struct atmel_sha_reqctx *ctx)
 }
 
 /*
- * The purpose of this padding is to ensure that the padded message
- * is a multiple of 512 bits. The bit "1" is appended at the end of
- * the message followed by "padlen-1" zero bits. Then a 64 bits block
- * equals to the message length in bits is appended.
+ * The purpose of this padding is to ensure that the padded message is a
+ * multiple of 512 bits (SHA1/SHA224/SHA256) or 1024 bits (SHA384/SHA512).
+ * The bit "1" is appended at the end of the message followed by
+ * "padlen-1" zero bits. Then a 64 bits block (SHA1/SHA224/SHA256) or
+ * 128 bits block (SHA384/SHA512) equals to the message length in bits
+ * is appended.
  *
- * padlen is calculated as followed:
+ * For SHA1/SHA224/SHA256, padlen is calculated as followed:
  *  - if message length < 56 bytes then padlen = 56 - message length
  *  - else padlen = 64 + 56 - message length
+ *
+ * For SHA384/SHA512, padlen is calculated as followed:
+ *  - if message length < 112 bytes then padlen = 112 - message length
+ *  - else padlen = 128 + 112 - message length
  */
 static void atmel_sha_fill_padding(struct atmel_sha_reqctx *ctx, int length)
 {
         unsigned int index, padlen;
-        u64 bits;
-        u64 size;
-
-        bits = (ctx->bufcnt + ctx->digcnt + length) << 3;
-        size = cpu_to_be64(bits);
-
-        index = ctx->bufcnt & 0x3f;
-        padlen = (index < 56) ? (56 - index) : ((64+56) - index);
-        *(ctx->buffer + ctx->bufcnt) = 0x80;
-        memset(ctx->buffer + ctx->bufcnt + 1, 0, padlen-1);
-        memcpy(ctx->buffer + ctx->bufcnt + padlen, &size, 8);
-        ctx->bufcnt += padlen + 8;
-        ctx->flags |= SHA_FLAGS_PAD;
+        u64 bits[2];
+        u64 size[2];
+
+        size[0] = ctx->digcnt[0];
+        size[1] = ctx->digcnt[1];
+
+        size[0] += ctx->bufcnt;
+        if (size[0] < ctx->bufcnt)
+                size[1]++;
+
+        size[0] += length;
+        if (size[0]  < length)
+                size[1]++;
+
+        bits[1] = cpu_to_be64(size[0] << 3);
+        bits[0] = cpu_to_be64(size[1] << 3 | size[0] >> 61);
+
+        if (ctx->flags & (SHA_FLAGS_SHA384 | SHA_FLAGS_SHA512)) {
+                index = ctx->bufcnt & 0x7f;
+                padlen = (index < 112) ? (112 - index) : ((128+112) - index);
+                *(ctx->buffer + ctx->bufcnt) = 0x80;
+                memset(ctx->buffer + ctx->bufcnt + 1, 0, padlen-1);
+                memcpy(ctx->buffer + ctx->bufcnt + padlen, bits, 16);
+                ctx->bufcnt += padlen + 16;
+                ctx->flags |= SHA_FLAGS_PAD;
+        } else {
+                index = ctx->bufcnt & 0x3f;
+                padlen = (index < 56) ? (56 - index) : ((64+56) - index);
+                *(ctx->buffer + ctx->bufcnt) = 0x80;
+                memset(ctx->buffer + ctx->bufcnt + 1, 0, padlen-1);
+                memcpy(ctx->buffer + ctx->bufcnt + padlen, &bits[1], 8);
+                ctx->bufcnt += padlen + 8;
+                ctx->flags |= SHA_FLAGS_PAD;
+        }
 }
 
 static int atmel_sha_init(struct ahash_request *req)
@@ -231,13 +271,35 @@ static int atmel_sha_init(struct ahash_request *req)
         dev_dbg(dd->dev, "init: digest size: %d\n",
                 crypto_ahash_digestsize(tfm));
 
-        if (crypto_ahash_digestsize(tfm) == SHA1_DIGEST_SIZE)
+        switch (crypto_ahash_digestsize(tfm)) {
+        case SHA1_DIGEST_SIZE:
                 ctx->flags |= SHA_FLAGS_SHA1;
-        else if (crypto_ahash_digestsize(tfm) == SHA256_DIGEST_SIZE)
+                ctx->block_size = SHA1_BLOCK_SIZE;
+                break;
+        case SHA224_DIGEST_SIZE:
+                ctx->flags |= SHA_FLAGS_SHA224;
+                ctx->block_size = SHA224_BLOCK_SIZE;
+                break;
+        case SHA256_DIGEST_SIZE:
                 ctx->flags |= SHA_FLAGS_SHA256;
+                ctx->block_size = SHA256_BLOCK_SIZE;
+                break;
+        case SHA384_DIGEST_SIZE:
+                ctx->flags |= SHA_FLAGS_SHA384;
+                ctx->block_size = SHA384_BLOCK_SIZE;
+                break;
+        case SHA512_DIGEST_SIZE:
+                ctx->flags |= SHA_FLAGS_SHA512;
+                ctx->block_size = SHA512_BLOCK_SIZE;
+                break;
+        default:
+                return -EINVAL;
+                break;
+        }
 
         ctx->bufcnt = 0;
-        ctx->digcnt = 0;
+        ctx->digcnt[0] = 0;
+        ctx->digcnt[1] = 0;
         ctx->buflen = SHA_BUFFER_LEN;
 
         return 0;
@@ -249,19 +311,28 @@ static void atmel_sha_write_ctrl(struct atmel_sha_dev *dd, int dma)
         u32 valcr = 0, valmr = SHA_MR_MODE_AUTO;
 
         if (likely(dma)) {
-                atmel_sha_write(dd, SHA_IER, SHA_INT_TXBUFE);
+                if (!dd->caps.has_dma)
+                        atmel_sha_write(dd, SHA_IER, SHA_INT_TXBUFE);
                 valmr = SHA_MR_MODE_PDC;
-                if (dd->flags & SHA_FLAGS_DUALBUFF)
-                        valmr = SHA_MR_DUALBUFF;
+                if (dd->caps.has_dualbuff)
+                        valmr |= SHA_MR_DUALBUFF;
         } else {
                 atmel_sha_write(dd, SHA_IER, SHA_INT_DATARDY);
         }
 
-        if (ctx->flags & SHA_FLAGS_SHA256)
+        if (ctx->flags & SHA_FLAGS_SHA1)
+                valmr |= SHA_MR_ALGO_SHA1;
+        else if (ctx->flags & SHA_FLAGS_SHA224)
+                valmr |= SHA_MR_ALGO_SHA224;
+        else if (ctx->flags & SHA_FLAGS_SHA256)
                 valmr |= SHA_MR_ALGO_SHA256;
+        else if (ctx->flags & SHA_FLAGS_SHA384)
+                valmr |= SHA_MR_ALGO_SHA384;
+        else if (ctx->flags & SHA_FLAGS_SHA512)
+                valmr |= SHA_MR_ALGO_SHA512;
 
         /* Setting CR_FIRST only for the first iteration */
-        if (!ctx->digcnt)
+        if (!(ctx->digcnt[0] || ctx->digcnt[1]))
                 valcr = SHA_CR_FIRST;
 
         atmel_sha_write(dd, SHA_CR, valcr);
@@ -275,13 +346,15 @@ static int atmel_sha_xmit_cpu(struct atmel_sha_dev *dd, const u8 *buf,
         int count, len32;
         const u32 *buffer = (const u32 *)buf;
 
-        dev_dbg(dd->dev, "xmit_cpu: digcnt: %d, length: %d, final: %d\n",
-                                                ctx->digcnt, length, final);
+        dev_dbg(dd->dev, "xmit_cpu: digcnt: 0x%llx 0x%llx, length: %d, final: %d\n",
+                ctx->digcnt[1], ctx->digcnt[0], length, final);
 
         atmel_sha_write_ctrl(dd, 0);
 
         /* should be non-zero before next lines to disable clocks later */
-        ctx->digcnt += length;
+        ctx->digcnt[0] += length;
+        if (ctx->digcnt[0] < length)
+                ctx->digcnt[1]++;
 
         if (final)
                 dd->flags |= SHA_FLAGS_FINAL; /* catch last interrupt */
@@ -302,8 +375,8 @@ static int atmel_sha_xmit_pdc(struct atmel_sha_dev *dd, dma_addr_t dma_addr1,
         struct atmel_sha_reqctx *ctx = ahash_request_ctx(dd->req);
         int len32;
 
-        dev_dbg(dd->dev, "xmit_pdc: digcnt: %d, length: %d, final: %d\n",
-                                                ctx->digcnt, length1, final);
+        dev_dbg(dd->dev, "xmit_pdc: digcnt: 0x%llx 0x%llx, length: %d, final: %d\n",
+                ctx->digcnt[1], ctx->digcnt[0], length1, final);
 
         len32 = DIV_ROUND_UP(length1, sizeof(u32));
         atmel_sha_write(dd, SHA_PTCR, SHA_PTCR_TXTDIS);
@@ -317,7 +390,9 @@ static int atmel_sha_xmit_pdc(struct atmel_sha_dev *dd, dma_addr_t dma_addr1,
         atmel_sha_write_ctrl(dd, 1);
 
         /* should be non-zero before next lines to disable clocks later */
-        ctx->digcnt += length1;
+        ctx->digcnt[0] += length1;
+        if (ctx->digcnt[0] < length1)
+                ctx->digcnt[1]++;
 
         if (final)
                 dd->flags |= SHA_FLAGS_FINAL; /* catch last interrupt */
@@ -330,6 +405,86 @@ static int atmel_sha_xmit_pdc(struct atmel_sha_dev *dd, dma_addr_t dma_addr1,
         return -EINPROGRESS;
 }
 
+static void atmel_sha_dma_callback(void *data)
+{
+        struct atmel_sha_dev *dd = data;
+
+        /* dma_lch_in - completed - wait DATRDY */
+        atmel_sha_write(dd, SHA_IER, SHA_INT_DATARDY);
+}
+
+static int atmel_sha_xmit_dma(struct atmel_sha_dev *dd, dma_addr_t dma_addr1,
+                size_t length1, dma_addr_t dma_addr2, size_t length2, int final)
+{
+        struct atmel_sha_reqctx *ctx = ahash_request_ctx(dd->req);
+        struct dma_async_tx_descriptor  *in_desc;
+        struct scatterlist sg[2];
+
+        dev_dbg(dd->dev, "xmit_dma: digcnt: 0x%llx 0x%llx, length: %d, final: %d\n",
+                ctx->digcnt[1], ctx->digcnt[0], length1, final);
+
+        if (ctx->flags & (SHA_FLAGS_SHA1 | SHA_FLAGS_SHA224 |
+                        SHA_FLAGS_SHA256)) {
+                dd->dma_lch_in.dma_conf.src_maxburst = 16;
+                dd->dma_lch_in.dma_conf.dst_maxburst = 16;
+        } else {
+                dd->dma_lch_in.dma_conf.src_maxburst = 32;
+                dd->dma_lch_in.dma_conf.dst_maxburst = 32;
+        }
+
+        dmaengine_slave_config(dd->dma_lch_in.chan, &dd->dma_lch_in.dma_conf);
+
+        if (length2) {
+                sg_init_table(sg, 2);
+                sg_dma_address(&sg[0]) = dma_addr1;
+                sg_dma_len(&sg[0]) = length1;
+                sg_dma_address(&sg[1]) = dma_addr2;
+                sg_dma_len(&sg[1]) = length2;
+                in_desc = dmaengine_prep_slave_sg(dd->dma_lch_in.chan, sg, 2,
+                        DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
+        } else {
+                sg_init_table(sg, 1);
+                sg_dma_address(&sg[0]) = dma_addr1;
+                sg_dma_len(&sg[0]) = length1;
+                in_desc = dmaengine_prep_slave_sg(dd->dma_lch_in.chan, sg, 1,
+                        DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
+        }
+        if (!in_desc)
+                return -EINVAL;
+
+        in_desc->callback = atmel_sha_dma_callback;
+        in_desc->callback_param = dd;
+
+        atmel_sha_write_ctrl(dd, 1);
+
+        /* should be non-zero before next lines to disable clocks later */
+        ctx->digcnt[0] += length1;
+        if (ctx->digcnt[0] < length1)
+                ctx->digcnt[1]++;
+
+        if (final)
+                dd->flags |= SHA_FLAGS_FINAL; /* catch last interrupt */
+
+        dd->flags |=  SHA_FLAGS_DMA_ACTIVE;
+
+        /* Start DMA transfer */
+        dmaengine_submit(in_desc);
+        dma_async_issue_pending(dd->dma_lch_in.chan);
+
+        return -EINPROGRESS;
+}
+
+static int atmel_sha_xmit_start(struct atmel_sha_dev *dd, dma_addr_t dma_addr1,
+                size_t length1, dma_addr_t dma_addr2, size_t length2, int final)
+{
+        if (dd->caps.has_dma)
+                return atmel_sha_xmit_dma(dd, dma_addr1, length1,
+                                dma_addr2, length2, final);
+        else
+                return atmel_sha_xmit_pdc(dd, dma_addr1, length1,
+                                dma_addr2, length2, final);
+}
+
 static int atmel_sha_update_cpu(struct atmel_sha_dev *dd)
 {
         struct atmel_sha_reqctx *ctx = ahash_request_ctx(dd->req);
@@ -337,7 +492,6 @@ static int atmel_sha_update_cpu(struct atmel_sha_dev *dd)
 
         atmel_sha_append_sg(ctx);
         atmel_sha_fill_padding(ctx, 0);
-
         bufcnt = ctx->bufcnt;
         ctx->bufcnt = 0;
 
@@ -349,17 +503,17 @@ static int atmel_sha_xmit_dma_map(struct atmel_sha_dev *dd,
                                         size_t length, int final)
 {
         ctx->dma_addr = dma_map_single(dd->dev, ctx->buffer,
-                                ctx->buflen + SHA1_BLOCK_SIZE, DMA_TO_DEVICE);
+                                ctx->buflen + ctx->block_size, DMA_TO_DEVICE);
         if (dma_mapping_error(dd->dev, ctx->dma_addr)) {
                 dev_err(dd->dev, "dma %u bytes error\n", ctx->buflen +
-                                SHA1_BLOCK_SIZE);
+                                ctx->block_size);
                 return -EINVAL;
         }
 
         ctx->flags &= ~SHA_FLAGS_SG;
 
         /* next call does not fail... so no unmap in the case of error */
-        return atmel_sha_xmit_pdc(dd, ctx->dma_addr, length, 0, 0, final);
+        return atmel_sha_xmit_start(dd, ctx->dma_addr, length, 0, 0, final);
 }
 
 static int atmel_sha_update_dma_slow(struct atmel_sha_dev *dd)
@@ -372,8 +526,8 @@ static int atmel_sha_update_dma_slow(struct atmel_sha_dev *dd)
 
         final = (ctx->flags & SHA_FLAGS_FINUP) && !ctx->total;
 
-        dev_dbg(dd->dev, "slow: bufcnt: %u, digcnt: %d, final: %d\n",
-                                         ctx->bufcnt, ctx->digcnt, final);
+        dev_dbg(dd->dev, "slow: bufcnt: %u, digcnt: 0x%llx 0x%llx, final: %d\n",
+                 ctx->bufcnt, ctx->digcnt[1], ctx->digcnt[0], final);
 
         if (final)
                 atmel_sha_fill_padding(ctx, 0);
@@ -400,30 +554,25 @@ static int atmel_sha_update_dma_start(struct atmel_sha_dev *dd)
         if (ctx->bufcnt || ctx->offset)
                 return atmel_sha_update_dma_slow(dd);
 
-        dev_dbg(dd->dev, "fast: digcnt: %d, bufcnt: %u, total: %u\n",
-                        ctx->digcnt, ctx->bufcnt, ctx->total);
+        dev_dbg(dd->dev, "fast: digcnt: 0x%llx 0x%llx, bufcnt: %u, total: %u\n",
+                ctx->digcnt[1], ctx->digcnt[0], ctx->bufcnt, ctx->total);
 
         sg = ctx->sg;
 
         if (!IS_ALIGNED(sg->offset, sizeof(u32)))
                 return atmel_sha_update_dma_slow(dd);
 
-        if (!sg_is_last(sg) && !IS_ALIGNED(sg->length, SHA1_BLOCK_SIZE))
-                /* size is not SHA1_BLOCK_SIZE aligned */
+        if (!sg_is_last(sg) && !IS_ALIGNED(sg->length, ctx->block_size))
+                /* size is not ctx->block_size aligned */
                 return atmel_sha_update_dma_slow(dd);
 
         length = min(ctx->total, sg->length);
 
         if (sg_is_last(sg)) {
                 if (!(ctx->flags & SHA_FLAGS_FINUP)) {
-                        /* not last sg must be SHA1_BLOCK_SIZE aligned */
-                        tail = length & (SHA1_BLOCK_SIZE - 1);
+                        /* not last sg must be ctx->block_size aligned */
+                        tail = length & (ctx->block_size - 1);
                         length -= tail;
-                        if (length == 0) {
-                                /* offset where to start slow */
-                                ctx->offset = length;
-                                return atmel_sha_update_dma_slow(dd);
-                        }
                 }
         }
 
@@ -434,7 +583,7 @@ static int atmel_sha_update_dma_start(struct atmel_sha_dev *dd)
 
         /* Add padding */
         if (final) {
-                tail = length & (SHA1_BLOCK_SIZE - 1);
+                tail = length & (ctx->block_size - 1);
                 length -= tail;
                 ctx->total += tail;
                 ctx->offset = length; /* offset where to start slow */
@@ -445,10 +594,10 @@ static int atmel_sha_update_dma_start(struct atmel_sha_dev *dd)
                 atmel_sha_fill_padding(ctx, length);
 
                 ctx->dma_addr = dma_map_single(dd->dev, ctx->buffer,
-                        ctx->buflen + SHA1_BLOCK_SIZE, DMA_TO_DEVICE);
+                        ctx->buflen + ctx->block_size, DMA_TO_DEVICE);
                 if (dma_mapping_error(dd->dev, ctx->dma_addr)) {
                         dev_err(dd->dev, "dma %u bytes error\n",
-                                ctx->buflen + SHA1_BLOCK_SIZE);
+                                ctx->buflen + ctx->block_size);
                         return -EINVAL;
                 }
 
@@ -456,7 +605,7 @@ static int atmel_sha_update_dma_start(struct atmel_sha_dev *dd)
                         ctx->flags &= ~SHA_FLAGS_SG;
                         count = ctx->bufcnt;
                         ctx->bufcnt = 0;
-                        return atmel_sha_xmit_pdc(dd, ctx->dma_addr, count, 0,
+                        return atmel_sha_xmit_start(dd, ctx->dma_addr, count, 0,
                                         0, final);
                 } else {
                         ctx->sg = sg;
@@ -470,7 +619,7 @@ static int atmel_sha_update_dma_start(struct atmel_sha_dev *dd)
 
                         count = ctx->bufcnt;
                         ctx->bufcnt = 0;
-                        return atmel_sha_xmit_pdc(dd, sg_dma_address(ctx->sg),
+                        return atmel_sha_xmit_start(dd, sg_dma_address(ctx->sg),
                                         length, ctx->dma_addr, count, final);
                 }
         }
@@ -483,7 +632,7 @@ static int atmel_sha_update_dma_start(struct atmel_sha_dev *dd)
         ctx->flags |= SHA_FLAGS_SG;
 
         /* next call does not fail... so no unmap in the case of error */
-        return atmel_sha_xmit_pdc(dd, sg_dma_address(ctx->sg), length, 0,
+        return atmel_sha_xmit_start(dd, sg_dma_address(ctx->sg), length, 0,
                                                                 0, final);
 }
 
@@ -498,12 +647,13 @@ static int atmel_sha_update_dma_stop(struct atmel_sha_dev *dd)
                         if (ctx->sg)
                                 ctx->offset = 0;
                 }
-                if (ctx->flags & SHA_FLAGS_PAD)
+                if (ctx->flags & SHA_FLAGS_PAD) {
                         dma_unmap_single(dd->dev, ctx->dma_addr,
-                                ctx->buflen + SHA1_BLOCK_SIZE, DMA_TO_DEVICE);
+                                ctx->buflen + ctx->block_size, DMA_TO_DEVICE);
+                }
         } else {
                 dma_unmap_single(dd->dev, ctx->dma_addr, ctx->buflen +
-                                                SHA1_BLOCK_SIZE, DMA_TO_DEVICE);
+                                                ctx->block_size, DMA_TO_DEVICE);
         }
 
         return 0;
@@ -515,8 +665,8 @@ static int atmel_sha_update_req(struct atmel_sha_dev *dd)
         struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
         int err;
 
-        dev_dbg(dd->dev, "update_req: total: %u, digcnt: %d, finup: %d\n",
-                 ctx->total, ctx->digcnt, (ctx->flags & SHA_FLAGS_FINUP) != 0);
+        dev_dbg(dd->dev, "update_req: total: %u, digcnt: 0x%llx 0x%llx\n",
+                ctx->total, ctx->digcnt[1], ctx->digcnt[0]);
 
         if (ctx->flags & SHA_FLAGS_CPU)
                 err = atmel_sha_update_cpu(dd);
@@ -524,8 +674,8 @@ static int atmel_sha_update_req(struct atmel_sha_dev *dd)
                 err = atmel_sha_update_dma_start(dd);
 
         /* wait for dma completion before can take more data */
-        dev_dbg(dd->dev, "update: err: %d, digcnt: %d\n",
-                        err, ctx->digcnt);
+        dev_dbg(dd->dev, "update: err: %d, digcnt: 0x%llx 0%llx\n",
+                        err, ctx->digcnt[1], ctx->digcnt[0]);
 
         return err;
 }
@@ -562,12 +712,21 @@ static void atmel_sha_copy_hash(struct ahash_request *req)
         u32 *hash = (u32 *)ctx->digest;
         int i;
 
-        if (likely(ctx->flags & SHA_FLAGS_SHA1))
+        if (ctx->flags & SHA_FLAGS_SHA1)
                 for (i = 0; i < SHA1_DIGEST_SIZE / sizeof(u32); i++)
                         hash[i] = atmel_sha_read(ctx->dd, SHA_REG_DIGEST(i));
-        else
+        else if (ctx->flags & SHA_FLAGS_SHA224)
+                for (i = 0; i < SHA224_DIGEST_SIZE / sizeof(u32); i++)
+                        hash[i] = atmel_sha_read(ctx->dd, SHA_REG_DIGEST(i));
+        else if (ctx->flags & SHA_FLAGS_SHA256)
                 for (i = 0; i < SHA256_DIGEST_SIZE / sizeof(u32); i++)
                         hash[i] = atmel_sha_read(ctx->dd, SHA_REG_DIGEST(i));
+        else if (ctx->flags & SHA_FLAGS_SHA384)
+                for (i = 0; i < SHA384_DIGEST_SIZE / sizeof(u32); i++)
+                        hash[i] = atmel_sha_read(ctx->dd, SHA_REG_DIGEST(i));
+        else
+                for (i = 0; i < SHA512_DIGEST_SIZE / sizeof(u32); i++)
+                        hash[i] = atmel_sha_read(ctx->dd, SHA_REG_DIGEST(i));
 }
 
 static void atmel_sha_copy_ready_hash(struct ahash_request *req)
@@ -577,10 +736,16 @@ static void atmel_sha_copy_ready_hash(struct ahash_request *req)
         if (!req->result)
                 return;
 
-        if (likely(ctx->flags & SHA_FLAGS_SHA1))
+        if (ctx->flags & SHA_FLAGS_SHA1)
                 memcpy(req->result, ctx->digest, SHA1_DIGEST_SIZE);
-        else
+        else if (ctx->flags & SHA_FLAGS_SHA224)
+                memcpy(req->result, ctx->digest, SHA224_DIGEST_SIZE);
+        else if (ctx->flags & SHA_FLAGS_SHA256)
                 memcpy(req->result, ctx->digest, SHA256_DIGEST_SIZE);
+        else if (ctx->flags & SHA_FLAGS_SHA384)
+                memcpy(req->result, ctx->digest, SHA384_DIGEST_SIZE);
+        else
+                memcpy(req->result, ctx->digest, SHA512_DIGEST_SIZE);
 }
 
 static int atmel_sha_finish(struct ahash_request *req)
@@ -589,11 +754,11 @@ static int atmel_sha_finish(struct ahash_request *req)
         struct atmel_sha_dev *dd = ctx->dd;
         int err = 0;
 
-        if (ctx->digcnt)
+        if (ctx->digcnt[0] || ctx->digcnt[1])
                 atmel_sha_copy_ready_hash(req);
 
-        dev_dbg(dd->dev, "digcnt: %d, bufcnt: %d\n", ctx->digcnt,
-                ctx->bufcnt);
+        dev_dbg(dd->dev, "digcnt: 0x%llx 0x%llx, bufcnt: %d\n", ctx->digcnt[1],
+                ctx->digcnt[0], ctx->bufcnt);
 
         return err;
 }
@@ -628,9 +793,8 @@ static int atmel_sha_hw_init(struct atmel_sha_dev *dd)
 {
         clk_prepare_enable(dd->iclk);
 
-        if (SHA_FLAGS_INIT & dd->flags) {
+        if (!(SHA_FLAGS_INIT & dd->flags)) {
                 atmel_sha_write(dd, SHA_CR, SHA_CR_SWRST);
-                atmel_sha_dualbuff_test(dd);
                 dd->flags |= SHA_FLAGS_INIT;
                 dd->err = 0;
         }
@@ -638,6 +802,23 @@ static int atmel_sha_hw_init(struct atmel_sha_dev *dd)
         return 0;
 }
 
+static inline unsigned int atmel_sha_get_version(struct atmel_sha_dev *dd)
+{
+        return atmel_sha_read(dd, SHA_HW_VERSION) & 0x00000fff;
+}
+
+static void atmel_sha_hw_version_init(struct atmel_sha_dev *dd)
+{
+        atmel_sha_hw_init(dd);
+
+        dd->hw_version = atmel_sha_get_version(dd);
+
+        dev_info(dd->dev,
+                        "version: 0x%x\n", dd->hw_version);
+
+        clk_disable_unprepare(dd->iclk);
+}
+
 static int atmel_sha_handle_queue(struct atmel_sha_dev *dd,
                                   struct ahash_request *req)
 {
@@ -682,10 +863,9 @@ static int atmel_sha_handle_queue(struct atmel_sha_dev *dd,
 
         if (ctx->op == SHA_OP_UPDATE) {
                 err = atmel_sha_update_req(dd);
-                if (err != -EINPROGRESS && (ctx->flags & SHA_FLAGS_FINUP)) {
+                if (err != -EINPROGRESS && (ctx->flags & SHA_FLAGS_FINUP))
                         /* no final() after finup() */
                         err = atmel_sha_final_req(dd);
-                }
         } else if (ctx->op == SHA_OP_FINAL) {
                 err = atmel_sha_final_req(dd);
         }
@@ -808,7 +988,7 @@ static int atmel_sha_cra_init_alg(struct crypto_tfm *tfm, const char *alg_base)
         }
         crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
                                  sizeof(struct atmel_sha_reqctx) +
-                                 SHA_BUFFER_LEN + SHA256_BLOCK_SIZE);
+                                 SHA_BUFFER_LEN + SHA512_BLOCK_SIZE);
 
         return 0;
 }
@@ -826,7 +1006,7 @@ static void atmel_sha_cra_exit(struct crypto_tfm *tfm)
         tctx->fallback = NULL;
 }
 
-static struct ahash_alg sha_algs[] = {
+static struct ahash_alg sha_1_256_algs[] = {
 {
         .init           = atmel_sha_init,
         .update         = atmel_sha_update,
@@ -875,6 +1055,79 @@ static struct ahash_alg sha_algs[] = {
 },
 };
 
+static struct ahash_alg sha_224_alg = {
+        .init           = atmel_sha_init,
+        .update         = atmel_sha_update,
+        .final          = atmel_sha_final,
+        .finup          = atmel_sha_finup,
+        .digest         = atmel_sha_digest,
+        .halg = {
+                .digestsize     = SHA224_DIGEST_SIZE,
+                .base   = {
+                        .cra_name               = "sha224",
+                        .cra_driver_name        = "atmel-sha224",
+                        .cra_priority           = 100,
+                        .cra_flags              = CRYPTO_ALG_ASYNC |
+                                                CRYPTO_ALG_NEED_FALLBACK,
+                        .cra_blocksize          = SHA224_BLOCK_SIZE,
+                        .cra_ctxsize            = sizeof(struct atmel_sha_ctx),
+                        .cra_alignmask          = 0,
+                        .cra_module             = THIS_MODULE,
+                        .cra_init               = atmel_sha_cra_init,
+                        .cra_exit               = atmel_sha_cra_exit,
+                }
+        }
+};
+
+static struct ahash_alg sha_384_512_algs[] = {
+{
+        .init           = atmel_sha_init,
+        .update         = atmel_sha_update,
+        .final          = atmel_sha_final,
+        .finup          = atmel_sha_finup,
+        .digest         = atmel_sha_digest,
+        .halg = {
+                .digestsize     = SHA384_DIGEST_SIZE,
+                .base   = {
+                        .cra_name               = "sha384",
+                        .cra_driver_name        = "atmel-sha384",
+                        .cra_priority           = 100,
+                        .cra_flags              = CRYPTO_ALG_ASYNC |
+                                                CRYPTO_ALG_NEED_FALLBACK,
+                        .cra_blocksize          = SHA384_BLOCK_SIZE,
+                        .cra_ctxsize            = sizeof(struct atmel_sha_ctx),
+                        .cra_alignmask          = 0x3,
+                        .cra_module             = THIS_MODULE,
+                        .cra_init               = atmel_sha_cra_init,
+                        .cra_exit               = atmel_sha_cra_exit,
+                }
+        }
+},
+{
+        .init           = atmel_sha_init,
+        .update         = atmel_sha_update,
+        .final          = atmel_sha_final,
+        .finup          = atmel_sha_finup,
+        .digest         = atmel_sha_digest,
+        .halg = {
+                .digestsize     = SHA512_DIGEST_SIZE,
+                .base   = {
+                        .cra_name               = "sha512",
+                        .cra_driver_name        = "atmel-sha512",
+                        .cra_priority           = 100,
+                        .cra_flags              = CRYPTO_ALG_ASYNC |
+                                                CRYPTO_ALG_NEED_FALLBACK,
+                        .cra_blocksize          = SHA512_BLOCK_SIZE,
+                        .cra_ctxsize            = sizeof(struct atmel_sha_ctx),
+                        .cra_alignmask          = 0x3,
+                        .cra_module             = THIS_MODULE,
+                        .cra_init               = atmel_sha_cra_init,
+                        .cra_exit               = atmel_sha_cra_exit,
+                }
+        }
+},
+};
+
 static void atmel_sha_done_task(unsigned long data)
 {
         struct atmel_sha_dev *dd = (struct atmel_sha_dev *)data;
@@ -941,32 +1194,142 @@ static void atmel_sha_unregister_algs(struct atmel_sha_dev *dd)
 {
         int i;
 
-        for (i = 0; i < ARRAY_SIZE(sha_algs); i++)
-                crypto_unregister_ahash(&sha_algs[i]);
+        for (i = 0; i < ARRAY_SIZE(sha_1_256_algs); i++)
+                crypto_unregister_ahash(&sha_1_256_algs[i]);
+
+        if (dd->caps.has_sha224)
+                crypto_unregister_ahash(&sha_224_alg);
+
+        if (dd->caps.has_sha_384_512) {
+                for (i = 0; i < ARRAY_SIZE(sha_384_512_algs); i++)
+                        crypto_unregister_ahash(&sha_384_512_algs[i]);
+        }
 }
 
 static int atmel_sha_register_algs(struct atmel_sha_dev *dd)
 {
         int err, i, j;
 
-        for (i = 0; i < ARRAY_SIZE(sha_algs); i++) {
-                err = crypto_register_ahash(&sha_algs[i]);
+        for (i = 0; i < ARRAY_SIZE(sha_1_256_algs); i++) {
+                err = crypto_register_ahash(&sha_1_256_algs[i]);
                 if (err)
-                        goto err_sha_algs;
+                        goto err_sha_1_256_algs;
+        }
+
+        if (dd->caps.has_sha224) {
+                err = crypto_register_ahash(&sha_224_alg);
+                if (err)
+                        goto err_sha_224_algs;
+        }
+
+        if (dd->caps.has_sha_384_512) {
+                for (i = 0; i < ARRAY_SIZE(sha_384_512_algs); i++) {
+                        err = crypto_register_ahash(&sha_384_512_algs[i]);
+                        if (err)
+                                goto err_sha_384_512_algs;
+                }
         }
 
         return 0;
 
-err_sha_algs:
+err_sha_384_512_algs:
+        for (j = 0; j < i; j++)
+                crypto_unregister_ahash(&sha_384_512_algs[j]);
+        crypto_unregister_ahash(&sha_224_alg);
+err_sha_224_algs:
+        i = ARRAY_SIZE(sha_1_256_algs);
+err_sha_1_256_algs:
         for (j = 0; j < i; j++)
-                crypto_unregister_ahash(&sha_algs[j]);
+                crypto_unregister_ahash(&sha_1_256_algs[j]);
 
         return err;
 }
 
+static bool atmel_sha_filter(struct dma_chan *chan, void *slave)
+{
+        struct at_dma_slave     *sl = slave;
+
+        if (sl && sl->dma_dev == chan->device->dev) {
+                chan->private = sl;
+                return true;
+        } else {
+                return false;
+        }
+}
+
+static int atmel_sha_dma_init(struct atmel_sha_dev *dd,
+                                struct crypto_platform_data *pdata)
+{
+        int err = -ENOMEM;
+        dma_cap_mask_t mask_in;
+
+        if (pdata && pdata->dma_slave->rxdata.dma_dev) {
+                /* Try to grab DMA channel */
+                dma_cap_zero(mask_in);
+                dma_cap_set(DMA_SLAVE, mask_in);
+
+                dd->dma_lch_in.chan = dma_request_channel(mask_in,
+                                atmel_sha_filter, &pdata->dma_slave->rxdata);
+
+                if (!dd->dma_lch_in.chan)
+                        return err;
+
+                dd->dma_lch_in.dma_conf.direction = DMA_MEM_TO_DEV;
+                dd->dma_lch_in.dma_conf.dst_addr = dd->phys_base +
+                        SHA_REG_DIN(0);
+                dd->dma_lch_in.dma_conf.src_maxburst = 1;
+                dd->dma_lch_in.dma_conf.src_addr_width =
+                        DMA_SLAVE_BUSWIDTH_4_BYTES;
+                dd->dma_lch_in.dma_conf.dst_maxburst = 1;
+                dd->dma_lch_in.dma_conf.dst_addr_width =
+                        DMA_SLAVE_BUSWIDTH_4_BYTES;
+                dd->dma_lch_in.dma_conf.device_fc = false;
+
+                return 0;
+        }
+
+        return -ENODEV;
+}
+
+static void atmel_sha_dma_cleanup(struct atmel_sha_dev *dd)
+{
+        dma_release_channel(dd->dma_lch_in.chan);
+}
+
+static void atmel_sha_get_cap(struct atmel_sha_dev *dd)
+{
+
+        dd->caps.has_dma = 0;
+        dd->caps.has_dualbuff = 0;
+        dd->caps.has_sha224 = 0;
+        dd->caps.has_sha_384_512 = 0;
+
+        /* keep only major version number */
+        switch (dd->hw_version & 0xff0) {
+        case 0x410:
+                dd->caps.has_dma = 1;
+                dd->caps.has_dualbuff = 1;
+                dd->caps.has_sha224 = 1;
+                dd->caps.has_sha_384_512 = 1;
+                break;
+        case 0x400:
+                dd->caps.has_dma = 1;
+                dd->caps.has_dualbuff = 1;
+                dd->caps.has_sha224 = 1;
+                break;
+        case 0x320:
+                break;
+        default:
+                dev_warn(dd->dev,
+                                "Unmanaged sha version, set minimum capabilities\n");
+                break;
+        }
+}
+
 static int atmel_sha_probe(struct platform_device *pdev)
 {
         struct atmel_sha_dev *sha_dd;
+        struct crypto_platform_data     *pdata;
         struct device *dev = &pdev->dev;
         struct resource *sha_res;
         unsigned long sha_phys_size;
@@ -1018,7 +1381,7 @@ static int atmel_sha_probe(struct platform_device *pdev)
         }
 
         /* Initializing the clock */
-        sha_dd->iclk = clk_get(&pdev->dev, NULL);
+        sha_dd->iclk = clk_get(&pdev->dev, "sha_clk");
         if (IS_ERR(sha_dd->iclk)) {
                 dev_err(dev, "clock intialization failed.\n");
                 err = PTR_ERR(sha_dd->iclk);
@@ -1032,6 +1395,22 @@ static int atmel_sha_probe(struct platform_device *pdev)
                 goto sha_io_err;
         }
 
+        atmel_sha_hw_version_init(sha_dd);
+
+        atmel_sha_get_cap(sha_dd);
+
+        if (sha_dd->caps.has_dma) {
+                pdata = pdev->dev.platform_data;
+                if (!pdata) {
+                        dev_err(&pdev->dev, "platform data not available\n");
+                        err = -ENXIO;
+                        goto err_pdata;
+                }
+                err = atmel_sha_dma_init(sha_dd, pdata);
+                if (err)
+                        goto err_sha_dma;
+        }
+
         spin_lock(&atmel_sha.lock);
         list_add_tail(&sha_dd->list, &atmel_sha.dev_list);
         spin_unlock(&atmel_sha.lock);
@@ -1048,6 +1427,10 @@ err_algs:
         spin_lock(&atmel_sha.lock);
         list_del(&sha_dd->list);
         spin_unlock(&atmel_sha.lock);
+        if (sha_dd->caps.has_dma)
+                atmel_sha_dma_cleanup(sha_dd);
+err_sha_dma:
+err_pdata:
         iounmap(sha_dd->io_base);
 sha_io_err:
         clk_put(sha_dd->iclk);
@@ -1078,6 +1461,9 @@ static int atmel_sha_remove(struct platform_device *pdev)
 
         tasklet_kill(&sha_dd->done_task);
 
+        if (sha_dd->caps.has_dma)
+                atmel_sha_dma_cleanup(sha_dd);
+
         iounmap(sha_dd->io_base);
 
         clk_put(sha_dd->iclk);
@@ -1102,6 +1488,6 @@ static struct platform_driver atmel_sha_driver = {
 
 module_platform_driver(atmel_sha_driver);
 
-MODULE_DESCRIPTION("Atmel SHA1/SHA256 hw acceleration support.");
+MODULE_DESCRIPTION("Atmel SHA (1/256/224/384/512) hw acceleration support.");
 MODULE_LICENSE("GPL v2");
 MODULE_AUTHOR("Nicolas Royer - Eukréa Electromatique");