diff options
author | Tadeusz Struk <tadeusz.struk@intel.com> | 2014-07-25 18:55:46 -0400 |
---|---|---|
committer | Herbert Xu <herbert@gondor.apana.org.au> | 2014-08-01 10:36:06 -0400 |
commit | 9a147cb3232fd8dbd44ed4628c6c0d05033d4c61 (patch) | |
tree | 56b4b76ad144e0960b04d07402256afbf78d9819 /drivers/crypto/qat/qat_common/qat_hal.c | |
parent | 8c1f8e3bbf60d0d06190be81f55d5199d52a463f (diff) |
crypto: qat - change ae_num to ae_id
Change the logic how acceleration engines are indexed to make it
easier to read. Aslo some return code values updates to better reflect
what failed.
Signed-off-by: Pingchao Yang <pingchao.yang@intel.com>
Signed-off-by: Tadeusz Struk <tadeusz.struk@intel.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Diffstat (limited to 'drivers/crypto/qat/qat_common/qat_hal.c')
-rw-r--r-- | drivers/crypto/qat/qat_common/qat_hal.c | 26 |
1 files changed, 13 insertions, 13 deletions
diff --git a/drivers/crypto/qat/qat_common/qat_hal.c b/drivers/crypto/qat/qat_common/qat_hal.c index 28da876ee268..da9626b6b6b4 100644 --- a/drivers/crypto/qat/qat_common/qat_hal.c +++ b/drivers/crypto/qat/qat_common/qat_hal.c | |||
@@ -424,7 +424,7 @@ static void qat_hal_reset_timestamp(struct icp_qat_fw_loader_handle *handle) | |||
424 | SET_GLB_CSR(handle, MISC_CONTROL, misc_ctl & | 424 | SET_GLB_CSR(handle, MISC_CONTROL, misc_ctl & |
425 | (~MC_TIMESTAMP_ENABLE)); | 425 | (~MC_TIMESTAMP_ENABLE)); |
426 | 426 | ||
427 | for (ae = 0; ae <= handle->hal_handle->ae_max_num; ae++) { | 427 | for (ae = 0; ae < handle->hal_handle->ae_max_num; ae++) { |
428 | if (!(handle->hal_handle->ae_mask & (1 << ae))) | 428 | if (!(handle->hal_handle->ae_mask & (1 << ae))) |
429 | continue; | 429 | continue; |
430 | qat_hal_wr_ae_csr(handle, ae, TIMESTAMP_LOW, 0); | 430 | qat_hal_wr_ae_csr(handle, ae, TIMESTAMP_LOW, 0); |
@@ -492,7 +492,7 @@ int qat_hal_clr_reset(struct icp_qat_fw_loader_handle *handle) | |||
492 | goto out_err; | 492 | goto out_err; |
493 | 493 | ||
494 | /* Set undefined power-up/reset states to reasonable default values */ | 494 | /* Set undefined power-up/reset states to reasonable default values */ |
495 | for (ae = 0; ae <= handle->hal_handle->ae_max_num; ae++) { | 495 | for (ae = 0; ae < handle->hal_handle->ae_max_num; ae++) { |
496 | if (!(handle->hal_handle->ae_mask & (1 << ae))) | 496 | if (!(handle->hal_handle->ae_mask & (1 << ae))) |
497 | continue; | 497 | continue; |
498 | qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, | 498 | qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, |
@@ -608,7 +608,7 @@ static int qat_hal_clear_gpr(struct icp_qat_fw_loader_handle *handle) | |||
608 | unsigned int savctx = 0; | 608 | unsigned int savctx = 0; |
609 | int ret = 0; | 609 | int ret = 0; |
610 | 610 | ||
611 | for (ae = 0; ae <= handle->hal_handle->ae_max_num; ae++) { | 611 | for (ae = 0; ae < handle->hal_handle->ae_max_num; ae++) { |
612 | if (!(handle->hal_handle->ae_mask & (1 << ae))) | 612 | if (!(handle->hal_handle->ae_mask & (1 << ae))) |
613 | continue; | 613 | continue; |
614 | for (reg = 0; reg < ICP_QAT_UCLO_MAX_GPR_REG; reg++) { | 614 | for (reg = 0; reg < ICP_QAT_UCLO_MAX_GPR_REG; reg++) { |
@@ -637,7 +637,7 @@ static int qat_hal_clear_gpr(struct icp_qat_fw_loader_handle *handle) | |||
637 | qat_hal_wr_ae_csr(handle, ae, CTX_SIG_EVENTS_ACTIVE, 0); | 637 | qat_hal_wr_ae_csr(handle, ae, CTX_SIG_EVENTS_ACTIVE, 0); |
638 | qat_hal_enable_ctx(handle, ae, ctx_mask); | 638 | qat_hal_enable_ctx(handle, ae, ctx_mask); |
639 | } | 639 | } |
640 | for (ae = 0; ae <= handle->hal_handle->ae_max_num; ae++) { | 640 | for (ae = 0; ae < handle->hal_handle->ae_max_num; ae++) { |
641 | if (!(handle->hal_handle->ae_mask & (1 << ae))) | 641 | if (!(handle->hal_handle->ae_mask & (1 << ae))) |
642 | continue; | 642 | continue; |
643 | /* wait for AE to finish */ | 643 | /* wait for AE to finish */ |
@@ -674,17 +674,16 @@ static int qat_hal_clear_gpr(struct icp_qat_fw_loader_handle *handle) | |||
674 | #define ICP_DH895XCC_PMISC_BAR 1 | 674 | #define ICP_DH895XCC_PMISC_BAR 1 |
675 | int qat_hal_init(struct adf_accel_dev *accel_dev) | 675 | int qat_hal_init(struct adf_accel_dev *accel_dev) |
676 | { | 676 | { |
677 | unsigned char ae = 0; | 677 | unsigned char ae; |
678 | unsigned int csr_val = 0; | 678 | unsigned int max_en_ae_id = 0; |
679 | unsigned int max_en_ae_num = 0; | 679 | struct icp_qat_fw_loader_handle *handle; |
680 | struct icp_qat_fw_loader_handle *handle = NULL; | ||
681 | struct adf_accel_pci *pci_info = &accel_dev->accel_pci_dev; | 680 | struct adf_accel_pci *pci_info = &accel_dev->accel_pci_dev; |
682 | struct adf_hw_device_data *hw_data = accel_dev->hw_device; | 681 | struct adf_hw_device_data *hw_data = accel_dev->hw_device; |
683 | struct adf_bar *bar = &pci_info->pci_bars[ADF_DH895XCC_PMISC_BAR]; | 682 | struct adf_bar *bar = &pci_info->pci_bars[ADF_DH895XCC_PMISC_BAR]; |
684 | 683 | ||
685 | handle = kzalloc(sizeof(*handle), GFP_KERNEL); | 684 | handle = kzalloc(sizeof(*handle), GFP_KERNEL); |
686 | if (!handle) | 685 | if (!handle) |
687 | goto out_handle; | 686 | return -ENOMEM; |
688 | 687 | ||
689 | handle->hal_cap_g_ctl_csr_addr_v = bar->virt_addr + | 688 | handle->hal_cap_g_ctl_csr_addr_v = bar->virt_addr + |
690 | ICP_DH895XCC_CAP_OFFSET; | 689 | ICP_DH895XCC_CAP_OFFSET; |
@@ -713,9 +712,9 @@ int qat_hal_init(struct adf_accel_dev *accel_dev) | |||
713 | handle->hal_handle->max_ustore; | 712 | handle->hal_handle->max_ustore; |
714 | handle->hal_handle->aes[ae].live_ctx_mask = | 713 | handle->hal_handle->aes[ae].live_ctx_mask = |
715 | ICP_QAT_UCLO_AE_ALL_CTX; | 714 | ICP_QAT_UCLO_AE_ALL_CTX; |
716 | max_en_ae_num = ae; | 715 | max_en_ae_id = ae; |
717 | } | 716 | } |
718 | handle->hal_handle->ae_max_num = max_en_ae_num; | 717 | handle->hal_handle->ae_max_num = max_en_ae_id + 1; |
719 | /* take all AEs out of reset */ | 718 | /* take all AEs out of reset */ |
720 | if (qat_hal_clr_reset(handle)) { | 719 | if (qat_hal_clr_reset(handle)) { |
721 | pr_err("QAT: qat_hal_clr_reset error\n"); | 720 | pr_err("QAT: qat_hal_clr_reset error\n"); |
@@ -724,7 +723,9 @@ int qat_hal_init(struct adf_accel_dev *accel_dev) | |||
724 | if (qat_hal_clear_gpr(handle)) | 723 | if (qat_hal_clear_gpr(handle)) |
725 | goto out_err; | 724 | goto out_err; |
726 | /* Set SIGNATURE_ENABLE[0] to 0x1 in order to enable ALU_OUT csr */ | 725 | /* Set SIGNATURE_ENABLE[0] to 0x1 in order to enable ALU_OUT csr */ |
727 | for (ae = 0; ae <= handle->hal_handle->ae_max_num; ae++) { | 726 | for (ae = 0; ae < handle->hal_handle->ae_max_num; ae++) { |
727 | unsigned int csr_val = 0; | ||
728 | |||
728 | if (!(hw_data->ae_mask & (1 << ae))) | 729 | if (!(hw_data->ae_mask & (1 << ae))) |
729 | continue; | 730 | continue; |
730 | qat_hal_rd_ae_csr(handle, ae, SIGNATURE_ENABLE, &csr_val); | 731 | qat_hal_rd_ae_csr(handle, ae, SIGNATURE_ENABLE, &csr_val); |
@@ -738,7 +739,6 @@ out_err: | |||
738 | kfree(handle->hal_handle); | 739 | kfree(handle->hal_handle); |
739 | out_hal_handle: | 740 | out_hal_handle: |
740 | kfree(handle); | 741 | kfree(handle); |
741 | out_handle: | ||
742 | return -EFAULT; | 742 | return -EFAULT; |
743 | } | 743 | } |
744 | 744 | ||