Merge git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6

Pull crypto update from Herbert Xu:

 - XTS mode optimisation for twofish/cast6/camellia/aes on x86

 - AVX2/x86_64 implementation for blowfish/twofish/serpent/camellia

 - SSSE3/AVX/AVX2 optimisations for sha256/sha512

 - Added driver for SAHARA2 crypto accelerator

 - Fix for GMAC when used in non-IPsec secnarios

 - Added generic CMAC implementation (including IPsec glue)

 - IP update for crypto/atmel

 - Support for more than one device in hwrng/timeriomem

 - Added Broadcom BCM2835 RNG driver

 - Misc fixes

* git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6: (59 commits)
  crypto: caam - fix job ring cleanup code
  crypto: camellia - add AVX2/AES-NI/x86_64 assembler implementation of camellia cipher
  crypto: serpent - add AVX2/x86_64 assembler implementation of serpent cipher
  crypto: twofish - add AVX2/x86_64 assembler implementation of twofish cipher
  crypto: blowfish - add AVX2/x86_64 implementation of blowfish cipher
  crypto: tcrypt - add async cipher speed tests for blowfish
  crypto: testmgr - extend camellia test-vectors for camellia-aesni/avx2
  crypto: aesni_intel - fix Kconfig problem with CRYPTO_GLUE_HELPER_X86
  crypto: aesni_intel - add more optimized XTS mode for x86-64
  crypto: x86/camellia-aesni-avx - add more optimized XTS code
  crypto: cast6-avx: use new optimized XTS code
  crypto: x86/twofish-avx - use optimized XTS code
  crypto: x86 - add more optimized XTS-mode for serpent-avx
  xfrm: add rfc4494 AES-CMAC-96 support
  crypto: add CMAC support to CryptoAPI
  crypto: testmgr - add empty test vectors for null ciphers
  crypto: testmgr - add AES GMAC test vectors
  crypto: gcm - fix rfc4543 to handle async crypto correctly
  crypto: gcm - make GMAC work when dst and src are different
  hwrng: timeriomem - added devicetree hooks
  ...

10 files changed, 27 insertions, 11 deletions

diff --git a/drivers/crypto/caam/Kconfig b/drivers/crypto/caam/Kconfig
index 65c7668614ab..b44091c47f75 100644
--- a/drivers/crypto/caam/Kconfig
+++ b/drivers/crypto/caam/Kconfig
@@ -78,7 +78,7 @@ config CRYPTO_DEV_FSL_CAAM_AHASH_API
         tristate "Register hash algorithm implementations with Crypto API"
         depends on CRYPTO_DEV_FSL_CAAM
         default y
-        select CRYPTO_AHASH
+        select CRYPTO_HASH
         help
           Selecting this will offload ahash for users of the
           scatterlist crypto API to the SEC4 via job ring.
diff --git a/drivers/crypto/caam/caamalg.c b/drivers/crypto/caam/caamalg.c
index cf268b14ae9a..765fdf5ce579 100644
--- a/drivers/crypto/caam/caamalg.c
+++ b/drivers/crypto/caam/caamalg.c
@@ -1693,6 +1693,7 @@ static struct caam_alg_template driver_algs[] = {
                 .name = "authenc(hmac(sha224),cbc(aes))",
                 .driver_name = "authenc-hmac-sha224-cbc-aes-caam",
                 .blocksize = AES_BLOCK_SIZE,
+                .type = CRYPTO_ALG_TYPE_AEAD,
                 .template_aead = {
                         .setkey = aead_setkey,
                         .setauthsize = aead_setauthsize,
@@ -1732,6 +1733,7 @@ static struct caam_alg_template driver_algs[] = {
                 .name = "authenc(hmac(sha384),cbc(aes))",
                 .driver_name = "authenc-hmac-sha384-cbc-aes-caam",
                 .blocksize = AES_BLOCK_SIZE,
+                .type = CRYPTO_ALG_TYPE_AEAD,
                 .template_aead = {
                         .setkey = aead_setkey,
                         .setauthsize = aead_setauthsize,
@@ -1810,6 +1812,7 @@ static struct caam_alg_template driver_algs[] = {
                 .name = "authenc(hmac(sha224),cbc(des3_ede))",
                 .driver_name = "authenc-hmac-sha224-cbc-des3_ede-caam",
                 .blocksize = DES3_EDE_BLOCK_SIZE,
+                .type = CRYPTO_ALG_TYPE_AEAD,
                 .template_aead = {
                         .setkey = aead_setkey,
                         .setauthsize = aead_setauthsize,
@@ -1849,6 +1852,7 @@ static struct caam_alg_template driver_algs[] = {
                 .name = "authenc(hmac(sha384),cbc(des3_ede))",
                 .driver_name = "authenc-hmac-sha384-cbc-des3_ede-caam",
                 .blocksize = DES3_EDE_BLOCK_SIZE,
+                .type = CRYPTO_ALG_TYPE_AEAD,
                 .template_aead = {
                         .setkey = aead_setkey,
                         .setauthsize = aead_setauthsize,
@@ -1926,6 +1930,7 @@ static struct caam_alg_template driver_algs[] = {
                 .name = "authenc(hmac(sha224),cbc(des))",
                 .driver_name = "authenc-hmac-sha224-cbc-des-caam",
                 .blocksize = DES_BLOCK_SIZE,
+                .type = CRYPTO_ALG_TYPE_AEAD,
                 .template_aead = {
                         .setkey = aead_setkey,
                         .setauthsize = aead_setauthsize,
@@ -1965,6 +1970,7 @@ static struct caam_alg_template driver_algs[] = {
                 .name = "authenc(hmac(sha384),cbc(des))",
                 .driver_name = "authenc-hmac-sha384-cbc-des-caam",
                 .blocksize = DES_BLOCK_SIZE,
+                .type = CRYPTO_ALG_TYPE_AEAD,
                 .template_aead = {
                         .setkey = aead_setkey,
                         .setauthsize = aead_setauthsize,
diff --git a/drivers/crypto/caam/caamhash.c b/drivers/crypto/caam/caamhash.c
index 32aba7a61503..5996521a1caf 100644
--- a/drivers/crypto/caam/caamhash.c
+++ b/drivers/crypto/caam/caamhash.c
@@ -411,7 +411,7 @@ static int ahash_set_sh_desc(struct crypto_ahash *ahash)
         return 0;
 }
 
-static u32 gen_split_hash_key(struct caam_hash_ctx *ctx, const u8 *key_in,
+static int gen_split_hash_key(struct caam_hash_ctx *ctx, const u8 *key_in,
                               u32 keylen)
 {
         return gen_split_key(ctx->jrdev, ctx->key, ctx->split_key_len,
@@ -420,7 +420,7 @@ static u32 gen_split_hash_key(struct caam_hash_ctx *ctx, const u8 *key_in,
 }
 
 /* Digest hash size if it is too large */
-static u32 hash_digest_key(struct caam_hash_ctx *ctx, const u8 *key_in,
+static int hash_digest_key(struct caam_hash_ctx *ctx, const u8 *key_in,
                            u32 *keylen, u8 *key_out, u32 digestsize)
 {
         struct device *jrdev = ctx->jrdev;
diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c
index 8acf00490fd5..6e94bcd94678 100644
--- a/drivers/crypto/caam/ctrl.c
+++ b/drivers/crypto/caam/ctrl.c
@@ -304,6 +304,9 @@ static int caam_probe(struct platform_device *pdev)
                         caam_remove(pdev);
                         return ret;
                 }
+
+                /* Enable RDB bit so that RNG works faster */
+                setbits32(&topregs->ctrl.scfgr, SCFGR_RDBENABLE);
         }
 
         /* NOTE: RTIC detection ought to go here, around Si time */
diff --git a/drivers/crypto/caam/error.c b/drivers/crypto/caam/error.c
index 30b8f74833d4..9f25f5296029 100644
--- a/drivers/crypto/caam/error.c
+++ b/drivers/crypto/caam/error.c
@@ -36,7 +36,7 @@ static void report_jump_idx(u32 status, char *outstr)
 
 static void report_ccb_status(u32 status, char *outstr)
 {
-        char *cha_id_list[] = {
+        static const char * const cha_id_list[] = {
                 "",
                 "AES",
                 "DES",
@@ -51,7 +51,7 @@ static void report_ccb_status(u32 status, char *outstr)
                 "ZUCE",
                 "ZUCA",
         };
-        char *err_id_list[] = {
+        static const char * const err_id_list[] = {
                 "No error.",
                 "Mode error.",
                 "Data size error.",
@@ -69,7 +69,7 @@ static void report_ccb_status(u32 status, char *outstr)
                 "Invalid CHA combination was selected",
                 "Invalid CHA selected.",
         };
-        char *rng_err_id_list[] = {
+        static const char * const rng_err_id_list[] = {
                 "",
                 "",
                 "",
@@ -117,7 +117,7 @@ static void report_jump_status(u32 status, char *outstr)
 
 static void report_deco_status(u32 status, char *outstr)
 {
-        const struct {
+        static const struct {
                 u8 value;
                 char *error_text;
         } desc_error_list[] = {
@@ -245,7 +245,7 @@ static void report_cond_code_status(u32 status, char *outstr)
 
 char *caam_jr_strstatus(char *outstr, u32 status)
 {
-        struct stat_src {
+        static const struct stat_src {
                 void (*report_ssed)(u32 status, char *outstr);
                 char *error;
         } status_src[] = {
diff --git a/drivers/crypto/caam/intern.h b/drivers/crypto/caam/intern.h
index 5cd4c1b268a1..e4a16b741371 100644
--- a/drivers/crypto/caam/intern.h
+++ b/drivers/crypto/caam/intern.h
@@ -41,6 +41,7 @@ struct caam_jrentry_info {
 /* Private sub-storage for a single JobR */
 struct caam_drv_private_jr {
         struct device *parentdev;       /* points back to controller dev */
+        struct platform_device *jr_pdev;/* points to platform device for JR */
         int ridx;
         struct caam_job_ring __iomem *rregs;    /* JobR's register space */
         struct tasklet_struct irqtask;
diff --git a/drivers/crypto/caam/jr.c b/drivers/crypto/caam/jr.c
index 93d14070141a..b4aa773ecbc8 100644
--- a/drivers/crypto/caam/jr.c
+++ b/drivers/crypto/caam/jr.c
@@ -407,6 +407,7 @@ int caam_jr_shutdown(struct device *dev)
         dma_free_coherent(dev, sizeof(struct jr_outentry) * JOBR_DEPTH,
                           jrp->outring, outbusaddr);
         kfree(jrp->entinfo);
+        of_device_unregister(jrp->jr_pdev);
 
         return ret;
 }
@@ -454,6 +455,8 @@ int caam_jr_probe(struct platform_device *pdev, struct device_node *np,
                 kfree(jrpriv);
                 return -EINVAL;
         }
+
+        jrpriv->jr_pdev = jr_pdev;
         jrdev = &jr_pdev->dev;
         dev_set_drvdata(jrdev, jrpriv);
         ctrlpriv->jrdev[ring] = jrdev;
@@ -472,6 +475,7 @@ int caam_jr_probe(struct platform_device *pdev, struct device_node *np,
         /* Now do the platform independent part */
         error = caam_jr_init(jrdev); /* now turn on hardware */
         if (error) {
+                of_device_unregister(jr_pdev);
                 kfree(jrpriv);
                 return error;
         }
diff --git a/drivers/crypto/caam/key_gen.c b/drivers/crypto/caam/key_gen.c
index f6dba10246c3..87138d2adb5f 100644
--- a/drivers/crypto/caam/key_gen.c
+++ b/drivers/crypto/caam/key_gen.c
@@ -44,7 +44,7 @@ Split key generation-----------------------------------------------
 [06] 0x64260028    fifostr: class2 mdsplit-jdk len=40
                         @0xffe04000
 */
-u32 gen_split_key(struct device *jrdev, u8 *key_out, int split_key_len,
+int gen_split_key(struct device *jrdev, u8 *key_out, int split_key_len,
                   int split_key_pad_len, const u8 *key_in, u32 keylen,
                   u32 alg_op)
 {
diff --git a/drivers/crypto/caam/key_gen.h b/drivers/crypto/caam/key_gen.h
index d95d290c6e8b..c5588f6d8109 100644
--- a/drivers/crypto/caam/key_gen.h
+++ b/drivers/crypto/caam/key_gen.h
@@ -12,6 +12,6 @@ struct split_key_result {
 
 void split_key_done(struct device *dev, u32 *desc, u32 err, void *context);
 
-u32 gen_split_key(struct device *jrdev, u8 *key_out, int split_key_len,
+int gen_split_key(struct device *jrdev, u8 *key_out, int split_key_len,
                     int split_key_pad_len, const u8 *key_in, u32 keylen,
                     u32 alg_op);
diff --git a/drivers/crypto/caam/regs.h b/drivers/crypto/caam/regs.h
index 3223fc6d647c..cd6fedad9935 100644
--- a/drivers/crypto/caam/regs.h
+++ b/drivers/crypto/caam/regs.h
@@ -252,7 +252,8 @@ struct caam_ctrl {
         /* Read/Writable                                                */
         u32 rsvd1;
         u32 mcr;                /* MCFG      Master Config Register  */
-        u32 rsvd2[2];
+        u32 rsvd2;
+        u32 scfgr;              /* SCFGR, Security Config Register */
 
         /* Bus Access Configuration Section                     010-11f */
         /* Read/Writable                                                */
@@ -299,6 +300,7 @@ struct caam_ctrl {
 #define MCFGR_WDFAIL            0x20000000 /* DECO watchdog force-fail */
 #define MCFGR_DMA_RESET         0x10000000
 #define MCFGR_LONG_PTR          0x00010000 /* Use >32-bit desc addressing */
+#define SCFGR_RDBENABLE         0x00000400
 
 /* AXI read cache control */
 #define MCFGR_ARCACHE_SHIFT     12