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authorRafael J. Wysocki <rafael.j.wysocki@intel.com>2013-02-15 08:00:15 -0500
committerRafael J. Wysocki <rafael.j.wysocki@intel.com>2013-02-15 08:00:15 -0500
commit60a406d1de227037193db6790a1a8650ea51dc93 (patch)
tree3ad0b8e66844ec90e6d0118f496e407f9761bc29 /drivers/cpufreq
parent4419fbd4b408c3a8634b3a8dd952055d0f0b601f (diff)
parentc098ea74b268969bde5aaf1689b61d236abf82f5 (diff)
Merge branch 'next/cpufreq-exynos' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung
* 'next/cpufreq-exynos' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: cpufreq: exynos: Fix hang in pm handler due to frequency mismatch cpufreq: exynos: Initialize return variable cpufreq: exynos: Fix unsigned variable being checked for negative value cpufreq: exynos: Get booting freq value in exynos_cpufreq_init cpufreq: exynos: Show list of available frequencies cpufreq: exynos: Add missing static cpufreq: exynos: Split exynos_target function into two functions cpufreq: exynos: Use APLL_FREQ macro for cpu divider value cpufreq: exynos: Check old & new frequency early cpufreq: exynos: Remove unused variable & IS_ERR
Diffstat (limited to 'drivers/cpufreq')
-rw-r--r--drivers/cpufreq/exynos-cpufreq.c174
-rw-r--r--drivers/cpufreq/exynos4210-cpufreq.c152
-rw-r--r--drivers/cpufreq/exynos4x12-cpufreq.c388
-rw-r--r--drivers/cpufreq/exynos5250-cpufreq.c178
4 files changed, 232 insertions, 660 deletions
diff --git a/drivers/cpufreq/exynos-cpufreq.c b/drivers/cpufreq/exynos-cpufreq.c
index 81eb84a24fa7..69b676dd3358 100644
--- a/drivers/cpufreq/exynos-cpufreq.c
+++ b/drivers/cpufreq/exynos-cpufreq.c
@@ -42,51 +42,56 @@ static unsigned int exynos_getspeed(unsigned int cpu)
42 return clk_get_rate(exynos_info->cpu_clk) / 1000; 42 return clk_get_rate(exynos_info->cpu_clk) / 1000;
43} 43}
44 44
45static int exynos_target(struct cpufreq_policy *policy, 45static int exynos_cpufreq_get_index(unsigned int freq)
46 unsigned int target_freq, 46{
47 unsigned int relation) 47 struct cpufreq_frequency_table *freq_table = exynos_info->freq_table;
48 int index;
49
50 for (index = 0;
51 freq_table[index].frequency != CPUFREQ_TABLE_END; index++)
52 if (freq_table[index].frequency == freq)
53 break;
54
55 if (freq_table[index].frequency == CPUFREQ_TABLE_END)
56 return -EINVAL;
57
58 return index;
59}
60
61static int exynos_cpufreq_scale(unsigned int target_freq)
48{ 62{
49 unsigned int index, old_index;
50 unsigned int arm_volt, safe_arm_volt = 0;
51 int ret = 0;
52 struct cpufreq_frequency_table *freq_table = exynos_info->freq_table; 63 struct cpufreq_frequency_table *freq_table = exynos_info->freq_table;
53 unsigned int *volt_table = exynos_info->volt_table; 64 unsigned int *volt_table = exynos_info->volt_table;
65 struct cpufreq_policy *policy = cpufreq_cpu_get(0);
66 unsigned int arm_volt, safe_arm_volt = 0;
54 unsigned int mpll_freq_khz = exynos_info->mpll_freq_khz; 67 unsigned int mpll_freq_khz = exynos_info->mpll_freq_khz;
55 68 int index, old_index;
56 mutex_lock(&cpufreq_lock); 69 int ret = 0;
57 70
58 freqs.old = policy->cur; 71 freqs.old = policy->cur;
72 freqs.new = target_freq;
73 freqs.cpu = policy->cpu;
59 74
60 if (frequency_locked && target_freq != locking_frequency) { 75 if (freqs.new == freqs.old)
61 ret = -EAGAIN;
62 goto out; 76 goto out;
63 }
64 77
65 /* 78 /*
66 * The policy max have been changed so that we cannot get proper 79 * The policy max have been changed so that we cannot get proper
67 * old_index with cpufreq_frequency_table_target(). Thus, ignore 80 * old_index with cpufreq_frequency_table_target(). Thus, ignore
68 * policy and get the index from the raw freqeuncy table. 81 * policy and get the index from the raw freqeuncy table.
69 */ 82 */
70 for (old_index = 0; 83 old_index = exynos_cpufreq_get_index(freqs.old);
71 freq_table[old_index].frequency != CPUFREQ_TABLE_END; 84 if (old_index < 0) {
72 old_index++) 85 ret = old_index;
73 if (freq_table[old_index].frequency == freqs.old)
74 break;
75
76 if (freq_table[old_index].frequency == CPUFREQ_TABLE_END) {
77 ret = -EINVAL;
78 goto out; 86 goto out;
79 } 87 }
80 88
81 if (cpufreq_frequency_table_target(policy, freq_table, 89 index = exynos_cpufreq_get_index(target_freq);
82 target_freq, relation, &index)) { 90 if (index < 0) {
83 ret = -EINVAL; 91 ret = index;
84 goto out; 92 goto out;
85 } 93 }
86 94
87 freqs.new = freq_table[index].frequency;
88 freqs.cpu = policy->cpu;
89
90 /* 95 /*
91 * ARM clock source will be changed APLL to MPLL temporary 96 * ARM clock source will be changed APLL to MPLL temporary
92 * To support this level, need to control regulator for 97 * To support this level, need to control regulator for
@@ -106,15 +111,25 @@ static int exynos_target(struct cpufreq_policy *policy,
106 /* When the new frequency is higher than current frequency */ 111 /* When the new frequency is higher than current frequency */
107 if ((freqs.new > freqs.old) && !safe_arm_volt) { 112 if ((freqs.new > freqs.old) && !safe_arm_volt) {
108 /* Firstly, voltage up to increase frequency */ 113 /* Firstly, voltage up to increase frequency */
109 regulator_set_voltage(arm_regulator, arm_volt, 114 ret = regulator_set_voltage(arm_regulator, arm_volt, arm_volt);
110 arm_volt); 115 if (ret) {
116 pr_err("%s: failed to set cpu voltage to %d\n",
117 __func__, arm_volt);
118 goto out;
119 }
111 } 120 }
112 121
113 if (safe_arm_volt) 122 if (safe_arm_volt) {
114 regulator_set_voltage(arm_regulator, safe_arm_volt, 123 ret = regulator_set_voltage(arm_regulator, safe_arm_volt,
115 safe_arm_volt); 124 safe_arm_volt);
116 if (freqs.new != freqs.old) 125 if (ret) {
117 exynos_info->set_freq(old_index, index); 126 pr_err("%s: failed to set cpu voltage to %d\n",
127 __func__, safe_arm_volt);
128 goto out;
129 }
130 }
131
132 exynos_info->set_freq(old_index, index);
118 133
119 for_each_cpu(freqs.cpu, policy->cpus) 134 for_each_cpu(freqs.cpu, policy->cpus)
120 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); 135 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
@@ -125,9 +140,45 @@ static int exynos_target(struct cpufreq_policy *policy,
125 /* down the voltage after frequency change */ 140 /* down the voltage after frequency change */
126 regulator_set_voltage(arm_regulator, arm_volt, 141 regulator_set_voltage(arm_regulator, arm_volt,
127 arm_volt); 142 arm_volt);
143 if (ret) {
144 pr_err("%s: failed to set cpu voltage to %d\n",
145 __func__, arm_volt);
146 goto out;
147 }
128 } 148 }
129 149
130out: 150out:
151
152 cpufreq_cpu_put(policy);
153
154 return ret;
155}
156
157static int exynos_target(struct cpufreq_policy *policy,
158 unsigned int target_freq,
159 unsigned int relation)
160{
161 struct cpufreq_frequency_table *freq_table = exynos_info->freq_table;
162 unsigned int index;
163 unsigned int new_freq;
164 int ret = 0;
165
166 mutex_lock(&cpufreq_lock);
167
168 if (frequency_locked)
169 goto out;
170
171 if (cpufreq_frequency_table_target(policy, freq_table,
172 target_freq, relation, &index)) {
173 ret = -EINVAL;
174 goto out;
175 }
176
177 new_freq = freq_table[index].frequency;
178
179 ret = exynos_cpufreq_scale(new_freq);
180
181out:
131 mutex_unlock(&cpufreq_lock); 182 mutex_unlock(&cpufreq_lock);
132 183
133 return ret; 184 return ret;
@@ -163,51 +214,26 @@ static int exynos_cpufreq_resume(struct cpufreq_policy *policy)
163static int exynos_cpufreq_pm_notifier(struct notifier_block *notifier, 214static int exynos_cpufreq_pm_notifier(struct notifier_block *notifier,
164 unsigned long pm_event, void *v) 215 unsigned long pm_event, void *v)
165{ 216{
166 struct cpufreq_policy *policy = cpufreq_cpu_get(0); /* boot CPU */ 217 int ret;
167 static unsigned int saved_frequency;
168 unsigned int temp;
169 218
170 mutex_lock(&cpufreq_lock);
171 switch (pm_event) { 219 switch (pm_event) {
172 case PM_SUSPEND_PREPARE: 220 case PM_SUSPEND_PREPARE:
173 if (frequency_locked) 221 mutex_lock(&cpufreq_lock);
174 goto out;
175
176 frequency_locked = true; 222 frequency_locked = true;
223 mutex_unlock(&cpufreq_lock);
177 224
178 if (locking_frequency) { 225 ret = exynos_cpufreq_scale(locking_frequency);
179 saved_frequency = exynos_getspeed(0); 226 if (ret < 0)
227 return NOTIFY_BAD;
180 228
181 mutex_unlock(&cpufreq_lock);
182 exynos_target(policy, locking_frequency,
183 CPUFREQ_RELATION_H);
184 mutex_lock(&cpufreq_lock);
185 }
186 break; 229 break;
187 230
188 case PM_POST_SUSPEND: 231 case PM_POST_SUSPEND:
189 if (saved_frequency) { 232 mutex_lock(&cpufreq_lock);
190 /*
191 * While frequency_locked, only locking_frequency
192 * is valid for target(). In order to use
193 * saved_frequency while keeping frequency_locked,
194 * we temporarly overwrite locking_frequency.
195 */
196 temp = locking_frequency;
197 locking_frequency = saved_frequency;
198
199 mutex_unlock(&cpufreq_lock);
200 exynos_target(policy, locking_frequency,
201 CPUFREQ_RELATION_H);
202 mutex_lock(&cpufreq_lock);
203
204 locking_frequency = temp;
205 }
206 frequency_locked = false; 233 frequency_locked = false;
234 mutex_unlock(&cpufreq_lock);
207 break; 235 break;
208 } 236 }
209out:
210 mutex_unlock(&cpufreq_lock);
211 237
212 return NOTIFY_OK; 238 return NOTIFY_OK;
213} 239}
@@ -222,8 +248,6 @@ static int exynos_cpufreq_cpu_init(struct cpufreq_policy *policy)
222 248
223 cpufreq_frequency_table_get_attr(exynos_info->freq_table, policy->cpu); 249 cpufreq_frequency_table_get_attr(exynos_info->freq_table, policy->cpu);
224 250
225 locking_frequency = exynos_getspeed(0);
226
227 /* set the transition latency value */ 251 /* set the transition latency value */
228 policy->cpuinfo.transition_latency = 100000; 252 policy->cpuinfo.transition_latency = 100000;
229 253
@@ -232,13 +256,26 @@ static int exynos_cpufreq_cpu_init(struct cpufreq_policy *policy)
232 return cpufreq_frequency_table_cpuinfo(policy, exynos_info->freq_table); 256 return cpufreq_frequency_table_cpuinfo(policy, exynos_info->freq_table);
233} 257}
234 258
259static int exynos_cpufreq_cpu_exit(struct cpufreq_policy *policy)
260{
261 cpufreq_frequency_table_put_attr(policy->cpu);
262 return 0;
263}
264
265static struct freq_attr *exynos_cpufreq_attr[] = {
266 &cpufreq_freq_attr_scaling_available_freqs,
267 NULL,
268};
269
235static struct cpufreq_driver exynos_driver = { 270static struct cpufreq_driver exynos_driver = {
236 .flags = CPUFREQ_STICKY, 271 .flags = CPUFREQ_STICKY,
237 .verify = exynos_verify_speed, 272 .verify = exynos_verify_speed,
238 .target = exynos_target, 273 .target = exynos_target,
239 .get = exynos_getspeed, 274 .get = exynos_getspeed,
240 .init = exynos_cpufreq_cpu_init, 275 .init = exynos_cpufreq_cpu_init,
276 .exit = exynos_cpufreq_cpu_exit,
241 .name = "exynos_cpufreq", 277 .name = "exynos_cpufreq",
278 .attr = exynos_cpufreq_attr,
242#ifdef CONFIG_PM 279#ifdef CONFIG_PM
243 .suspend = exynos_cpufreq_suspend, 280 .suspend = exynos_cpufreq_suspend,
244 .resume = exynos_cpufreq_resume, 281 .resume = exynos_cpufreq_resume,
@@ -276,6 +313,8 @@ static int __init exynos_cpufreq_init(void)
276 goto err_vdd_arm; 313 goto err_vdd_arm;
277 } 314 }
278 315
316 locking_frequency = exynos_getspeed(0);
317
279 register_pm_notifier(&exynos_cpufreq_nb); 318 register_pm_notifier(&exynos_cpufreq_nb);
280 319
281 if (cpufreq_register_driver(&exynos_driver)) { 320 if (cpufreq_register_driver(&exynos_driver)) {
@@ -287,8 +326,7 @@ static int __init exynos_cpufreq_init(void)
287err_cpufreq: 326err_cpufreq:
288 unregister_pm_notifier(&exynos_cpufreq_nb); 327 unregister_pm_notifier(&exynos_cpufreq_nb);
289 328
290 if (!IS_ERR(arm_regulator)) 329 regulator_put(arm_regulator);
291 regulator_put(arm_regulator);
292err_vdd_arm: 330err_vdd_arm:
293 kfree(exynos_info); 331 kfree(exynos_info);
294 pr_debug("%s: failed initialization\n", __func__); 332 pr_debug("%s: failed initialization\n", __func__);
diff --git a/drivers/cpufreq/exynos4210-cpufreq.c b/drivers/cpufreq/exynos4210-cpufreq.c
index fb148fa27678..de91755e2556 100644
--- a/drivers/cpufreq/exynos4210-cpufreq.c
+++ b/drivers/cpufreq/exynos4210-cpufreq.c
@@ -20,97 +20,37 @@
20#include <mach/regs-clock.h> 20#include <mach/regs-clock.h>
21#include <mach/cpufreq.h> 21#include <mach/cpufreq.h>
22 22
23#define CPUFREQ_LEVEL_END L5
24
25static int max_support_idx = L0;
26static int min_support_idx = (CPUFREQ_LEVEL_END - 1);
27
28static struct clk *cpu_clk; 23static struct clk *cpu_clk;
29static struct clk *moutcore; 24static struct clk *moutcore;
30static struct clk *mout_mpll; 25static struct clk *mout_mpll;
31static struct clk *mout_apll; 26static struct clk *mout_apll;
32 27
33struct cpufreq_clkdiv { 28static unsigned int exynos4210_volt_table[] = {
34 unsigned int index;
35 unsigned int clkdiv;
36};
37
38static unsigned int exynos4210_volt_table[CPUFREQ_LEVEL_END] = {
39 1250000, 1150000, 1050000, 975000, 950000, 29 1250000, 1150000, 1050000, 975000, 950000,
40}; 30};
41 31
42
43static struct cpufreq_clkdiv exynos4210_clkdiv_table[CPUFREQ_LEVEL_END];
44
45static struct cpufreq_frequency_table exynos4210_freq_table[] = { 32static struct cpufreq_frequency_table exynos4210_freq_table[] = {
46 {L0, 1200*1000}, 33 {L0, 1200 * 1000},
47 {L1, 1000*1000}, 34 {L1, 1000 * 1000},
48 {L2, 800*1000}, 35 {L2, 800 * 1000},
49 {L3, 500*1000}, 36 {L3, 500 * 1000},
50 {L4, 200*1000}, 37 {L4, 200 * 1000},
51 {0, CPUFREQ_TABLE_END}, 38 {0, CPUFREQ_TABLE_END},
52}; 39};
53 40
54static unsigned int clkdiv_cpu0[CPUFREQ_LEVEL_END][7] = { 41static struct apll_freq apll_freq_4210[] = {
55 /* 42 /*
56 * Clock divider value for following 43 * values:
57 * { DIVCORE, DIVCOREM0, DIVCOREM1, DIVPERIPH, 44 * freq
58 * DIVATB, DIVPCLK_DBG, DIVAPLL } 45 * clock divider for CORE, COREM0, COREM1, PERIPH, ATB, PCLK_DBG, APLL, RESERVED
46 * clock divider for COPY, HPM, RESERVED
47 * PLL M, P, S
59 */ 48 */
60 49 APLL_FREQ(1200, 0, 3, 7, 3, 4, 1, 7, 0, 5, 0, 0, 150, 3, 1),
61 /* ARM L0: 1200MHz */ 50 APLL_FREQ(1000, 0, 3, 7, 3, 4, 1, 7, 0, 4, 0, 0, 250, 6, 1),
62 { 0, 3, 7, 3, 4, 1, 7 }, 51 APLL_FREQ(800, 0, 3, 7, 3, 3, 1, 7, 0, 3, 0, 0, 200, 6, 1),
63 52 APLL_FREQ(500, 0, 3, 7, 3, 3, 1, 7, 0, 3, 0, 0, 250, 6, 2),
64 /* ARM L1: 1000MHz */ 53 APLL_FREQ(200, 0, 1, 3, 1, 3, 1, 0, 0, 3, 0, 0, 200, 6, 3),
65 { 0, 3, 7, 3, 4, 1, 7 },
66
67 /* ARM L2: 800MHz */
68 { 0, 3, 7, 3, 3, 1, 7 },
69
70 /* ARM L3: 500MHz */
71 { 0, 3, 7, 3, 3, 1, 7 },
72
73 /* ARM L4: 200MHz */
74 { 0, 1, 3, 1, 3, 1, 0 },
75};
76
77static unsigned int clkdiv_cpu1[CPUFREQ_LEVEL_END][2] = {
78 /*
79 * Clock divider value for following
80 * { DIVCOPY, DIVHPM }
81 */
82
83 /* ARM L0: 1200MHz */
84 { 5, 0 },
85
86 /* ARM L1: 1000MHz */
87 { 4, 0 },
88
89 /* ARM L2: 800MHz */
90 { 3, 0 },
91
92 /* ARM L3: 500MHz */
93 { 3, 0 },
94
95 /* ARM L4: 200MHz */
96 { 3, 0 },
97};
98
99static unsigned int exynos4210_apll_pms_table[CPUFREQ_LEVEL_END] = {
100 /* APLL FOUT L0: 1200MHz */
101 ((150 << 16) | (3 << 8) | 1),
102
103 /* APLL FOUT L1: 1000MHz */
104 ((250 << 16) | (6 << 8) | 1),
105
106 /* APLL FOUT L2: 800MHz */
107 ((200 << 16) | (6 << 8) | 1),
108
109 /* APLL FOUT L3: 500MHz */
110 ((250 << 16) | (6 << 8) | 2),
111
112 /* APLL FOUT L4: 200MHz */
113 ((200 << 16) | (6 << 8) | 3),
114}; 54};
115 55
116static void exynos4210_set_clkdiv(unsigned int div_index) 56static void exynos4210_set_clkdiv(unsigned int div_index)
@@ -119,7 +59,7 @@ static void exynos4210_set_clkdiv(unsigned int div_index)
119 59
120 /* Change Divider - CPU0 */ 60 /* Change Divider - CPU0 */
121 61
122 tmp = exynos4210_clkdiv_table[div_index].clkdiv; 62 tmp = apll_freq_4210[div_index].clk_div_cpu0;
123 63
124 __raw_writel(tmp, EXYNOS4_CLKDIV_CPU); 64 __raw_writel(tmp, EXYNOS4_CLKDIV_CPU);
125 65
@@ -129,12 +69,7 @@ static void exynos4210_set_clkdiv(unsigned int div_index)
129 69
130 /* Change Divider - CPU1 */ 70 /* Change Divider - CPU1 */
131 71
132 tmp = __raw_readl(EXYNOS4_CLKDIV_CPU1); 72 tmp = apll_freq_4210[div_index].clk_div_cpu1;
133
134 tmp &= ~((0x7 << 4) | 0x7);
135
136 tmp |= ((clkdiv_cpu1[div_index][0] << 4) |
137 (clkdiv_cpu1[div_index][1] << 0));
138 73
139 __raw_writel(tmp, EXYNOS4_CLKDIV_CPU1); 74 __raw_writel(tmp, EXYNOS4_CLKDIV_CPU1);
140 75
@@ -162,7 +97,7 @@ static void exynos4210_set_apll(unsigned int index)
162 /* 3. Change PLL PMS values */ 97 /* 3. Change PLL PMS values */
163 tmp = __raw_readl(EXYNOS4_APLL_CON0); 98 tmp = __raw_readl(EXYNOS4_APLL_CON0);
164 tmp &= ~((0x3ff << 16) | (0x3f << 8) | (0x7 << 0)); 99 tmp &= ~((0x3ff << 16) | (0x3f << 8) | (0x7 << 0));
165 tmp |= exynos4210_apll_pms_table[index]; 100 tmp |= apll_freq_4210[index].mps;
166 __raw_writel(tmp, EXYNOS4_APLL_CON0); 101 __raw_writel(tmp, EXYNOS4_APLL_CON0);
167 102
168 /* 4. wait_lock_time */ 103 /* 4. wait_lock_time */
@@ -179,10 +114,10 @@ static void exynos4210_set_apll(unsigned int index)
179 } while (tmp != (0x1 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT)); 114 } while (tmp != (0x1 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT));
180} 115}
181 116
182bool exynos4210_pms_change(unsigned int old_index, unsigned int new_index) 117static bool exynos4210_pms_change(unsigned int old_index, unsigned int new_index)
183{ 118{
184 unsigned int old_pm = (exynos4210_apll_pms_table[old_index] >> 8); 119 unsigned int old_pm = apll_freq_4210[old_index].mps >> 8;
185 unsigned int new_pm = (exynos4210_apll_pms_table[new_index] >> 8); 120 unsigned int new_pm = apll_freq_4210[new_index].mps >> 8;
186 121
187 return (old_pm == new_pm) ? 0 : 1; 122 return (old_pm == new_pm) ? 0 : 1;
188} 123}
@@ -200,7 +135,7 @@ static void exynos4210_set_frequency(unsigned int old_index,
200 /* 2. Change just s value in apll m,p,s value */ 135 /* 2. Change just s value in apll m,p,s value */
201 tmp = __raw_readl(EXYNOS4_APLL_CON0); 136 tmp = __raw_readl(EXYNOS4_APLL_CON0);
202 tmp &= ~(0x7 << 0); 137 tmp &= ~(0x7 << 0);
203 tmp |= (exynos4210_apll_pms_table[new_index] & 0x7); 138 tmp |= apll_freq_4210[new_index].mps & 0x7;
204 __raw_writel(tmp, EXYNOS4_APLL_CON0); 139 __raw_writel(tmp, EXYNOS4_APLL_CON0);
205 } else { 140 } else {
206 /* Clock Configuration Procedure */ 141 /* Clock Configuration Procedure */
@@ -214,7 +149,7 @@ static void exynos4210_set_frequency(unsigned int old_index,
214 /* 1. Change just s value in apll m,p,s value */ 149 /* 1. Change just s value in apll m,p,s value */
215 tmp = __raw_readl(EXYNOS4_APLL_CON0); 150 tmp = __raw_readl(EXYNOS4_APLL_CON0);
216 tmp &= ~(0x7 << 0); 151 tmp &= ~(0x7 << 0);
217 tmp |= (exynos4210_apll_pms_table[new_index] & 0x7); 152 tmp |= apll_freq_4210[new_index].mps & 0x7;
218 __raw_writel(tmp, EXYNOS4_APLL_CON0); 153 __raw_writel(tmp, EXYNOS4_APLL_CON0);
219 154
220 /* 2. Change the system clock divider values */ 155 /* 2. Change the system clock divider values */
@@ -231,8 +166,6 @@ static void exynos4210_set_frequency(unsigned int old_index,
231 166
232int exynos4210_cpufreq_init(struct exynos_dvfs_info *info) 167int exynos4210_cpufreq_init(struct exynos_dvfs_info *info)
233{ 168{
234 int i;
235 unsigned int tmp;
236 unsigned long rate; 169 unsigned long rate;
237 170
238 cpu_clk = clk_get(NULL, "armclk"); 171 cpu_clk = clk_get(NULL, "armclk");
@@ -253,33 +186,9 @@ int exynos4210_cpufreq_init(struct exynos_dvfs_info *info)
253 if (IS_ERR(mout_apll)) 186 if (IS_ERR(mout_apll))
254 goto err_mout_apll; 187 goto err_mout_apll;
255 188
256 tmp = __raw_readl(EXYNOS4_CLKDIV_CPU);
257
258 for (i = L0; i < CPUFREQ_LEVEL_END; i++) {
259 tmp &= ~(EXYNOS4_CLKDIV_CPU0_CORE_MASK |
260 EXYNOS4_CLKDIV_CPU0_COREM0_MASK |
261 EXYNOS4_CLKDIV_CPU0_COREM1_MASK |
262 EXYNOS4_CLKDIV_CPU0_PERIPH_MASK |
263 EXYNOS4_CLKDIV_CPU0_ATB_MASK |
264 EXYNOS4_CLKDIV_CPU0_PCLKDBG_MASK |
265 EXYNOS4_CLKDIV_CPU0_APLL_MASK);
266
267 tmp |= ((clkdiv_cpu0[i][0] << EXYNOS4_CLKDIV_CPU0_CORE_SHIFT) |
268 (clkdiv_cpu0[i][1] << EXYNOS4_CLKDIV_CPU0_COREM0_SHIFT) |
269 (clkdiv_cpu0[i][2] << EXYNOS4_CLKDIV_CPU0_COREM1_SHIFT) |
270 (clkdiv_cpu0[i][3] << EXYNOS4_CLKDIV_CPU0_PERIPH_SHIFT) |
271 (clkdiv_cpu0[i][4] << EXYNOS4_CLKDIV_CPU0_ATB_SHIFT) |
272 (clkdiv_cpu0[i][5] << EXYNOS4_CLKDIV_CPU0_PCLKDBG_SHIFT) |
273 (clkdiv_cpu0[i][6] << EXYNOS4_CLKDIV_CPU0_APLL_SHIFT));
274
275 exynos4210_clkdiv_table[i].clkdiv = tmp;
276 }
277
278 info->mpll_freq_khz = rate; 189 info->mpll_freq_khz = rate;
279 info->pm_lock_idx = L2; 190 /* 800Mhz */
280 info->pll_safe_idx = L2; 191 info->pll_safe_idx = L2;
281 info->max_support_idx = max_support_idx;
282 info->min_support_idx = min_support_idx;
283 info->cpu_clk = cpu_clk; 192 info->cpu_clk = cpu_clk;
284 info->volt_table = exynos4210_volt_table; 193 info->volt_table = exynos4210_volt_table;
285 info->freq_table = exynos4210_freq_table; 194 info->freq_table = exynos4210_freq_table;
@@ -289,14 +198,11 @@ int exynos4210_cpufreq_init(struct exynos_dvfs_info *info)
289 return 0; 198 return 0;
290 199
291err_mout_apll: 200err_mout_apll:
292 if (!IS_ERR(mout_mpll)) 201 clk_put(mout_mpll);
293 clk_put(mout_mpll);
294err_mout_mpll: 202err_mout_mpll:
295 if (!IS_ERR(moutcore)) 203 clk_put(moutcore);
296 clk_put(moutcore);
297err_moutcore: 204err_moutcore:
298 if (!IS_ERR(cpu_clk)) 205 clk_put(cpu_clk);
299 clk_put(cpu_clk);
300 206
301 pr_debug("%s: failed initialization\n", __func__); 207 pr_debug("%s: failed initialization\n", __func__);
302 return -EINVAL; 208 return -EINVAL;
diff --git a/drivers/cpufreq/exynos4x12-cpufreq.c b/drivers/cpufreq/exynos4x12-cpufreq.c
index 8c5a7afa5b0b..0661039e5d4a 100644
--- a/drivers/cpufreq/exynos4x12-cpufreq.c
+++ b/drivers/cpufreq/exynos4x12-cpufreq.c
@@ -20,26 +20,18 @@
20#include <mach/regs-clock.h> 20#include <mach/regs-clock.h>
21#include <mach/cpufreq.h> 21#include <mach/cpufreq.h>
22 22
23#define CPUFREQ_LEVEL_END (L13 + 1)
24
25static int max_support_idx;
26static int min_support_idx = (CPUFREQ_LEVEL_END - 1);
27
28static struct clk *cpu_clk; 23static struct clk *cpu_clk;
29static struct clk *moutcore; 24static struct clk *moutcore;
30static struct clk *mout_mpll; 25static struct clk *mout_mpll;
31static struct clk *mout_apll; 26static struct clk *mout_apll;
32 27
33struct cpufreq_clkdiv { 28static unsigned int exynos4x12_volt_table[] = {
34 unsigned int index; 29 1350000, 1287500, 1250000, 1187500, 1137500, 1087500, 1037500,
35 unsigned int clkdiv; 30 1000000, 987500, 975000, 950000, 925000, 900000, 900000
36 unsigned int clkdiv1;
37}; 31};
38 32
39static unsigned int exynos4x12_volt_table[CPUFREQ_LEVEL_END];
40
41static struct cpufreq_frequency_table exynos4x12_freq_table[] = { 33static struct cpufreq_frequency_table exynos4x12_freq_table[] = {
42 {L0, 1500 * 1000}, 34 {L0, CPUFREQ_ENTRY_INVALID},
43 {L1, 1400 * 1000}, 35 {L1, 1400 * 1000},
44 {L2, 1300 * 1000}, 36 {L2, 1300 * 1000},
45 {L3, 1200 * 1000}, 37 {L3, 1200 * 1000},
@@ -56,247 +48,54 @@ static struct cpufreq_frequency_table exynos4x12_freq_table[] = {
56 {0, CPUFREQ_TABLE_END}, 48 {0, CPUFREQ_TABLE_END},
57}; 49};
58 50
59static struct cpufreq_clkdiv exynos4x12_clkdiv_table[CPUFREQ_LEVEL_END]; 51static struct apll_freq *apll_freq_4x12;
60 52
61static unsigned int clkdiv_cpu0_4212[CPUFREQ_LEVEL_END][8] = { 53static struct apll_freq apll_freq_4212[] = {
62 /* 54 /*
63 * Clock divider value for following 55 * values:
64 * { DIVCORE, DIVCOREM0, DIVCOREM1, DIVPERIPH, 56 * freq
65 * DIVATB, DIVPCLK_DBG, DIVAPLL, DIVCORE2 } 57 * clock divider for CORE, COREM0, COREM1, PERIPH, ATB, PCLK_DBG, APLL, CORE2
58 * clock divider for COPY, HPM, RESERVED
59 * PLL M, P, S
66 */ 60 */
67 /* ARM L0: 1500 MHz */ 61 APLL_FREQ(1500, 0, 3, 7, 0, 6, 1, 2, 0, 6, 2, 0, 250, 4, 0),
68 { 0, 3, 7, 0, 6, 1, 2, 0 }, 62 APLL_FREQ(1400, 0, 3, 7, 0, 6, 1, 2, 0, 6, 2, 0, 175, 3, 0),
69 63 APLL_FREQ(1300, 0, 3, 7, 0, 5, 1, 2, 0, 5, 2, 0, 325, 6, 0),
70 /* ARM L1: 1400 MHz */ 64 APLL_FREQ(1200, 0, 3, 7, 0, 5, 1, 2, 0, 5, 2, 0, 200, 4, 0),
71 { 0, 3, 7, 0, 6, 1, 2, 0 }, 65 APLL_FREQ(1100, 0, 3, 6, 0, 4, 1, 2, 0, 4, 2, 0, 275, 6, 0),
72 66 APLL_FREQ(1000, 0, 2, 5, 0, 4, 1, 1, 0, 4, 2, 0, 125, 3, 0),
73 /* ARM L2: 1300 MHz */ 67 APLL_FREQ(900, 0, 2, 5, 0, 3, 1, 1, 0, 3, 2, 0, 150, 4, 0),
74 { 0, 3, 7, 0, 5, 1, 2, 0 }, 68 APLL_FREQ(800, 0, 2, 5, 0, 3, 1, 1, 0, 3, 2, 0, 100, 3, 0),
75 69 APLL_FREQ(700, 0, 2, 4, 0, 3, 1, 1, 0, 3, 2, 0, 175, 3, 1),
76 /* ARM L3: 1200 MHz */ 70 APLL_FREQ(600, 0, 2, 4, 0, 3, 1, 1, 0, 3, 2, 0, 200, 4, 1),
77 { 0, 3, 7, 0, 5, 1, 2, 0 }, 71 APLL_FREQ(500, 0, 2, 4, 0, 3, 1, 1, 0, 3, 2, 0, 125, 3, 1),
78 72 APLL_FREQ(400, 0, 2, 4, 0, 3, 1, 1, 0, 3, 2, 0, 100, 3, 1),
79 /* ARM L4: 1100 MHz */ 73 APLL_FREQ(300, 0, 2, 4, 0, 2, 1, 1, 0, 3, 2, 0, 200, 4, 2),
80 { 0, 3, 6, 0, 4, 1, 2, 0 }, 74 APLL_FREQ(200, 0, 1, 3, 0, 1, 1, 1, 0, 3, 2, 0, 100, 3, 2),
81
82 /* ARM L5: 1000 MHz */
83 { 0, 2, 5, 0, 4, 1, 1, 0 },
84
85 /* ARM L6: 900 MHz */
86 { 0, 2, 5, 0, 3, 1, 1, 0 },
87
88 /* ARM L7: 800 MHz */
89 { 0, 2, 5, 0, 3, 1, 1, 0 },
90
91 /* ARM L8: 700 MHz */
92 { 0, 2, 4, 0, 3, 1, 1, 0 },
93
94 /* ARM L9: 600 MHz */
95 { 0, 2, 4, 0, 3, 1, 1, 0 },
96
97 /* ARM L10: 500 MHz */
98 { 0, 2, 4, 0, 3, 1, 1, 0 },
99
100 /* ARM L11: 400 MHz */
101 { 0, 2, 4, 0, 3, 1, 1, 0 },
102
103 /* ARM L12: 300 MHz */
104 { 0, 2, 4, 0, 2, 1, 1, 0 },
105
106 /* ARM L13: 200 MHz */
107 { 0, 1, 3, 0, 1, 1, 1, 0 },
108}; 75};
109 76
110static unsigned int clkdiv_cpu0_4412[CPUFREQ_LEVEL_END][8] = { 77static struct apll_freq apll_freq_4412[] = {
111 /* 78 /*
112 * Clock divider value for following 79 * values:
113 * { DIVCORE, DIVCOREM0, DIVCOREM1, DIVPERIPH, 80 * freq
114 * DIVATB, DIVPCLK_DBG, DIVAPLL, DIVCORE2 } 81 * clock divider for CORE, COREM0, COREM1, PERIPH, ATB, PCLK_DBG, APLL, CORE2
115 */ 82 * clock divider for COPY, HPM, CORES
116 /* ARM L0: 1500 MHz */ 83 * PLL M, P, S
117 { 0, 3, 7, 0, 6, 1, 2, 0 },
118
119 /* ARM L1: 1400 MHz */
120 { 0, 3, 7, 0, 6, 1, 2, 0 },
121
122 /* ARM L2: 1300 MHz */
123 { 0, 3, 7, 0, 5, 1, 2, 0 },
124
125 /* ARM L3: 1200 MHz */
126 { 0, 3, 7, 0, 5, 1, 2, 0 },
127
128 /* ARM L4: 1100 MHz */
129 { 0, 3, 6, 0, 4, 1, 2, 0 },
130
131 /* ARM L5: 1000 MHz */
132 { 0, 2, 5, 0, 4, 1, 1, 0 },
133
134 /* ARM L6: 900 MHz */
135 { 0, 2, 5, 0, 3, 1, 1, 0 },
136
137 /* ARM L7: 800 MHz */
138 { 0, 2, 5, 0, 3, 1, 1, 0 },
139
140 /* ARM L8: 700 MHz */
141 { 0, 2, 4, 0, 3, 1, 1, 0 },
142
143 /* ARM L9: 600 MHz */
144 { 0, 2, 4, 0, 3, 1, 1, 0 },
145
146 /* ARM L10: 500 MHz */
147 { 0, 2, 4, 0, 3, 1, 1, 0 },
148
149 /* ARM L11: 400 MHz */
150 { 0, 2, 4, 0, 3, 1, 1, 0 },
151
152 /* ARM L12: 300 MHz */
153 { 0, 2, 4, 0, 2, 1, 1, 0 },
154
155 /* ARM L13: 200 MHz */
156 { 0, 1, 3, 0, 1, 1, 1, 0 },
157};
158
159static unsigned int clkdiv_cpu1_4212[CPUFREQ_LEVEL_END][2] = {
160 /* Clock divider value for following
161 * { DIVCOPY, DIVHPM }
162 */
163 /* ARM L0: 1500 MHz */
164 { 6, 0 },
165
166 /* ARM L1: 1400 MHz */
167 { 6, 0 },
168
169 /* ARM L2: 1300 MHz */
170 { 5, 0 },
171
172 /* ARM L3: 1200 MHz */
173 { 5, 0 },
174
175 /* ARM L4: 1100 MHz */
176 { 4, 0 },
177
178 /* ARM L5: 1000 MHz */
179 { 4, 0 },
180
181 /* ARM L6: 900 MHz */
182 { 3, 0 },
183
184 /* ARM L7: 800 MHz */
185 { 3, 0 },
186
187 /* ARM L8: 700 MHz */
188 { 3, 0 },
189
190 /* ARM L9: 600 MHz */
191 { 3, 0 },
192
193 /* ARM L10: 500 MHz */
194 { 3, 0 },
195
196 /* ARM L11: 400 MHz */
197 { 3, 0 },
198
199 /* ARM L12: 300 MHz */
200 { 3, 0 },
201
202 /* ARM L13: 200 MHz */
203 { 3, 0 },
204};
205
206static unsigned int clkdiv_cpu1_4412[CPUFREQ_LEVEL_END][3] = {
207 /* Clock divider value for following
208 * { DIVCOPY, DIVHPM, DIVCORES }
209 */ 84 */
210 /* ARM L0: 1500 MHz */ 85 APLL_FREQ(1500, 0, 3, 7, 0, 6, 1, 2, 0, 6, 0, 7, 250, 4, 0),
211 { 6, 0, 7 }, 86 APLL_FREQ(1400, 0, 3, 7, 0, 6, 1, 2, 0, 6, 0, 6, 175, 3, 0),
212 87 APLL_FREQ(1300, 0, 3, 7, 0, 5, 1, 2, 0, 5, 0, 6, 325, 6, 0),
213 /* ARM L1: 1400 MHz */ 88 APLL_FREQ(1200, 0, 3, 7, 0, 5, 1, 2, 0, 5, 0, 5, 200, 4, 0),
214 { 6, 0, 6 }, 89 APLL_FREQ(1100, 0, 3, 6, 0, 4, 1, 2, 0, 4, 0, 5, 275, 6, 0),
215 90 APLL_FREQ(1000, 0, 2, 5, 0, 4, 1, 1, 0, 4, 0, 4, 125, 3, 0),
216 /* ARM L2: 1300 MHz */ 91 APLL_FREQ(900, 0, 2, 5, 0, 3, 1, 1, 0, 3, 0, 4, 150, 4, 0),
217 { 5, 0, 6 }, 92 APLL_FREQ(800, 0, 2, 5, 0, 3, 1, 1, 0, 3, 0, 3, 100, 3, 0),
218 93 APLL_FREQ(700, 0, 2, 4, 0, 3, 1, 1, 0, 3, 0, 3, 175, 3, 1),
219 /* ARM L3: 1200 MHz */ 94 APLL_FREQ(600, 0, 2, 4, 0, 3, 1, 1, 0, 3, 0, 2, 200, 4, 1),
220 { 5, 0, 5 }, 95 APLL_FREQ(500, 0, 2, 4, 0, 3, 1, 1, 0, 3, 0, 2, 125, 3, 1),
221 96 APLL_FREQ(400, 0, 2, 4, 0, 3, 1, 1, 0, 3, 0, 1, 100, 3, 1),
222 /* ARM L4: 1100 MHz */ 97 APLL_FREQ(300, 0, 2, 4, 0, 2, 1, 1, 0, 3, 0, 1, 200, 4, 2),
223 { 4, 0, 5 }, 98 APLL_FREQ(200, 0, 1, 3, 0, 1, 1, 1, 0, 3, 0, 0, 100, 3, 2),
224
225 /* ARM L5: 1000 MHz */
226 { 4, 0, 4 },
227
228 /* ARM L6: 900 MHz */
229 { 3, 0, 4 },
230
231 /* ARM L7: 800 MHz */
232 { 3, 0, 3 },
233
234 /* ARM L8: 700 MHz */
235 { 3, 0, 3 },
236
237 /* ARM L9: 600 MHz */
238 { 3, 0, 2 },
239
240 /* ARM L10: 500 MHz */
241 { 3, 0, 2 },
242
243 /* ARM L11: 400 MHz */
244 { 3, 0, 1 },
245
246 /* ARM L12: 300 MHz */
247 { 3, 0, 1 },
248
249 /* ARM L13: 200 MHz */
250 { 3, 0, 0 },
251};
252
253static unsigned int exynos4x12_apll_pms_table[CPUFREQ_LEVEL_END] = {
254 /* APLL FOUT L0: 1500 MHz */
255 ((250 << 16) | (4 << 8) | (0x0)),
256
257 /* APLL FOUT L1: 1400 MHz */
258 ((175 << 16) | (3 << 8) | (0x0)),
259
260 /* APLL FOUT L2: 1300 MHz */
261 ((325 << 16) | (6 << 8) | (0x0)),
262
263 /* APLL FOUT L3: 1200 MHz */
264 ((200 << 16) | (4 << 8) | (0x0)),
265
266 /* APLL FOUT L4: 1100 MHz */
267 ((275 << 16) | (6 << 8) | (0x0)),
268
269 /* APLL FOUT L5: 1000 MHz */
270 ((125 << 16) | (3 << 8) | (0x0)),
271
272 /* APLL FOUT L6: 900 MHz */
273 ((150 << 16) | (4 << 8) | (0x0)),
274
275 /* APLL FOUT L7: 800 MHz */
276 ((100 << 16) | (3 << 8) | (0x0)),
277
278 /* APLL FOUT L8: 700 MHz */
279 ((175 << 16) | (3 << 8) | (0x1)),
280
281 /* APLL FOUT L9: 600 MHz */
282 ((200 << 16) | (4 << 8) | (0x1)),
283
284 /* APLL FOUT L10: 500 MHz */
285 ((125 << 16) | (3 << 8) | (0x1)),
286
287 /* APLL FOUT L11 400 MHz */
288 ((100 << 16) | (3 << 8) | (0x1)),
289
290 /* APLL FOUT L12: 300 MHz */
291 ((200 << 16) | (4 << 8) | (0x2)),
292
293 /* APLL FOUT L13: 200 MHz */
294 ((100 << 16) | (3 << 8) | (0x2)),
295};
296
297static const unsigned int asv_voltage_4x12[CPUFREQ_LEVEL_END] = {
298 1350000, 1287500, 1250000, 1187500, 1137500, 1087500, 1037500,
299 1000000, 987500, 975000, 950000, 925000, 900000, 900000
300}; 99};
301 100
302static void exynos4x12_set_clkdiv(unsigned int div_index) 101static void exynos4x12_set_clkdiv(unsigned int div_index)
@@ -306,7 +105,7 @@ static void exynos4x12_set_clkdiv(unsigned int div_index)
306 105
307 /* Change Divider - CPU0 */ 106 /* Change Divider - CPU0 */
308 107
309 tmp = exynos4x12_clkdiv_table[div_index].clkdiv; 108 tmp = apll_freq_4x12[div_index].clk_div_cpu0;
310 109
311 __raw_writel(tmp, EXYNOS4_CLKDIV_CPU); 110 __raw_writel(tmp, EXYNOS4_CLKDIV_CPU);
312 111
@@ -314,7 +113,7 @@ static void exynos4x12_set_clkdiv(unsigned int div_index)
314 cpu_relax(); 113 cpu_relax();
315 114
316 /* Change Divider - CPU1 */ 115 /* Change Divider - CPU1 */
317 tmp = exynos4x12_clkdiv_table[div_index].clkdiv1; 116 tmp = apll_freq_4x12[div_index].clk_div_cpu1;
318 117
319 __raw_writel(tmp, EXYNOS4_CLKDIV_CPU1); 118 __raw_writel(tmp, EXYNOS4_CLKDIV_CPU1);
320 if (soc_is_exynos4212()) 119 if (soc_is_exynos4212())
@@ -341,14 +140,14 @@ static void exynos4x12_set_apll(unsigned int index)
341 } while (tmp != 0x2); 140 } while (tmp != 0x2);
342 141
343 /* 2. Set APLL Lock time */ 142 /* 2. Set APLL Lock time */
344 pdiv = ((exynos4x12_apll_pms_table[index] >> 8) & 0x3f); 143 pdiv = ((apll_freq_4x12[index].mps >> 8) & 0x3f);
345 144
346 __raw_writel((pdiv * 250), EXYNOS4_APLL_LOCK); 145 __raw_writel((pdiv * 250), EXYNOS4_APLL_LOCK);
347 146
348 /* 3. Change PLL PMS values */ 147 /* 3. Change PLL PMS values */
349 tmp = __raw_readl(EXYNOS4_APLL_CON0); 148 tmp = __raw_readl(EXYNOS4_APLL_CON0);
350 tmp &= ~((0x3ff << 16) | (0x3f << 8) | (0x7 << 0)); 149 tmp &= ~((0x3ff << 16) | (0x3f << 8) | (0x7 << 0));
351 tmp |= exynos4x12_apll_pms_table[index]; 150 tmp |= apll_freq_4x12[index].mps;
352 __raw_writel(tmp, EXYNOS4_APLL_CON0); 151 __raw_writel(tmp, EXYNOS4_APLL_CON0);
353 152
354 /* 4. wait_lock_time */ 153 /* 4. wait_lock_time */
@@ -367,10 +166,10 @@ static void exynos4x12_set_apll(unsigned int index)
367 } while (tmp != (0x1 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT)); 166 } while (tmp != (0x1 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT));
368} 167}
369 168
370bool exynos4x12_pms_change(unsigned int old_index, unsigned int new_index) 169static bool exynos4x12_pms_change(unsigned int old_index, unsigned int new_index)
371{ 170{
372 unsigned int old_pm = exynos4x12_apll_pms_table[old_index] >> 8; 171 unsigned int old_pm = apll_freq_4x12[old_index].mps >> 8;
373 unsigned int new_pm = exynos4x12_apll_pms_table[new_index] >> 8; 172 unsigned int new_pm = apll_freq_4x12[new_index].mps >> 8;
374 173
375 return (old_pm == new_pm) ? 0 : 1; 174 return (old_pm == new_pm) ? 0 : 1;
376} 175}
@@ -387,7 +186,7 @@ static void exynos4x12_set_frequency(unsigned int old_index,
387 /* 2. Change just s value in apll m,p,s value */ 186 /* 2. Change just s value in apll m,p,s value */
388 tmp = __raw_readl(EXYNOS4_APLL_CON0); 187 tmp = __raw_readl(EXYNOS4_APLL_CON0);
389 tmp &= ~(0x7 << 0); 188 tmp &= ~(0x7 << 0);
390 tmp |= (exynos4x12_apll_pms_table[new_index] & 0x7); 189 tmp |= apll_freq_4x12[new_index].mps & 0x7;
391 __raw_writel(tmp, EXYNOS4_APLL_CON0); 190 __raw_writel(tmp, EXYNOS4_APLL_CON0);
392 191
393 } else { 192 } else {
@@ -402,7 +201,7 @@ static void exynos4x12_set_frequency(unsigned int old_index,
402 /* 1. Change just s value in apll m,p,s value */ 201 /* 1. Change just s value in apll m,p,s value */
403 tmp = __raw_readl(EXYNOS4_APLL_CON0); 202 tmp = __raw_readl(EXYNOS4_APLL_CON0);
404 tmp &= ~(0x7 << 0); 203 tmp &= ~(0x7 << 0);
405 tmp |= (exynos4x12_apll_pms_table[new_index] & 0x7); 204 tmp |= apll_freq_4x12[new_index].mps & 0x7;
406 __raw_writel(tmp, EXYNOS4_APLL_CON0); 205 __raw_writel(tmp, EXYNOS4_APLL_CON0);
407 /* 2. Change the system clock divider values */ 206 /* 2. Change the system clock divider values */
408 exynos4x12_set_clkdiv(new_index); 207 exynos4x12_set_clkdiv(new_index);
@@ -416,27 +215,10 @@ static void exynos4x12_set_frequency(unsigned int old_index,
416 } 215 }
417} 216}
418 217
419static void __init set_volt_table(void)
420{
421 unsigned int i;
422
423 max_support_idx = L1;
424
425 /* Not supported */
426 exynos4x12_freq_table[L0].frequency = CPUFREQ_ENTRY_INVALID;
427
428 for (i = 0 ; i < CPUFREQ_LEVEL_END ; i++)
429 exynos4x12_volt_table[i] = asv_voltage_4x12[i];
430}
431
432int exynos4x12_cpufreq_init(struct exynos_dvfs_info *info) 218int exynos4x12_cpufreq_init(struct exynos_dvfs_info *info)
433{ 219{
434 int i;
435 unsigned int tmp;
436 unsigned long rate; 220 unsigned long rate;
437 221
438 set_volt_table();
439
440 cpu_clk = clk_get(NULL, "armclk"); 222 cpu_clk = clk_get(NULL, "armclk");
441 if (IS_ERR(cpu_clk)) 223 if (IS_ERR(cpu_clk))
442 return PTR_ERR(cpu_clk); 224 return PTR_ERR(cpu_clk);
@@ -455,66 +237,14 @@ int exynos4x12_cpufreq_init(struct exynos_dvfs_info *info)
455 if (IS_ERR(mout_apll)) 237 if (IS_ERR(mout_apll))
456 goto err_mout_apll; 238 goto err_mout_apll;
457 239
458 for (i = L0; i < CPUFREQ_LEVEL_END; i++) { 240 if (soc_is_exynos4212())
459 241 apll_freq_4x12 = apll_freq_4212;
460 exynos4x12_clkdiv_table[i].index = i; 242 else
461 243 apll_freq_4x12 = apll_freq_4412;
462 tmp = __raw_readl(EXYNOS4_CLKDIV_CPU);
463
464 tmp &= ~(EXYNOS4_CLKDIV_CPU0_CORE_MASK |
465 EXYNOS4_CLKDIV_CPU0_COREM0_MASK |
466 EXYNOS4_CLKDIV_CPU0_COREM1_MASK |
467 EXYNOS4_CLKDIV_CPU0_PERIPH_MASK |
468 EXYNOS4_CLKDIV_CPU0_ATB_MASK |
469 EXYNOS4_CLKDIV_CPU0_PCLKDBG_MASK |
470 EXYNOS4_CLKDIV_CPU0_APLL_MASK);
471
472 if (soc_is_exynos4212()) {
473 tmp |= ((clkdiv_cpu0_4212[i][0] << EXYNOS4_CLKDIV_CPU0_CORE_SHIFT) |
474 (clkdiv_cpu0_4212[i][1] << EXYNOS4_CLKDIV_CPU0_COREM0_SHIFT) |
475 (clkdiv_cpu0_4212[i][2] << EXYNOS4_CLKDIV_CPU0_COREM1_SHIFT) |
476 (clkdiv_cpu0_4212[i][3] << EXYNOS4_CLKDIV_CPU0_PERIPH_SHIFT) |
477 (clkdiv_cpu0_4212[i][4] << EXYNOS4_CLKDIV_CPU0_ATB_SHIFT) |
478 (clkdiv_cpu0_4212[i][5] << EXYNOS4_CLKDIV_CPU0_PCLKDBG_SHIFT) |
479 (clkdiv_cpu0_4212[i][6] << EXYNOS4_CLKDIV_CPU0_APLL_SHIFT));
480 } else {
481 tmp &= ~EXYNOS4_CLKDIV_CPU0_CORE2_MASK;
482
483 tmp |= ((clkdiv_cpu0_4412[i][0] << EXYNOS4_CLKDIV_CPU0_CORE_SHIFT) |
484 (clkdiv_cpu0_4412[i][1] << EXYNOS4_CLKDIV_CPU0_COREM0_SHIFT) |
485 (clkdiv_cpu0_4412[i][2] << EXYNOS4_CLKDIV_CPU0_COREM1_SHIFT) |
486 (clkdiv_cpu0_4412[i][3] << EXYNOS4_CLKDIV_CPU0_PERIPH_SHIFT) |
487 (clkdiv_cpu0_4412[i][4] << EXYNOS4_CLKDIV_CPU0_ATB_SHIFT) |
488 (clkdiv_cpu0_4412[i][5] << EXYNOS4_CLKDIV_CPU0_PCLKDBG_SHIFT) |
489 (clkdiv_cpu0_4412[i][6] << EXYNOS4_CLKDIV_CPU0_APLL_SHIFT) |
490 (clkdiv_cpu0_4412[i][7] << EXYNOS4_CLKDIV_CPU0_CORE2_SHIFT));
491 }
492
493 exynos4x12_clkdiv_table[i].clkdiv = tmp;
494
495 tmp = __raw_readl(EXYNOS4_CLKDIV_CPU1);
496
497 if (soc_is_exynos4212()) {
498 tmp &= ~(EXYNOS4_CLKDIV_CPU1_COPY_MASK |
499 EXYNOS4_CLKDIV_CPU1_HPM_MASK);
500 tmp |= ((clkdiv_cpu1_4212[i][0] << EXYNOS4_CLKDIV_CPU1_COPY_SHIFT) |
501 (clkdiv_cpu1_4212[i][1] << EXYNOS4_CLKDIV_CPU1_HPM_SHIFT));
502 } else {
503 tmp &= ~(EXYNOS4_CLKDIV_CPU1_COPY_MASK |
504 EXYNOS4_CLKDIV_CPU1_HPM_MASK |
505 EXYNOS4_CLKDIV_CPU1_CORES_MASK);
506 tmp |= ((clkdiv_cpu1_4412[i][0] << EXYNOS4_CLKDIV_CPU1_COPY_SHIFT) |
507 (clkdiv_cpu1_4412[i][1] << EXYNOS4_CLKDIV_CPU1_HPM_SHIFT) |
508 (clkdiv_cpu1_4412[i][2] << EXYNOS4_CLKDIV_CPU1_CORES_SHIFT));
509 }
510 exynos4x12_clkdiv_table[i].clkdiv1 = tmp;
511 }
512 244
513 info->mpll_freq_khz = rate; 245 info->mpll_freq_khz = rate;
514 info->pm_lock_idx = L5; 246 /* 800Mhz */
515 info->pll_safe_idx = L7; 247 info->pll_safe_idx = L7;
516 info->max_support_idx = max_support_idx;
517 info->min_support_idx = min_support_idx;
518 info->cpu_clk = cpu_clk; 248 info->cpu_clk = cpu_clk;
519 info->volt_table = exynos4x12_volt_table; 249 info->volt_table = exynos4x12_volt_table;
520 info->freq_table = exynos4x12_freq_table; 250 info->freq_table = exynos4x12_freq_table;
diff --git a/drivers/cpufreq/exynos5250-cpufreq.c b/drivers/cpufreq/exynos5250-cpufreq.c
index e64c253cb169..b9344869f822 100644
--- a/drivers/cpufreq/exynos5250-cpufreq.c
+++ b/drivers/cpufreq/exynos5250-cpufreq.c
@@ -21,23 +21,18 @@
21#include <mach/regs-clock.h> 21#include <mach/regs-clock.h>
22#include <mach/cpufreq.h> 22#include <mach/cpufreq.h>
23 23
24#define CPUFREQ_LEVEL_END (L15 + 1)
25
26static int max_support_idx;
27static int min_support_idx = (CPUFREQ_LEVEL_END - 1);
28static struct clk *cpu_clk; 24static struct clk *cpu_clk;
29static struct clk *moutcore; 25static struct clk *moutcore;
30static struct clk *mout_mpll; 26static struct clk *mout_mpll;
31static struct clk *mout_apll; 27static struct clk *mout_apll;
32 28
33struct cpufreq_clkdiv { 29static unsigned int exynos5250_volt_table[] = {
34 unsigned int index; 30 1300000, 1250000, 1225000, 1200000, 1150000,
35 unsigned int clkdiv; 31 1125000, 1100000, 1075000, 1050000, 1025000,
36 unsigned int clkdiv1; 32 1012500, 1000000, 975000, 950000, 937500,
33 925000
37}; 34};
38 35
39static unsigned int exynos5250_volt_table[CPUFREQ_LEVEL_END];
40
41static struct cpufreq_frequency_table exynos5250_freq_table[] = { 36static struct cpufreq_frequency_table exynos5250_freq_table[] = {
42 {L0, 1700 * 1000}, 37 {L0, 1700 * 1000},
43 {L1, 1600 * 1000}, 38 {L1, 1600 * 1000},
@@ -47,8 +42,8 @@ static struct cpufreq_frequency_table exynos5250_freq_table[] = {
47 {L5, 1200 * 1000}, 42 {L5, 1200 * 1000},
48 {L6, 1100 * 1000}, 43 {L6, 1100 * 1000},
49 {L7, 1000 * 1000}, 44 {L7, 1000 * 1000},
50 {L8, 900 * 1000}, 45 {L8, 900 * 1000},
51 {L9, 800 * 1000}, 46 {L9, 800 * 1000},
52 {L10, 700 * 1000}, 47 {L10, 700 * 1000},
53 {L11, 600 * 1000}, 48 {L11, 600 * 1000},
54 {L12, 500 * 1000}, 49 {L12, 500 * 1000},
@@ -58,78 +53,30 @@ static struct cpufreq_frequency_table exynos5250_freq_table[] = {
58 {0, CPUFREQ_TABLE_END}, 53 {0, CPUFREQ_TABLE_END},
59}; 54};
60 55
61static struct cpufreq_clkdiv exynos5250_clkdiv_table[CPUFREQ_LEVEL_END]; 56static struct apll_freq apll_freq_5250[] = {
62
63static unsigned int clkdiv_cpu0_5250[CPUFREQ_LEVEL_END][8] = {
64 /* 57 /*
65 * Clock divider value for following 58 * values:
66 * { ARM, CPUD, ACP, PERIPH, ATB, PCLK_DBG, APLL, ARM2 } 59 * freq
67 */ 60 * clock divider for ARM, CPUD, ACP, PERIPH, ATB, PCLK_DBG, APLL, ARM2
68 { 0, 3, 7, 7, 7, 3, 5, 0 }, /* 1700 MHz */ 61 * clock divider for COPY, HPM, RESERVED
69 { 0, 3, 7, 7, 7, 1, 4, 0 }, /* 1600 MHz */ 62 * PLL M, P, S
70 { 0, 2, 7, 7, 7, 1, 4, 0 }, /* 1500 MHz */
71 { 0, 2, 7, 7, 6, 1, 4, 0 }, /* 1400 MHz */
72 { 0, 2, 7, 7, 6, 1, 3, 0 }, /* 1300 MHz */
73 { 0, 2, 7, 7, 5, 1, 3, 0 }, /* 1200 MHz */
74 { 0, 3, 7, 7, 5, 1, 3, 0 }, /* 1100 MHz */
75 { 0, 1, 7, 7, 4, 1, 2, 0 }, /* 1000 MHz */
76 { 0, 1, 7, 7, 4, 1, 2, 0 }, /* 900 MHz */
77 { 0, 1, 7, 7, 4, 1, 2, 0 }, /* 800 MHz */
78 { 0, 1, 7, 7, 3, 1, 1, 0 }, /* 700 MHz */
79 { 0, 1, 7, 7, 3, 1, 1, 0 }, /* 600 MHz */
80 { 0, 1, 7, 7, 2, 1, 1, 0 }, /* 500 MHz */
81 { 0, 1, 7, 7, 2, 1, 1, 0 }, /* 400 MHz */
82 { 0, 1, 7, 7, 1, 1, 1, 0 }, /* 300 MHz */
83 { 0, 1, 7, 7, 1, 1, 1, 0 }, /* 200 MHz */
84};
85
86static unsigned int clkdiv_cpu1_5250[CPUFREQ_LEVEL_END][2] = {
87 /* Clock divider value for following
88 * { COPY, HPM }
89 */ 63 */
90 { 0, 2 }, /* 1700 MHz */ 64 APLL_FREQ(1700, 0, 3, 7, 7, 7, 3, 5, 0, 0, 2, 0, 425, 6, 0),
91 { 0, 2 }, /* 1600 MHz */ 65 APLL_FREQ(1600, 0, 3, 7, 7, 7, 1, 4, 0, 0, 2, 0, 200, 3, 0),
92 { 0, 2 }, /* 1500 MHz */ 66 APLL_FREQ(1500, 0, 2, 7, 7, 7, 1, 4, 0, 0, 2, 0, 250, 4, 0),
93 { 0, 2 }, /* 1400 MHz */ 67 APLL_FREQ(1400, 0, 2, 7, 7, 6, 1, 4, 0, 0, 2, 0, 175, 3, 0),
94 { 0, 2 }, /* 1300 MHz */ 68 APLL_FREQ(1300, 0, 2, 7, 7, 6, 1, 3, 0, 0, 2, 0, 325, 6, 0),
95 { 0, 2 }, /* 1200 MHz */ 69 APLL_FREQ(1200, 0, 2, 7, 7, 5, 1, 3, 0, 0, 2, 0, 200, 4, 0),
96 { 0, 2 }, /* 1100 MHz */ 70 APLL_FREQ(1100, 0, 3, 7, 7, 5, 1, 3, 0, 0, 2, 0, 275, 6, 0),
97 { 0, 2 }, /* 1000 MHz */ 71 APLL_FREQ(1000, 0, 1, 7, 7, 4, 1, 2, 0, 0, 2, 0, 125, 3, 0),
98 { 0, 2 }, /* 900 MHz */ 72 APLL_FREQ(900, 0, 1, 7, 7, 4, 1, 2, 0, 0, 2, 0, 150, 4, 0),
99 { 0, 2 }, /* 800 MHz */ 73 APLL_FREQ(800, 0, 1, 7, 7, 4, 1, 2, 0, 0, 2, 0, 100, 3, 0),
100 { 0, 2 }, /* 700 MHz */ 74 APLL_FREQ(700, 0, 1, 7, 7, 3, 1, 1, 0, 0, 2, 0, 175, 3, 1),
101 { 0, 2 }, /* 600 MHz */ 75 APLL_FREQ(600, 0, 1, 7, 7, 3, 1, 1, 0, 0, 2, 0, 200, 4, 1),
102 { 0, 2 }, /* 500 MHz */ 76 APLL_FREQ(500, 0, 1, 7, 7, 2, 1, 1, 0, 0, 2, 0, 125, 3, 1),
103 { 0, 2 }, /* 400 MHz */ 77 APLL_FREQ(400, 0, 1, 7, 7, 2, 1, 1, 0, 0, 2, 0, 100, 3, 1),
104 { 0, 2 }, /* 300 MHz */ 78 APLL_FREQ(300, 0, 1, 7, 7, 1, 1, 1, 0, 0, 2, 0, 200, 4, 2),
105 { 0, 2 }, /* 200 MHz */ 79 APLL_FREQ(200, 0, 1, 7, 7, 1, 1, 1, 0, 0, 2, 0, 100, 3, 2),
106};
107
108static unsigned int exynos5_apll_pms_table[CPUFREQ_LEVEL_END] = {
109 ((425 << 16) | (6 << 8) | 0), /* 1700 MHz */
110 ((200 << 16) | (3 << 8) | 0), /* 1600 MHz */
111 ((250 << 16) | (4 << 8) | 0), /* 1500 MHz */
112 ((175 << 16) | (3 << 8) | 0), /* 1400 MHz */
113 ((325 << 16) | (6 << 8) | 0), /* 1300 MHz */
114 ((200 << 16) | (4 << 8) | 0), /* 1200 MHz */
115 ((275 << 16) | (6 << 8) | 0), /* 1100 MHz */
116 ((125 << 16) | (3 << 8) | 0), /* 1000 MHz */
117 ((150 << 16) | (4 << 8) | 0), /* 900 MHz */
118 ((100 << 16) | (3 << 8) | 0), /* 800 MHz */
119 ((175 << 16) | (3 << 8) | 1), /* 700 MHz */
120 ((200 << 16) | (4 << 8) | 1), /* 600 MHz */
121 ((125 << 16) | (3 << 8) | 1), /* 500 MHz */
122 ((100 << 16) | (3 << 8) | 1), /* 400 MHz */
123 ((200 << 16) | (4 << 8) | 2), /* 300 MHz */
124 ((100 << 16) | (3 << 8) | 2), /* 200 MHz */
125};
126
127/* ASV group voltage table */
128static const unsigned int asv_voltage_5250[CPUFREQ_LEVEL_END] = {
129 1300000, 1250000, 1225000, 1200000, 1150000,
130 1125000, 1100000, 1075000, 1050000, 1025000,
131 1012500, 1000000, 975000, 950000, 937500,
132 925000
133}; 80};
134 81
135static void set_clkdiv(unsigned int div_index) 82static void set_clkdiv(unsigned int div_index)
@@ -138,7 +85,7 @@ static void set_clkdiv(unsigned int div_index)
138 85
139 /* Change Divider - CPU0 */ 86 /* Change Divider - CPU0 */
140 87
141 tmp = exynos5250_clkdiv_table[div_index].clkdiv; 88 tmp = apll_freq_5250[div_index].clk_div_cpu0;
142 89
143 __raw_writel(tmp, EXYNOS5_CLKDIV_CPU0); 90 __raw_writel(tmp, EXYNOS5_CLKDIV_CPU0);
144 91
@@ -146,7 +93,7 @@ static void set_clkdiv(unsigned int div_index)
146 cpu_relax(); 93 cpu_relax();
147 94
148 /* Change Divider - CPU1 */ 95 /* Change Divider - CPU1 */
149 tmp = exynos5250_clkdiv_table[div_index].clkdiv1; 96 tmp = apll_freq_5250[div_index].clk_div_cpu1;
150 97
151 __raw_writel(tmp, EXYNOS5_CLKDIV_CPU1); 98 __raw_writel(tmp, EXYNOS5_CLKDIV_CPU1);
152 99
@@ -169,14 +116,14 @@ static void set_apll(unsigned int new_index,
169 } while (tmp != 0x2); 116 } while (tmp != 0x2);
170 117
171 /* 2. Set APLL Lock time */ 118 /* 2. Set APLL Lock time */
172 pdiv = ((exynos5_apll_pms_table[new_index] >> 8) & 0x3f); 119 pdiv = ((apll_freq_5250[new_index].mps >> 8) & 0x3f);
173 120
174 __raw_writel((pdiv * 250), EXYNOS5_APLL_LOCK); 121 __raw_writel((pdiv * 250), EXYNOS5_APLL_LOCK);
175 122
176 /* 3. Change PLL PMS values */ 123 /* 3. Change PLL PMS values */
177 tmp = __raw_readl(EXYNOS5_APLL_CON0); 124 tmp = __raw_readl(EXYNOS5_APLL_CON0);
178 tmp &= ~((0x3ff << 16) | (0x3f << 8) | (0x7 << 0)); 125 tmp &= ~((0x3ff << 16) | (0x3f << 8) | (0x7 << 0));
179 tmp |= exynos5_apll_pms_table[new_index]; 126 tmp |= apll_freq_5250[new_index].mps;
180 __raw_writel(tmp, EXYNOS5_APLL_CON0); 127 __raw_writel(tmp, EXYNOS5_APLL_CON0);
181 128
182 /* 4. wait_lock_time */ 129 /* 4. wait_lock_time */
@@ -196,10 +143,10 @@ static void set_apll(unsigned int new_index,
196 143
197} 144}
198 145
199bool exynos5250_pms_change(unsigned int old_index, unsigned int new_index) 146static bool exynos5250_pms_change(unsigned int old_index, unsigned int new_index)
200{ 147{
201 unsigned int old_pm = (exynos5_apll_pms_table[old_index] >> 8); 148 unsigned int old_pm = apll_freq_5250[old_index].mps >> 8;
202 unsigned int new_pm = (exynos5_apll_pms_table[new_index] >> 8); 149 unsigned int new_pm = apll_freq_5250[new_index].mps >> 8;
203 150
204 return (old_pm == new_pm) ? 0 : 1; 151 return (old_pm == new_pm) ? 0 : 1;
205} 152}
@@ -216,7 +163,7 @@ static void exynos5250_set_frequency(unsigned int old_index,
216 /* 2. Change just s value in apll m,p,s value */ 163 /* 2. Change just s value in apll m,p,s value */
217 tmp = __raw_readl(EXYNOS5_APLL_CON0); 164 tmp = __raw_readl(EXYNOS5_APLL_CON0);
218 tmp &= ~(0x7 << 0); 165 tmp &= ~(0x7 << 0);
219 tmp |= (exynos5_apll_pms_table[new_index] & 0x7); 166 tmp |= apll_freq_5250[new_index].mps & 0x7;
220 __raw_writel(tmp, EXYNOS5_APLL_CON0); 167 __raw_writel(tmp, EXYNOS5_APLL_CON0);
221 168
222 } else { 169 } else {
@@ -231,7 +178,7 @@ static void exynos5250_set_frequency(unsigned int old_index,
231 /* 1. Change just s value in apll m,p,s value */ 178 /* 1. Change just s value in apll m,p,s value */
232 tmp = __raw_readl(EXYNOS5_APLL_CON0); 179 tmp = __raw_readl(EXYNOS5_APLL_CON0);
233 tmp &= ~(0x7 << 0); 180 tmp &= ~(0x7 << 0);
234 tmp |= (exynos5_apll_pms_table[new_index] & 0x7); 181 tmp |= apll_freq_5250[new_index].mps & 0x7;
235 __raw_writel(tmp, EXYNOS5_APLL_CON0); 182 __raw_writel(tmp, EXYNOS5_APLL_CON0);
236 /* 2. Change the system clock divider values */ 183 /* 2. Change the system clock divider values */
237 set_clkdiv(new_index); 184 set_clkdiv(new_index);
@@ -245,24 +192,10 @@ static void exynos5250_set_frequency(unsigned int old_index,
245 } 192 }
246} 193}
247 194
248static void __init set_volt_table(void)
249{
250 unsigned int i;
251
252 max_support_idx = L0;
253
254 for (i = 0 ; i < CPUFREQ_LEVEL_END ; i++)
255 exynos5250_volt_table[i] = asv_voltage_5250[i];
256}
257
258int exynos5250_cpufreq_init(struct exynos_dvfs_info *info) 195int exynos5250_cpufreq_init(struct exynos_dvfs_info *info)
259{ 196{
260 int i;
261 unsigned int tmp;
262 unsigned long rate; 197 unsigned long rate;
263 198
264 set_volt_table();
265
266 cpu_clk = clk_get(NULL, "armclk"); 199 cpu_clk = clk_get(NULL, "armclk");
267 if (IS_ERR(cpu_clk)) 200 if (IS_ERR(cpu_clk))
268 return PTR_ERR(cpu_clk); 201 return PTR_ERR(cpu_clk);
@@ -281,44 +214,9 @@ int exynos5250_cpufreq_init(struct exynos_dvfs_info *info)
281 if (IS_ERR(mout_apll)) 214 if (IS_ERR(mout_apll))
282 goto err_mout_apll; 215 goto err_mout_apll;
283 216
284 for (i = L0; i < CPUFREQ_LEVEL_END; i++) {
285
286 exynos5250_clkdiv_table[i].index = i;
287
288 tmp = __raw_readl(EXYNOS5_CLKDIV_CPU0);
289
290 tmp &= ~((0x7 << 0) | (0x7 << 4) | (0x7 << 8) |
291 (0x7 << 12) | (0x7 << 16) | (0x7 << 20) |
292 (0x7 << 24) | (0x7 << 28));
293
294 tmp |= ((clkdiv_cpu0_5250[i][0] << 0) |
295 (clkdiv_cpu0_5250[i][1] << 4) |
296 (clkdiv_cpu0_5250[i][2] << 8) |
297 (clkdiv_cpu0_5250[i][3] << 12) |
298 (clkdiv_cpu0_5250[i][4] << 16) |
299 (clkdiv_cpu0_5250[i][5] << 20) |
300 (clkdiv_cpu0_5250[i][6] << 24) |
301 (clkdiv_cpu0_5250[i][7] << 28));
302
303 exynos5250_clkdiv_table[i].clkdiv = tmp;
304
305 tmp = __raw_readl(EXYNOS5_CLKDIV_CPU1);
306
307 tmp &= ~((0x7 << 0) | (0x7 << 4));
308
309 tmp |= ((clkdiv_cpu1_5250[i][0] << 0) |
310 (clkdiv_cpu1_5250[i][1] << 4));
311
312 exynos5250_clkdiv_table[i].clkdiv1 = tmp;
313 }
314
315 info->mpll_freq_khz = rate; 217 info->mpll_freq_khz = rate;
316 /* 1000Mhz */
317 info->pm_lock_idx = L7;
318 /* 800Mhz */ 218 /* 800Mhz */
319 info->pll_safe_idx = L9; 219 info->pll_safe_idx = L9;
320 info->max_support_idx = max_support_idx;
321 info->min_support_idx = min_support_idx;
322 info->cpu_clk = cpu_clk; 220 info->cpu_clk = cpu_clk;
323 info->volt_table = exynos5250_volt_table; 221 info->volt_table = exynos5250_volt_table;
324 info->freq_table = exynos5250_freq_table; 222 info->freq_table = exynos5250_freq_table;
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-11 19:14:00 -0500