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authorLinus Torvalds <torvalds@linux-foundation.org>2012-01-11 21:53:33 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2012-01-11 21:53:33 -0500
commit02d929502ce7b57f4835d8bb7c828d36e6d9e8ce (patch)
tree7bb0ca7a9bfe5c336c3125f823770934a2150ae4 /drivers/cpufreq/exynos4210-cpufreq.c
parentb24ca57e7625bc304e77bc429693ad32a691eb16 (diff)
parent6c523c614c13b84a3dc64f7a56d6855b03e6b292 (diff)
Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/davej/cpufreq
* 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/davej/cpufreq: (23 commits) [CPUFREQ] EXYNOS: Removed useless headers and codes [CPUFREQ] EXYNOS: Make EXYNOS common cpufreq driver [CPUFREQ] powernow-k8: Update copyright, maintainer and documentation information [CPUFREQ] powernow-k8: Fix indexing issue [CPUFREQ] powernow-k8: Avoid Pstate MSR accesses on systems supporting CPB [CPUFREQ] update lpj only if frequency has changed [CPUFREQ] cpufreq:userspace: fix cpu_cur_freq updation [CPUFREQ] Remove wall variable from cpufreq_gov_dbs_init() [CPUFREQ] EXYNOS4210: cpufreq code is changed for stable working [CPUFREQ] EXYNOS4210: Update frequency table for cpu divider [CPUFREQ] EXYNOS4210: Remove code about bus on cpufreq [CPUFREQ] s3c64xx: Use pr_fmt() for consistent log messages cpufreq: OMAP: fixup for omap_device changes, include <linux/module.h> cpufreq: OMAP: fix freq_table leak cpufreq: OMAP: put clk if cpu_init failed cpufreq: OMAP: only supports OPP library cpufreq: OMAP: dont support !freq_table cpufreq: OMAP: deny initialization if no mpudev cpufreq: OMAP: move clk name decision to init cpufreq: OMAP: notify even with bad boot frequency ...
Diffstat (limited to 'drivers/cpufreq/exynos4210-cpufreq.c')
-rw-r--r--drivers/cpufreq/exynos4210-cpufreq.c643
1 files changed, 130 insertions, 513 deletions
diff --git a/drivers/cpufreq/exynos4210-cpufreq.c b/drivers/cpufreq/exynos4210-cpufreq.c
index ab9741fab92e..065da5b702f1 100644
--- a/drivers/cpufreq/exynos4210-cpufreq.c
+++ b/drivers/cpufreq/exynos4210-cpufreq.c
@@ -2,61 +2,52 @@
2 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. 2 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com 3 * http://www.samsung.com
4 * 4 *
5 * EXYNOS4 - CPU frequency scaling support 5 * EXYNOS4210 - CPU frequency scaling support
6 * 6 *
7 * This program is free software; you can redistribute it and/or modify 7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as 8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation. 9 * published by the Free Software Foundation.
10*/ 10*/
11 11
12#include <linux/types.h> 12#include <linux/module.h>
13#include <linux/kernel.h> 13#include <linux/kernel.h>
14#include <linux/err.h> 14#include <linux/err.h>
15#include <linux/clk.h> 15#include <linux/clk.h>
16#include <linux/io.h> 16#include <linux/io.h>
17#include <linux/slab.h> 17#include <linux/slab.h>
18#include <linux/regulator/consumer.h>
19#include <linux/cpufreq.h> 18#include <linux/cpufreq.h>
20#include <linux/notifier.h>
21#include <linux/suspend.h>
22 19
23#include <mach/map.h>
24#include <mach/regs-clock.h> 20#include <mach/regs-clock.h>
25#include <mach/regs-mem.h> 21#include <mach/cpufreq.h>
26 22
27#include <plat/clock.h> 23#define CPUFREQ_LEVEL_END L5
28#include <plat/pm.h> 24
25static int max_support_idx = L0;
26static int min_support_idx = (CPUFREQ_LEVEL_END - 1);
29 27
30static struct clk *cpu_clk; 28static struct clk *cpu_clk;
31static struct clk *moutcore; 29static struct clk *moutcore;
32static struct clk *mout_mpll; 30static struct clk *mout_mpll;
33static struct clk *mout_apll; 31static struct clk *mout_apll;
34 32
35static struct regulator *arm_regulator; 33struct cpufreq_clkdiv {
36static struct regulator *int_regulator; 34 unsigned int index;
37 35 unsigned int clkdiv;
38static struct cpufreq_freqs freqs;
39static unsigned int memtype;
40
41static unsigned int locking_frequency;
42static bool frequency_locked;
43static DEFINE_MUTEX(cpufreq_lock);
44
45enum exynos4_memory_type {
46 DDR2 = 4,
47 LPDDR2,
48 DDR3,
49}; 36};
50 37
51enum cpufreq_level_index { 38static unsigned int exynos4210_volt_table[CPUFREQ_LEVEL_END] = {
52 L0, L1, L2, L3, CPUFREQ_LEVEL_END, 39 1250000, 1150000, 1050000, 975000, 950000,
53}; 40};
54 41
55static struct cpufreq_frequency_table exynos4_freq_table[] = { 42
56 {L0, 1000*1000}, 43static struct cpufreq_clkdiv exynos4210_clkdiv_table[CPUFREQ_LEVEL_END];
57 {L1, 800*1000}, 44
58 {L2, 400*1000}, 45static struct cpufreq_frequency_table exynos4210_freq_table[] = {
59 {L3, 100*1000}, 46 {L0, 1200*1000},
47 {L1, 1000*1000},
48 {L2, 800*1000},
49 {L3, 500*1000},
50 {L4, 200*1000},
60 {0, CPUFREQ_TABLE_END}, 51 {0, CPUFREQ_TABLE_END},
61}; 52};
62 53
@@ -67,17 +58,20 @@ static unsigned int clkdiv_cpu0[CPUFREQ_LEVEL_END][7] = {
67 * DIVATB, DIVPCLK_DBG, DIVAPLL } 58 * DIVATB, DIVPCLK_DBG, DIVAPLL }
68 */ 59 */
69 60
70 /* ARM L0: 1000MHz */ 61 /* ARM L0: 1200MHz */
71 { 0, 3, 7, 3, 3, 0, 1 }, 62 { 0, 3, 7, 3, 4, 1, 7 },
72 63
73 /* ARM L1: 800MHz */ 64 /* ARM L1: 1000MHz */
74 { 0, 3, 7, 3, 3, 0, 1 }, 65 { 0, 3, 7, 3, 4, 1, 7 },
75 66
76 /* ARM L2: 400MHz */ 67 /* ARM L2: 800MHz */
77 { 0, 1, 3, 1, 3, 0, 1 }, 68 { 0, 3, 7, 3, 3, 1, 7 },
78 69
79 /* ARM L3: 100MHz */ 70 /* ARM L3: 500MHz */
80 { 0, 0, 1, 0, 3, 1, 1 }, 71 { 0, 3, 7, 3, 3, 1, 7 },
72
73 /* ARM L4: 200MHz */
74 { 0, 1, 3, 1, 3, 1, 0 },
81}; 75};
82 76
83static unsigned int clkdiv_cpu1[CPUFREQ_LEVEL_END][2] = { 77static unsigned int clkdiv_cpu1[CPUFREQ_LEVEL_END][2] = {
@@ -86,147 +80,46 @@ static unsigned int clkdiv_cpu1[CPUFREQ_LEVEL_END][2] = {
86 * { DIVCOPY, DIVHPM } 80 * { DIVCOPY, DIVHPM }
87 */ 81 */
88 82
89 /* ARM L0: 1000MHz */ 83 /* ARM L0: 1200MHz */
90 { 3, 0 }, 84 { 5, 0 },
91 85
92 /* ARM L1: 800MHz */ 86 /* ARM L1: 1000MHz */
93 { 3, 0 }, 87 { 4, 0 },
94 88
95 /* ARM L2: 400MHz */ 89 /* ARM L2: 800MHz */
96 { 3, 0 }, 90 { 3, 0 },
97 91
98 /* ARM L3: 100MHz */ 92 /* ARM L3: 500MHz */
99 { 3, 0 }, 93 { 3, 0 },
100};
101
102static unsigned int clkdiv_dmc0[CPUFREQ_LEVEL_END][8] = {
103 /*
104 * Clock divider value for following
105 * { DIVACP, DIVACP_PCLK, DIVDPHY, DIVDMC, DIVDMCD
106 * DIVDMCP, DIVCOPY2, DIVCORE_TIMERS }
107 */
108
109 /* DMC L0: 400MHz */
110 { 3, 1, 1, 1, 1, 1, 3, 1 },
111
112 /* DMC L1: 400MHz */
113 { 3, 1, 1, 1, 1, 1, 3, 1 },
114
115 /* DMC L2: 266.7MHz */
116 { 7, 1, 1, 2, 1, 1, 3, 1 },
117
118 /* DMC L3: 200MHz */
119 { 7, 1, 1, 3, 1, 1, 3, 1 },
120};
121
122static unsigned int clkdiv_top[CPUFREQ_LEVEL_END][5] = {
123 /*
124 * Clock divider value for following
125 * { DIVACLK200, DIVACLK100, DIVACLK160, DIVACLK133, DIVONENAND }
126 */
127 94
128 /* ACLK200 L0: 200MHz */ 95 /* ARM L4: 200MHz */
129 { 3, 7, 4, 5, 1 }, 96 { 3, 0 },
130
131 /* ACLK200 L1: 200MHz */
132 { 3, 7, 4, 5, 1 },
133
134 /* ACLK200 L2: 160MHz */
135 { 4, 7, 5, 7, 1 },
136
137 /* ACLK200 L3: 133.3MHz */
138 { 5, 7, 7, 7, 1 },
139};
140
141static unsigned int clkdiv_lr_bus[CPUFREQ_LEVEL_END][2] = {
142 /*
143 * Clock divider value for following
144 * { DIVGDL/R, DIVGPL/R }
145 */
146
147 /* ACLK_GDL/R L0: 200MHz */
148 { 3, 1 },
149
150 /* ACLK_GDL/R L1: 200MHz */
151 { 3, 1 },
152
153 /* ACLK_GDL/R L2: 160MHz */
154 { 4, 1 },
155
156 /* ACLK_GDL/R L3: 133.3MHz */
157 { 5, 1 },
158};
159
160struct cpufreq_voltage_table {
161 unsigned int index; /* any */
162 unsigned int arm_volt; /* uV */
163 unsigned int int_volt;
164}; 97};
165 98
166static struct cpufreq_voltage_table exynos4_volt_table[CPUFREQ_LEVEL_END] = { 99static unsigned int exynos4210_apll_pms_table[CPUFREQ_LEVEL_END] = {
167 { 100 /* APLL FOUT L0: 1200MHz */
168 .index = L0, 101 ((150 << 16) | (3 << 8) | 1),
169 .arm_volt = 1200000,
170 .int_volt = 1100000,
171 }, {
172 .index = L1,
173 .arm_volt = 1100000,
174 .int_volt = 1100000,
175 }, {
176 .index = L2,
177 .arm_volt = 1000000,
178 .int_volt = 1000000,
179 }, {
180 .index = L3,
181 .arm_volt = 900000,
182 .int_volt = 1000000,
183 },
184};
185 102
186static unsigned int exynos4_apll_pms_table[CPUFREQ_LEVEL_END] = { 103 /* APLL FOUT L1: 1000MHz */
187 /* APLL FOUT L0: 1000MHz */
188 ((250 << 16) | (6 << 8) | 1), 104 ((250 << 16) | (6 << 8) | 1),
189 105
190 /* APLL FOUT L1: 800MHz */ 106 /* APLL FOUT L2: 800MHz */
191 ((200 << 16) | (6 << 8) | 1), 107 ((200 << 16) | (6 << 8) | 1),
192 108
193 /* APLL FOUT L2 : 400MHz */ 109 /* APLL FOUT L3: 500MHz */
194 ((200 << 16) | (6 << 8) | 2), 110 ((250 << 16) | (6 << 8) | 2),
195 111
196 /* APLL FOUT L3: 100MHz */ 112 /* APLL FOUT L4: 200MHz */
197 ((200 << 16) | (6 << 8) | 4), 113 ((200 << 16) | (6 << 8) | 3),
198}; 114};
199 115
200static int exynos4_verify_speed(struct cpufreq_policy *policy) 116static void exynos4210_set_clkdiv(unsigned int div_index)
201{
202 return cpufreq_frequency_table_verify(policy, exynos4_freq_table);
203}
204
205static unsigned int exynos4_getspeed(unsigned int cpu)
206{
207 return clk_get_rate(cpu_clk) / 1000;
208}
209
210static void exynos4_set_clkdiv(unsigned int div_index)
211{ 117{
212 unsigned int tmp; 118 unsigned int tmp;
213 119
214 /* Change Divider - CPU0 */ 120 /* Change Divider - CPU0 */
215 121
216 tmp = __raw_readl(S5P_CLKDIV_CPU); 122 tmp = exynos4210_clkdiv_table[div_index].clkdiv;
217
218 tmp &= ~(S5P_CLKDIV_CPU0_CORE_MASK | S5P_CLKDIV_CPU0_COREM0_MASK |
219 S5P_CLKDIV_CPU0_COREM1_MASK | S5P_CLKDIV_CPU0_PERIPH_MASK |
220 S5P_CLKDIV_CPU0_ATB_MASK | S5P_CLKDIV_CPU0_PCLKDBG_MASK |
221 S5P_CLKDIV_CPU0_APLL_MASK);
222
223 tmp |= ((clkdiv_cpu0[div_index][0] << S5P_CLKDIV_CPU0_CORE_SHIFT) |
224 (clkdiv_cpu0[div_index][1] << S5P_CLKDIV_CPU0_COREM0_SHIFT) |
225 (clkdiv_cpu0[div_index][2] << S5P_CLKDIV_CPU0_COREM1_SHIFT) |
226 (clkdiv_cpu0[div_index][3] << S5P_CLKDIV_CPU0_PERIPH_SHIFT) |
227 (clkdiv_cpu0[div_index][4] << S5P_CLKDIV_CPU0_ATB_SHIFT) |
228 (clkdiv_cpu0[div_index][5] << S5P_CLKDIV_CPU0_PCLKDBG_SHIFT) |
229 (clkdiv_cpu0[div_index][6] << S5P_CLKDIV_CPU0_APLL_SHIFT));
230 123
231 __raw_writel(tmp, S5P_CLKDIV_CPU); 124 __raw_writel(tmp, S5P_CLKDIV_CPU);
232 125
@@ -248,83 +141,9 @@ static void exynos4_set_clkdiv(unsigned int div_index)
248 do { 141 do {
249 tmp = __raw_readl(S5P_CLKDIV_STATCPU1); 142 tmp = __raw_readl(S5P_CLKDIV_STATCPU1);
250 } while (tmp & 0x11); 143 } while (tmp & 0x11);
251
252 /* Change Divider - DMC0 */
253
254 tmp = __raw_readl(S5P_CLKDIV_DMC0);
255
256 tmp &= ~(S5P_CLKDIV_DMC0_ACP_MASK | S5P_CLKDIV_DMC0_ACPPCLK_MASK |
257 S5P_CLKDIV_DMC0_DPHY_MASK | S5P_CLKDIV_DMC0_DMC_MASK |
258 S5P_CLKDIV_DMC0_DMCD_MASK | S5P_CLKDIV_DMC0_DMCP_MASK |
259 S5P_CLKDIV_DMC0_COPY2_MASK | S5P_CLKDIV_DMC0_CORETI_MASK);
260
261 tmp |= ((clkdiv_dmc0[div_index][0] << S5P_CLKDIV_DMC0_ACP_SHIFT) |
262 (clkdiv_dmc0[div_index][1] << S5P_CLKDIV_DMC0_ACPPCLK_SHIFT) |
263 (clkdiv_dmc0[div_index][2] << S5P_CLKDIV_DMC0_DPHY_SHIFT) |
264 (clkdiv_dmc0[div_index][3] << S5P_CLKDIV_DMC0_DMC_SHIFT) |
265 (clkdiv_dmc0[div_index][4] << S5P_CLKDIV_DMC0_DMCD_SHIFT) |
266 (clkdiv_dmc0[div_index][5] << S5P_CLKDIV_DMC0_DMCP_SHIFT) |
267 (clkdiv_dmc0[div_index][6] << S5P_CLKDIV_DMC0_COPY2_SHIFT) |
268 (clkdiv_dmc0[div_index][7] << S5P_CLKDIV_DMC0_CORETI_SHIFT));
269
270 __raw_writel(tmp, S5P_CLKDIV_DMC0);
271
272 do {
273 tmp = __raw_readl(S5P_CLKDIV_STAT_DMC0);
274 } while (tmp & 0x11111111);
275
276 /* Change Divider - TOP */
277
278 tmp = __raw_readl(S5P_CLKDIV_TOP);
279
280 tmp &= ~(S5P_CLKDIV_TOP_ACLK200_MASK | S5P_CLKDIV_TOP_ACLK100_MASK |
281 S5P_CLKDIV_TOP_ACLK160_MASK | S5P_CLKDIV_TOP_ACLK133_MASK |
282 S5P_CLKDIV_TOP_ONENAND_MASK);
283
284 tmp |= ((clkdiv_top[div_index][0] << S5P_CLKDIV_TOP_ACLK200_SHIFT) |
285 (clkdiv_top[div_index][1] << S5P_CLKDIV_TOP_ACLK100_SHIFT) |
286 (clkdiv_top[div_index][2] << S5P_CLKDIV_TOP_ACLK160_SHIFT) |
287 (clkdiv_top[div_index][3] << S5P_CLKDIV_TOP_ACLK133_SHIFT) |
288 (clkdiv_top[div_index][4] << S5P_CLKDIV_TOP_ONENAND_SHIFT));
289
290 __raw_writel(tmp, S5P_CLKDIV_TOP);
291
292 do {
293 tmp = __raw_readl(S5P_CLKDIV_STAT_TOP);
294 } while (tmp & 0x11111);
295
296 /* Change Divider - LEFTBUS */
297
298 tmp = __raw_readl(S5P_CLKDIV_LEFTBUS);
299
300 tmp &= ~(S5P_CLKDIV_BUS_GDLR_MASK | S5P_CLKDIV_BUS_GPLR_MASK);
301
302 tmp |= ((clkdiv_lr_bus[div_index][0] << S5P_CLKDIV_BUS_GDLR_SHIFT) |
303 (clkdiv_lr_bus[div_index][1] << S5P_CLKDIV_BUS_GPLR_SHIFT));
304
305 __raw_writel(tmp, S5P_CLKDIV_LEFTBUS);
306
307 do {
308 tmp = __raw_readl(S5P_CLKDIV_STAT_LEFTBUS);
309 } while (tmp & 0x11);
310
311 /* Change Divider - RIGHTBUS */
312
313 tmp = __raw_readl(S5P_CLKDIV_RIGHTBUS);
314
315 tmp &= ~(S5P_CLKDIV_BUS_GDLR_MASK | S5P_CLKDIV_BUS_GPLR_MASK);
316
317 tmp |= ((clkdiv_lr_bus[div_index][0] << S5P_CLKDIV_BUS_GDLR_SHIFT) |
318 (clkdiv_lr_bus[div_index][1] << S5P_CLKDIV_BUS_GPLR_SHIFT));
319
320 __raw_writel(tmp, S5P_CLKDIV_RIGHTBUS);
321
322 do {
323 tmp = __raw_readl(S5P_CLKDIV_STAT_RIGHTBUS);
324 } while (tmp & 0x11);
325} 144}
326 145
327static void exynos4_set_apll(unsigned int index) 146static void exynos4210_set_apll(unsigned int index)
328{ 147{
329 unsigned int tmp; 148 unsigned int tmp;
330 149
@@ -343,7 +162,7 @@ static void exynos4_set_apll(unsigned int index)
343 /* 3. Change PLL PMS values */ 162 /* 3. Change PLL PMS values */
344 tmp = __raw_readl(S5P_APLL_CON0); 163 tmp = __raw_readl(S5P_APLL_CON0);
345 tmp &= ~((0x3ff << 16) | (0x3f << 8) | (0x7 << 0)); 164 tmp &= ~((0x3ff << 16) | (0x3f << 8) | (0x7 << 0));
346 tmp |= exynos4_apll_pms_table[index]; 165 tmp |= exynos4210_apll_pms_table[index];
347 __raw_writel(tmp, S5P_APLL_CON0); 166 __raw_writel(tmp, S5P_APLL_CON0);
348 167
349 /* 4. wait_lock_time */ 168 /* 4. wait_lock_time */
@@ -360,328 +179,126 @@ static void exynos4_set_apll(unsigned int index)
360 } while (tmp != (0x1 << S5P_CLKSRC_CPU_MUXCORE_SHIFT)); 179 } while (tmp != (0x1 << S5P_CLKSRC_CPU_MUXCORE_SHIFT));
361} 180}
362 181
363static void exynos4_set_frequency(unsigned int old_index, unsigned int new_index) 182bool exynos4210_pms_change(unsigned int old_index, unsigned int new_index)
183{
184 unsigned int old_pm = (exynos4210_apll_pms_table[old_index] >> 8);
185 unsigned int new_pm = (exynos4210_apll_pms_table[new_index] >> 8);
186
187 return (old_pm == new_pm) ? 0 : 1;
188}
189
190static void exynos4210_set_frequency(unsigned int old_index,
191 unsigned int new_index)
364{ 192{
365 unsigned int tmp; 193 unsigned int tmp;
366 194
367 if (old_index > new_index) { 195 if (old_index > new_index) {
368 /* The frequency changing to L0 needs to change apll */ 196 if (!exynos4210_pms_change(old_index, new_index)) {
369 if (freqs.new == exynos4_freq_table[L0].frequency) {
370 /* 1. Change the system clock divider values */
371 exynos4_set_clkdiv(new_index);
372
373 /* 2. Change the apll m,p,s value */
374 exynos4_set_apll(new_index);
375 } else {
376 /* 1. Change the system clock divider values */ 197 /* 1. Change the system clock divider values */
377 exynos4_set_clkdiv(new_index); 198 exynos4210_set_clkdiv(new_index);
378 199
379 /* 2. Change just s value in apll m,p,s value */ 200 /* 2. Change just s value in apll m,p,s value */
380 tmp = __raw_readl(S5P_APLL_CON0); 201 tmp = __raw_readl(S5P_APLL_CON0);
381 tmp &= ~(0x7 << 0); 202 tmp &= ~(0x7 << 0);
382 tmp |= (exynos4_apll_pms_table[new_index] & 0x7); 203 tmp |= (exynos4210_apll_pms_table[new_index] & 0x7);
383 __raw_writel(tmp, S5P_APLL_CON0); 204 __raw_writel(tmp, S5P_APLL_CON0);
384 }
385 }
386
387 else if (old_index < new_index) {
388 /* The frequency changing from L0 needs to change apll */
389 if (freqs.old == exynos4_freq_table[L0].frequency) {
390 /* 1. Change the apll m,p,s value */
391 exynos4_set_apll(new_index);
392
393 /* 2. Change the system clock divider values */
394 exynos4_set_clkdiv(new_index);
395 } else { 205 } else {
206 /* Clock Configuration Procedure */
207 /* 1. Change the system clock divider values */
208 exynos4210_set_clkdiv(new_index);
209 /* 2. Change the apll m,p,s value */
210 exynos4210_set_apll(new_index);
211 }
212 } else if (old_index < new_index) {
213 if (!exynos4210_pms_change(old_index, new_index)) {
396 /* 1. Change just s value in apll m,p,s value */ 214 /* 1. Change just s value in apll m,p,s value */
397 tmp = __raw_readl(S5P_APLL_CON0); 215 tmp = __raw_readl(S5P_APLL_CON0);
398 tmp &= ~(0x7 << 0); 216 tmp &= ~(0x7 << 0);
399 tmp |= (exynos4_apll_pms_table[new_index] & 0x7); 217 tmp |= (exynos4210_apll_pms_table[new_index] & 0x7);
400 __raw_writel(tmp, S5P_APLL_CON0); 218 __raw_writel(tmp, S5P_APLL_CON0);
401 219
402 /* 2. Change the system clock divider values */ 220 /* 2. Change the system clock divider values */
403 exynos4_set_clkdiv(new_index); 221 exynos4210_set_clkdiv(new_index);
222 } else {
223 /* Clock Configuration Procedure */
224 /* 1. Change the apll m,p,s value */
225 exynos4210_set_apll(new_index);
226 /* 2. Change the system clock divider values */
227 exynos4210_set_clkdiv(new_index);
404 } 228 }
405 } 229 }
406} 230}
407 231
408static int exynos4_target(struct cpufreq_policy *policy, 232int exynos4210_cpufreq_init(struct exynos_dvfs_info *info)
409 unsigned int target_freq,
410 unsigned int relation)
411{
412 unsigned int index, old_index;
413 unsigned int arm_volt, int_volt;
414 int err = -EINVAL;
415
416 freqs.old = exynos4_getspeed(policy->cpu);
417
418 mutex_lock(&cpufreq_lock);
419
420 if (frequency_locked && target_freq != locking_frequency) {
421 err = -EAGAIN;
422 goto out;
423 }
424
425 if (cpufreq_frequency_table_target(policy, exynos4_freq_table,
426 freqs.old, relation, &old_index))
427 goto out;
428
429 if (cpufreq_frequency_table_target(policy, exynos4_freq_table,
430 target_freq, relation, &index))
431 goto out;
432
433 err = 0;
434
435 freqs.new = exynos4_freq_table[index].frequency;
436 freqs.cpu = policy->cpu;
437
438 if (freqs.new == freqs.old)
439 goto out;
440
441 /* get the voltage value */
442 arm_volt = exynos4_volt_table[index].arm_volt;
443 int_volt = exynos4_volt_table[index].int_volt;
444
445 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
446
447 /* control regulator */
448 if (freqs.new > freqs.old) {
449 /* Voltage up */
450 regulator_set_voltage(arm_regulator, arm_volt, arm_volt);
451 regulator_set_voltage(int_regulator, int_volt, int_volt);
452 }
453
454 /* Clock Configuration Procedure */
455 exynos4_set_frequency(old_index, index);
456
457 /* control regulator */
458 if (freqs.new < freqs.old) {
459 /* Voltage down */
460 regulator_set_voltage(arm_regulator, arm_volt, arm_volt);
461 regulator_set_voltage(int_regulator, int_volt, int_volt);
462 }
463
464 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
465
466out:
467 mutex_unlock(&cpufreq_lock);
468 return err;
469}
470
471#ifdef CONFIG_PM
472/*
473 * These suspend/resume are used as syscore_ops, it is already too
474 * late to set regulator voltages at this stage.
475 */
476static int exynos4_cpufreq_suspend(struct cpufreq_policy *policy)
477{
478 return 0;
479}
480
481static int exynos4_cpufreq_resume(struct cpufreq_policy *policy)
482{ 233{
483 return 0; 234 int i;
484} 235 unsigned int tmp;
485#endif 236 unsigned long rate;
486
487/**
488 * exynos4_cpufreq_pm_notifier - block CPUFREQ's activities in suspend-resume
489 * context
490 * @notifier
491 * @pm_event
492 * @v
493 *
494 * While frequency_locked == true, target() ignores every frequency but
495 * locking_frequency. The locking_frequency value is the initial frequency,
496 * which is set by the bootloader. In order to eliminate possible
497 * inconsistency in clock values, we save and restore frequencies during
498 * suspend and resume and block CPUFREQ activities. Note that the standard
499 * suspend/resume cannot be used as they are too deep (syscore_ops) for
500 * regulator actions.
501 */
502static int exynos4_cpufreq_pm_notifier(struct notifier_block *notifier,
503 unsigned long pm_event, void *v)
504{
505 struct cpufreq_policy *policy = cpufreq_cpu_get(0); /* boot CPU */
506 static unsigned int saved_frequency;
507 unsigned int temp;
508
509 mutex_lock(&cpufreq_lock);
510 switch (pm_event) {
511 case PM_SUSPEND_PREPARE:
512 if (frequency_locked)
513 goto out;
514 frequency_locked = true;
515
516 if (locking_frequency) {
517 saved_frequency = exynos4_getspeed(0);
518
519 mutex_unlock(&cpufreq_lock);
520 exynos4_target(policy, locking_frequency,
521 CPUFREQ_RELATION_H);
522 mutex_lock(&cpufreq_lock);
523 }
524
525 break;
526 case PM_POST_SUSPEND:
527
528 if (saved_frequency) {
529 /*
530 * While frequency_locked, only locking_frequency
531 * is valid for target(). In order to use
532 * saved_frequency while keeping frequency_locked,
533 * we temporarly overwrite locking_frequency.
534 */
535 temp = locking_frequency;
536 locking_frequency = saved_frequency;
537
538 mutex_unlock(&cpufreq_lock);
539 exynos4_target(policy, locking_frequency,
540 CPUFREQ_RELATION_H);
541 mutex_lock(&cpufreq_lock);
542
543 locking_frequency = temp;
544 }
545
546 frequency_locked = false;
547 break;
548 }
549out:
550 mutex_unlock(&cpufreq_lock);
551
552 return NOTIFY_OK;
553}
554
555static struct notifier_block exynos4_cpufreq_nb = {
556 .notifier_call = exynos4_cpufreq_pm_notifier,
557};
558
559static int exynos4_cpufreq_cpu_init(struct cpufreq_policy *policy)
560{
561 int ret;
562
563 policy->cur = policy->min = policy->max = exynos4_getspeed(policy->cpu);
564
565 cpufreq_frequency_table_get_attr(exynos4_freq_table, policy->cpu);
566
567 /* set the transition latency value */
568 policy->cpuinfo.transition_latency = 100000;
569
570 /*
571 * EXYNOS4 multi-core processors has 2 cores
572 * that the frequency cannot be set independently.
573 * Each cpu is bound to the same speed.
574 * So the affected cpu is all of the cpus.
575 */
576 cpumask_setall(policy->cpus);
577
578 ret = cpufreq_frequency_table_cpuinfo(policy, exynos4_freq_table);
579 if (ret)
580 return ret;
581
582 cpufreq_frequency_table_get_attr(exynos4_freq_table, policy->cpu);
583
584 return 0;
585}
586
587static int exynos4_cpufreq_cpu_exit(struct cpufreq_policy *policy)
588{
589 cpufreq_frequency_table_put_attr(policy->cpu);
590 return 0;
591}
592
593static struct freq_attr *exynos4_cpufreq_attr[] = {
594 &cpufreq_freq_attr_scaling_available_freqs,
595 NULL,
596};
597
598static struct cpufreq_driver exynos4_driver = {
599 .flags = CPUFREQ_STICKY,
600 .verify = exynos4_verify_speed,
601 .target = exynos4_target,
602 .get = exynos4_getspeed,
603 .init = exynos4_cpufreq_cpu_init,
604 .exit = exynos4_cpufreq_cpu_exit,
605 .name = "exynos4_cpufreq",
606 .attr = exynos4_cpufreq_attr,
607#ifdef CONFIG_PM
608 .suspend = exynos4_cpufreq_suspend,
609 .resume = exynos4_cpufreq_resume,
610#endif
611};
612 237
613static int __init exynos4_cpufreq_init(void)
614{
615 cpu_clk = clk_get(NULL, "armclk"); 238 cpu_clk = clk_get(NULL, "armclk");
616 if (IS_ERR(cpu_clk)) 239 if (IS_ERR(cpu_clk))
617 return PTR_ERR(cpu_clk); 240 return PTR_ERR(cpu_clk);
618 241
619 locking_frequency = exynos4_getspeed(0);
620
621 moutcore = clk_get(NULL, "moutcore"); 242 moutcore = clk_get(NULL, "moutcore");
622 if (IS_ERR(moutcore)) 243 if (IS_ERR(moutcore))
623 goto out; 244 goto err_moutcore;
624 245
625 mout_mpll = clk_get(NULL, "mout_mpll"); 246 mout_mpll = clk_get(NULL, "mout_mpll");
626 if (IS_ERR(mout_mpll)) 247 if (IS_ERR(mout_mpll))
627 goto out; 248 goto err_mout_mpll;
249
250 rate = clk_get_rate(mout_mpll) / 1000;
628 251
629 mout_apll = clk_get(NULL, "mout_apll"); 252 mout_apll = clk_get(NULL, "mout_apll");
630 if (IS_ERR(mout_apll)) 253 if (IS_ERR(mout_apll))
631 goto out; 254 goto err_mout_apll;
632 255
633 arm_regulator = regulator_get(NULL, "vdd_arm"); 256 tmp = __raw_readl(S5P_CLKDIV_CPU);
634 if (IS_ERR(arm_regulator)) {
635 printk(KERN_ERR "failed to get resource %s\n", "vdd_arm");
636 goto out;
637 }
638 257
639 int_regulator = regulator_get(NULL, "vdd_int"); 258 for (i = L0; i < CPUFREQ_LEVEL_END; i++) {
640 if (IS_ERR(int_regulator)) { 259 tmp &= ~(S5P_CLKDIV_CPU0_CORE_MASK |
641 printk(KERN_ERR "failed to get resource %s\n", "vdd_int"); 260 S5P_CLKDIV_CPU0_COREM0_MASK |
642 goto out; 261 S5P_CLKDIV_CPU0_COREM1_MASK |
262 S5P_CLKDIV_CPU0_PERIPH_MASK |
263 S5P_CLKDIV_CPU0_ATB_MASK |
264 S5P_CLKDIV_CPU0_PCLKDBG_MASK |
265 S5P_CLKDIV_CPU0_APLL_MASK);
266
267 tmp |= ((clkdiv_cpu0[i][0] << S5P_CLKDIV_CPU0_CORE_SHIFT) |
268 (clkdiv_cpu0[i][1] << S5P_CLKDIV_CPU0_COREM0_SHIFT) |
269 (clkdiv_cpu0[i][2] << S5P_CLKDIV_CPU0_COREM1_SHIFT) |
270 (clkdiv_cpu0[i][3] << S5P_CLKDIV_CPU0_PERIPH_SHIFT) |
271 (clkdiv_cpu0[i][4] << S5P_CLKDIV_CPU0_ATB_SHIFT) |
272 (clkdiv_cpu0[i][5] << S5P_CLKDIV_CPU0_PCLKDBG_SHIFT) |
273 (clkdiv_cpu0[i][6] << S5P_CLKDIV_CPU0_APLL_SHIFT));
274
275 exynos4210_clkdiv_table[i].clkdiv = tmp;
643 } 276 }
644 277
645 /* 278 info->mpll_freq_khz = rate;
646 * Check DRAM type. 279 info->pm_lock_idx = L2;
647 * Because DVFS level is different according to DRAM type. 280 info->pll_safe_idx = L2;
648 */ 281 info->max_support_idx = max_support_idx;
649 memtype = __raw_readl(S5P_VA_DMC0 + S5P_DMC0_MEMCON_OFFSET); 282 info->min_support_idx = min_support_idx;
650 memtype = (memtype >> S5P_DMC0_MEMTYPE_SHIFT); 283 info->cpu_clk = cpu_clk;
651 memtype &= S5P_DMC0_MEMTYPE_MASK; 284 info->volt_table = exynos4210_volt_table;
652 285 info->freq_table = exynos4210_freq_table;
653 if ((memtype < DDR2) && (memtype > DDR3)) { 286 info->set_freq = exynos4210_set_frequency;
654 printk(KERN_ERR "%s: wrong memtype= 0x%x\n", __func__, memtype); 287 info->need_apll_change = exynos4210_pms_change;
655 goto out;
656 } else {
657 printk(KERN_DEBUG "%s: memtype= 0x%x\n", __func__, memtype);
658 }
659
660 register_pm_notifier(&exynos4_cpufreq_nb);
661
662 return cpufreq_register_driver(&exynos4_driver);
663
664out:
665 if (!IS_ERR(cpu_clk))
666 clk_put(cpu_clk);
667 288
668 if (!IS_ERR(moutcore)) 289 return 0;
669 clk_put(moutcore);
670 290
291err_mout_apll:
671 if (!IS_ERR(mout_mpll)) 292 if (!IS_ERR(mout_mpll))
672 clk_put(mout_mpll); 293 clk_put(mout_mpll);
294err_mout_mpll:
295 if (!IS_ERR(moutcore))
296 clk_put(moutcore);
297err_moutcore:
298 if (!IS_ERR(cpu_clk))
299 clk_put(cpu_clk);
673 300
674 if (!IS_ERR(mout_apll)) 301 pr_debug("%s: failed initialization\n", __func__);
675 clk_put(mout_apll);
676
677 if (!IS_ERR(arm_regulator))
678 regulator_put(arm_regulator);
679
680 if (!IS_ERR(int_regulator))
681 regulator_put(int_regulator);
682
683 printk(KERN_ERR "%s: failed initialization\n", __func__);
684
685 return -EINVAL; 302 return -EINVAL;
686} 303}
687late_initcall(exynos4_cpufreq_init); 304EXPORT_SYMBOL(exynos4210_cpufreq_init);
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-21 02:30:30 -0500