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authorLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>2014-03-04 06:59:54 -0500
committerLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>2014-04-16 06:03:25 -0400
commitf92d62f53973466cccb25900c2597ff6df950d74 (patch)
tree8af4782ca5d61fe30c4c03a2f0392ff1297b2d48 /drivers/clocksource
parent276bee05d8b72e98d530b55161e0a2131da99f58 (diff)
clocksource: sh_mtu2: Turn sh_mtu2_priv fields into local variables
The rate and periodic fields are used in a single function only, as local variables. Remove them from the structure. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Tested-by: Wolfram Sang <wsa@sang-engineering.com>
Diffstat (limited to 'drivers/clocksource')
-rw-r--r--drivers/clocksource/sh_mtu2.c10
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/clocksource/sh_mtu2.c b/drivers/clocksource/sh_mtu2.c
index 77992e081205..66684552fcc9 100644
--- a/drivers/clocksource/sh_mtu2.c
+++ b/drivers/clocksource/sh_mtu2.c
@@ -39,8 +39,6 @@ struct sh_mtu2_priv {
39 struct clk *clk; 39 struct clk *clk;
40 int irq; 40 int irq;
41 struct platform_device *pdev; 41 struct platform_device *pdev;
42 unsigned long rate;
43 unsigned long periodic;
44 struct clock_event_device ced; 42 struct clock_event_device ced;
45}; 43};
46 44
@@ -122,6 +120,8 @@ static void sh_mtu2_start_stop_ch(struct sh_mtu2_priv *p, int start)
122 120
123static int sh_mtu2_enable(struct sh_mtu2_priv *p) 121static int sh_mtu2_enable(struct sh_mtu2_priv *p)
124{ 122{
123 unsigned long periodic;
124 unsigned long rate;
125 int ret; 125 int ret;
126 126
127 pm_runtime_get_sync(&p->pdev->dev); 127 pm_runtime_get_sync(&p->pdev->dev);
@@ -137,13 +137,13 @@ static int sh_mtu2_enable(struct sh_mtu2_priv *p)
137 /* make sure channel is disabled */ 137 /* make sure channel is disabled */
138 sh_mtu2_start_stop_ch(p, 0); 138 sh_mtu2_start_stop_ch(p, 0);
139 139
140 p->rate = clk_get_rate(p->clk) / 64; 140 rate = clk_get_rate(p->clk) / 64;
141 p->periodic = (p->rate + HZ/2) / HZ; 141 periodic = (rate + HZ/2) / HZ;
142 142
143 /* "Periodic Counter Operation" */ 143 /* "Periodic Counter Operation" */
144 sh_mtu2_write(p, TCR, 0x23); /* TGRA clear, divide clock by 64 */ 144 sh_mtu2_write(p, TCR, 0x23); /* TGRA clear, divide clock by 64 */
145 sh_mtu2_write(p, TIOR, 0); 145 sh_mtu2_write(p, TIOR, 0);
146 sh_mtu2_write(p, TGR, p->periodic); 146 sh_mtu2_write(p, TGR, periodic);
147 sh_mtu2_write(p, TCNT, 0); 147 sh_mtu2_write(p, TCNT, 0);
148 sh_mtu2_write(p, TMDR, 0); 148 sh_mtu2_write(p, TMDR, 0);
149 sh_mtu2_write(p, TIER, 0x01); 149 sh_mtu2_write(p, TIER, 0x01);