diff options
author | Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> | 2014-03-04 08:04:24 -0500 |
---|---|---|
committer | Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> | 2014-04-16 06:03:28 -0400 |
commit | da90a1c67751a412499a9f5698c3bf0bf80f65a6 (patch) | |
tree | 47afdc9c8e3a3b7d726784ebe6a7f964e6812d11 /drivers/clocksource | |
parent | aa83804af705731d2802b80fb4b94a79045d31a3 (diff) |
clocksource: sh_mtu2: Add memory base to sh_mtu2_channel structure
The channel memory base is channel-specific, add it to the channel
structure in preparation for support of multiple channels per device.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Wolfram Sang <wsa@sang-engineering.com>
Diffstat (limited to 'drivers/clocksource')
-rw-r--r-- | drivers/clocksource/sh_mtu2.c | 32 |
1 files changed, 18 insertions, 14 deletions
diff --git a/drivers/clocksource/sh_mtu2.c b/drivers/clocksource/sh_mtu2.c index 2fe3ab4c3231..97714ce5e851 100644 --- a/drivers/clocksource/sh_mtu2.c +++ b/drivers/clocksource/sh_mtu2.c | |||
@@ -38,7 +38,10 @@ struct sh_mtu2_device; | |||
38 | 38 | ||
39 | struct sh_mtu2_channel { | 39 | struct sh_mtu2_channel { |
40 | struct sh_mtu2_device *mtu; | 40 | struct sh_mtu2_device *mtu; |
41 | |||
42 | void __iomem *base; | ||
41 | int irq; | 43 | int irq; |
44 | |||
42 | struct clock_event_device ced; | 45 | struct clock_event_device ced; |
43 | }; | 46 | }; |
44 | 47 | ||
@@ -74,39 +77,35 @@ static unsigned long mtu2_reg_offs[] = { | |||
74 | 77 | ||
75 | static inline unsigned long sh_mtu2_read(struct sh_mtu2_channel *ch, int reg_nr) | 78 | static inline unsigned long sh_mtu2_read(struct sh_mtu2_channel *ch, int reg_nr) |
76 | { | 79 | { |
77 | struct sh_timer_config *cfg = ch->mtu->pdev->dev.platform_data; | ||
78 | void __iomem *base = ch->mtu->mapbase; | ||
79 | unsigned long offs; | 80 | unsigned long offs; |
80 | 81 | ||
81 | if (reg_nr == TSTR) | 82 | if (reg_nr == TSTR) |
82 | return ioread8(base + cfg->channel_offset); | 83 | return ioread8(ch->mtu->mapbase); |
83 | 84 | ||
84 | offs = mtu2_reg_offs[reg_nr]; | 85 | offs = mtu2_reg_offs[reg_nr]; |
85 | 86 | ||
86 | if ((reg_nr == TCNT) || (reg_nr == TGR)) | 87 | if ((reg_nr == TCNT) || (reg_nr == TGR)) |
87 | return ioread16(base + offs); | 88 | return ioread16(ch->base + offs); |
88 | else | 89 | else |
89 | return ioread8(base + offs); | 90 | return ioread8(ch->base + offs); |
90 | } | 91 | } |
91 | 92 | ||
92 | static inline void sh_mtu2_write(struct sh_mtu2_channel *ch, int reg_nr, | 93 | static inline void sh_mtu2_write(struct sh_mtu2_channel *ch, int reg_nr, |
93 | unsigned long value) | 94 | unsigned long value) |
94 | { | 95 | { |
95 | struct sh_timer_config *cfg = ch->mtu->pdev->dev.platform_data; | ||
96 | void __iomem *base = ch->mtu->mapbase; | ||
97 | unsigned long offs; | 96 | unsigned long offs; |
98 | 97 | ||
99 | if (reg_nr == TSTR) { | 98 | if (reg_nr == TSTR) { |
100 | iowrite8(value, base + cfg->channel_offset); | 99 | iowrite8(value, ch->mtu->mapbase); |
101 | return; | 100 | return; |
102 | } | 101 | } |
103 | 102 | ||
104 | offs = mtu2_reg_offs[reg_nr]; | 103 | offs = mtu2_reg_offs[reg_nr]; |
105 | 104 | ||
106 | if ((reg_nr == TCNT) || (reg_nr == TGR)) | 105 | if ((reg_nr == TCNT) || (reg_nr == TGR)) |
107 | iowrite16(value, base + offs); | 106 | iowrite16(value, ch->base + offs); |
108 | else | 107 | else |
109 | iowrite8(value, base + offs); | 108 | iowrite8(value, ch->base + offs); |
110 | } | 109 | } |
111 | 110 | ||
112 | static void sh_mtu2_start_stop_ch(struct sh_mtu2_channel *ch, int start) | 111 | static void sh_mtu2_start_stop_ch(struct sh_mtu2_channel *ch, int start) |
@@ -315,13 +314,18 @@ static int sh_mtu2_setup(struct sh_mtu2_device *mtu, | |||
315 | goto err0; | 314 | goto err0; |
316 | } | 315 | } |
317 | 316 | ||
318 | /* map memory, let mapbase point to our channel */ | 317 | /* |
319 | mtu->mapbase = ioremap_nocache(res->start, resource_size(res)); | 318 | * Map memory, let channel.base point to our channel and mapbase to the |
320 | if (mtu->mapbase == NULL) { | 319 | * start/stop shared register. |
320 | */ | ||
321 | mtu->channel.base = ioremap_nocache(res->start, resource_size(res)); | ||
322 | if (mtu->channel.base == NULL) { | ||
321 | dev_err(&mtu->pdev->dev, "failed to remap I/O memory\n"); | 323 | dev_err(&mtu->pdev->dev, "failed to remap I/O memory\n"); |
322 | goto err0; | 324 | goto err0; |
323 | } | 325 | } |
324 | 326 | ||
327 | mtu->mapbase = mtu->channel.base + cfg->channel_offset; | ||
328 | |||
325 | /* get hold of clock */ | 329 | /* get hold of clock */ |
326 | mtu->clk = clk_get(&mtu->pdev->dev, "mtu2_fck"); | 330 | mtu->clk = clk_get(&mtu->pdev->dev, "mtu2_fck"); |
327 | if (IS_ERR(mtu->clk)) { | 331 | if (IS_ERR(mtu->clk)) { |
@@ -344,7 +348,7 @@ static int sh_mtu2_setup(struct sh_mtu2_device *mtu, | |||
344 | err2: | 348 | err2: |
345 | clk_put(mtu->clk); | 349 | clk_put(mtu->clk); |
346 | err1: | 350 | err1: |
347 | iounmap(mtu->mapbase); | 351 | iounmap(mtu->channel.base); |
348 | err0: | 352 | err0: |
349 | return ret; | 353 | return ret; |
350 | } | 354 | } |