Merge tag 'v3.16-rc5' into timers/core

Reason: Bring in upstream modifications, so the pending changes which
depend on them can be queued.

1 files changed, 21 insertions, 8 deletions

diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c
index 8d6420013a04..ab51bf20a3ed 100644
--- a/drivers/clocksource/exynos_mct.c
+++ b/drivers/clocksource/exynos_mct.c
@@ -153,19 +153,16 @@ static void exynos4_mct_write(unsigned int value, unsigned long offset)
 }
 
 /* Clocksource handling */
-static void exynos4_mct_frc_start(u32 hi, u32 lo)
+static void exynos4_mct_frc_start(void)
 {
         u32 reg;
 
-        exynos4_mct_write(lo, EXYNOS4_MCT_G_CNT_L);
-        exynos4_mct_write(hi, EXYNOS4_MCT_G_CNT_U);
-
         reg = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
         reg |= MCT_G_TCON_START;
         exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON);
 }
 
-static cycle_t exynos4_frc_read(struct clocksource *cs)
+static cycle_t notrace _exynos4_frc_read(void)
 {
         unsigned int lo, hi;
         u32 hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U);
@@ -179,9 +176,14 @@ static cycle_t exynos4_frc_read(struct clocksource *cs)
         return ((cycle_t)hi << 32) | lo;
 }
 
+static cycle_t exynos4_frc_read(struct clocksource *cs)
+{
+        return _exynos4_frc_read();
+}
+
 static void exynos4_frc_resume(struct clocksource *cs)
 {
-        exynos4_mct_frc_start(0, 0);
+        exynos4_mct_frc_start();
 }
 
 struct clocksource mct_frc = {
@@ -195,12 +197,23 @@ struct clocksource mct_frc = {
 
 static u64 notrace exynos4_read_sched_clock(void)
 {
-        return exynos4_frc_read(&mct_frc);
+        return _exynos4_frc_read();
+}
+
+static struct delay_timer exynos4_delay_timer;
+
+static cycles_t exynos4_read_current_timer(void)
+{
+        return _exynos4_frc_read();
 }
 
 static void __init exynos4_clocksource_init(void)
 {
-        exynos4_mct_frc_start(0, 0);
+        exynos4_mct_frc_start();
+
+        exynos4_delay_timer.read_current_timer = &exynos4_read_current_timer;
+        exynos4_delay_timer.freq = clk_rate;
+        register_current_timer_delay(&exynos4_delay_timer);
 
         if (clocksource_register_hz(&mct_frc, clk_rate))
                 panic("%s: can't register clocksource\n", mct_frc.name);