Merge branch 'timers-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull timer core updates from Thomas Gleixner:
 "The time(r) departement provides:

   - more infrastructure work on the year 2038 issue

   - a few fixes in the Armada SoC timers

   - the usual pile of fixlets and improvements"

* 'timers-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  clocksource: armada-370-xp: Use the reference clock on A375 SoC
  watchdog: orion: Use the reference clock on Armada 375 SoC
  clocksource: armada-370-xp: Add missing clock enable
  time: Fix sign bug in NTP mult overflow warning
  time: Remove timekeeping_inject_sleeptime()
  rtc: Update suspend/resume timing to use 64bit time
  rtc/lib: Provide y2038 safe rtc_tm_to_time()/rtc_time_to_tm() replacement
  time: Fixup comments to reflect usage of timespec64
  time: Expose get_monotonic_coarse64() for in-kernel uses
  time: Expose getrawmonotonic64 for in-kernel uses
  time: Provide y2038 safe mktime() replacement
  time: Provide y2038 safe timekeeping_inject_sleeptime() replacement
  time: Provide y2038 safe do_settimeofday() replacement
  time: Complete NTP adjustment threshold judging conditions
  time: Avoid possible NTP adjustment mult overflow.
  time: Rename udelay_test.c to test_udelay.c
  clocksource: sirf: Remove hard-coded clock rate

2 files changed, 39 insertions, 14 deletions

diff --git a/drivers/clocksource/time-armada-370-xp.c b/drivers/clocksource/time-armada-370-xp.c
index ff37d3abb806..0c8c5e337540 100644
--- a/drivers/clocksource/time-armada-370-xp.c
+++ b/drivers/clocksource/time-armada-370-xp.c
@@ -318,6 +318,7 @@ static void __init armada_xp_timer_init(struct device_node *np)
 
         /* The 25Mhz fixed clock is mandatory, and must always be available */
         BUG_ON(IS_ERR(clk));
+        clk_prepare_enable(clk);
         timer_clk = clk_get_rate(clk);
 
         armada_370_xp_timer_common_init(np);
@@ -325,11 +326,40 @@ static void __init armada_xp_timer_init(struct device_node *np)
 CLOCKSOURCE_OF_DECLARE(armada_xp, "marvell,armada-xp-timer",
                        armada_xp_timer_init);
 
+static void __init armada_375_timer_init(struct device_node *np)
+{
+        struct clk *clk;
+
+        clk = of_clk_get_by_name(np, "fixed");
+        if (!IS_ERR(clk)) {
+                clk_prepare_enable(clk);
+                timer_clk = clk_get_rate(clk);
+        } else {
+
+                /*
+                 * This fallback is required in order to retain proper
+                 * devicetree backwards compatibility.
+                 */
+                clk = of_clk_get(np, 0);
+
+                /* Must have at least a clock */
+                BUG_ON(IS_ERR(clk));
+                clk_prepare_enable(clk);
+                timer_clk = clk_get_rate(clk) / TIMER_DIVIDER;
+                timer25Mhz = false;
+        }
+
+        armada_370_xp_timer_common_init(np);
+}
+CLOCKSOURCE_OF_DECLARE(armada_375, "marvell,armada-375-timer",
+                       armada_375_timer_init);
+
 static void __init armada_370_timer_init(struct device_node *np)
 {
         struct clk *clk = of_clk_get(np, 0);
 
         BUG_ON(IS_ERR(clk));
+        clk_prepare_enable(clk);
         timer_clk = clk_get_rate(clk) / TIMER_DIVIDER;
         timer25Mhz = false;
 
diff --git a/drivers/clocksource/timer-marco.c b/drivers/clocksource/timer-marco.c
index caf7a2030461..361a789d4bee 100644
--- a/drivers/clocksource/timer-marco.c
+++ b/drivers/clocksource/timer-marco.c
@@ -20,8 +20,6 @@
 #include <linux/of_address.h>
 #include <linux/sched_clock.h>
 
-#define MARCO_CLOCK_FREQ 1000000
-
 #define SIRFSOC_TIMER_32COUNTER_0_CTRL                  0x0000
 #define SIRFSOC_TIMER_32COUNTER_1_CTRL                  0x0004
 #define SIRFSOC_TIMER_MATCH_0                           0x0018
@@ -40,6 +38,8 @@
 
 #define SIRFSOC_TIMER_REG_CNT 6
 
+static unsigned long marco_timer_rate;
+
 static const u32 sirfsoc_timer_reg_list[SIRFSOC_TIMER_REG_CNT] = {
         SIRFSOC_TIMER_WATCHDOG_EN,
         SIRFSOC_TIMER_32COUNTER_0_CTRL,
@@ -195,7 +195,7 @@ static int sirfsoc_local_timer_setup(struct clock_event_device *ce)
         ce->rating = 200;
         ce->set_mode = sirfsoc_timer_set_mode;
         ce->set_next_event = sirfsoc_timer_set_next_event;
-        clockevents_calc_mult_shift(ce, MARCO_CLOCK_FREQ, 60);
+        clockevents_calc_mult_shift(ce, marco_timer_rate, 60);
         ce->max_delta_ns = clockevent_delta2ns(-2, ce);
         ce->min_delta_ns = clockevent_delta2ns(2, ce);
         ce->cpumask = cpumask_of(cpu);
@@ -257,7 +257,6 @@ static void __init sirfsoc_clockevent_init(void)
 /* initialize the kernel jiffy timer source */
 static void __init sirfsoc_marco_timer_init(struct device_node *np)
 {
-        unsigned long rate;
         u32 timer_div;
         struct clk *clk;
 
@@ -266,16 +265,12 @@ static void __init sirfsoc_marco_timer_init(struct device_node *np)
 
         BUG_ON(clk_prepare_enable(clk));
 
-        rate = clk_get_rate(clk);
-
-        BUG_ON(rate < MARCO_CLOCK_FREQ);
-        BUG_ON(rate % MARCO_CLOCK_FREQ);
+        marco_timer_rate = clk_get_rate(clk);
 
-        /* Initialize the timer dividers */
-        timer_div = rate / MARCO_CLOCK_FREQ - 1;
-        writel_relaxed(timer_div << 16, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
-        writel_relaxed(timer_div << 16, sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL);
-        writel_relaxed(timer_div << 16, sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_1_CTRL);
+        /* timer dividers: 0, not divided */
+        writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
+        writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL);
+        writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_1_CTRL);
 
         /* Initialize timer counters to 0 */
         writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_LO);
@@ -288,7 +283,7 @@ static void __init sirfsoc_marco_timer_init(struct device_node *np)
         /* Clear all interrupts */
         writel_relaxed(0xFFFF, sirfsoc_timer_base + SIRFSOC_TIMER_INTR_STATUS);
 
-        BUG_ON(clocksource_register_hz(&sirfsoc_clocksource, MARCO_CLOCK_FREQ));
+        BUG_ON(clocksource_register_hz(&sirfsoc_clocksource, marco_timer_rate));
 
         sirfsoc_clockevent_init();
 }