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authorLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>2014-01-28 09:52:46 -0500
committerLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>2014-07-02 10:01:48 -0400
commit31e912f598371bcfdffc990289029e1110f8b3f9 (patch)
tree37114fdc2ab61490f6e6404981ad8995479f226f /drivers/clocksource
parent4c834452aad01531db949414f94f817a86348d59 (diff)
clocksource: sh_cmt: Drop support for legacy platform data
Now that all platforms have switched to the new-style platform data, drop support for the legacy version. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Tested-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'drivers/clocksource')
-rw-r--r--drivers/clocksource/sh_cmt.c172
1 files changed, 40 insertions, 132 deletions
diff --git a/drivers/clocksource/sh_cmt.c b/drivers/clocksource/sh_cmt.c
index dfa780396b91..fcd38db9ce5c 100644
--- a/drivers/clocksource/sh_cmt.c
+++ b/drivers/clocksource/sh_cmt.c
@@ -114,9 +114,7 @@ struct sh_cmt_device {
114 struct platform_device *pdev; 114 struct platform_device *pdev;
115 115
116 const struct sh_cmt_info *info; 116 const struct sh_cmt_info *info;
117 bool legacy;
118 117
119 void __iomem *mapbase_ch;
120 void __iomem *mapbase; 118 void __iomem *mapbase;
121 struct clk *clk; 119 struct clk *clk;
122 120
@@ -792,7 +790,7 @@ static int sh_cmt_register_clockevent(struct sh_cmt_channel *ch,
792 int irq; 790 int irq;
793 int ret; 791 int ret;
794 792
795 irq = platform_get_irq(ch->cmt->pdev, ch->cmt->legacy ? 0 : ch->index); 793 irq = platform_get_irq(ch->cmt->pdev, ch->index);
796 if (irq < 0) { 794 if (irq < 0) {
797 dev_err(&ch->cmt->pdev->dev, "ch%u: failed to get irq\n", 795 dev_err(&ch->cmt->pdev->dev, "ch%u: failed to get irq\n",
798 ch->index); 796 ch->index);
@@ -863,33 +861,26 @@ static int sh_cmt_setup_channel(struct sh_cmt_channel *ch, unsigned int index,
863 * Compute the address of the channel control register block. For the 861 * Compute the address of the channel control register block. For the
864 * timers with a per-channel start/stop register, compute its address 862 * timers with a per-channel start/stop register, compute its address
865 * as well. 863 * as well.
866 *
867 * For legacy configuration the address has been mapped explicitly.
868 */ 864 */
869 if (cmt->legacy) { 865 switch (cmt->info->model) {
870 ch->ioctrl = cmt->mapbase_ch; 866 case SH_CMT_16BIT:
871 } else { 867 ch->ioctrl = cmt->mapbase + 2 + ch->hwidx * 6;
872 switch (cmt->info->model) { 868 break;
873 case SH_CMT_16BIT: 869 case SH_CMT_32BIT:
874 ch->ioctrl = cmt->mapbase + 2 + ch->hwidx * 6; 870 case SH_CMT_48BIT:
875 break; 871 ch->ioctrl = cmt->mapbase + 0x10 + ch->hwidx * 0x10;
876 case SH_CMT_32BIT: 872 break;
877 case SH_CMT_48BIT: 873 case SH_CMT_32BIT_FAST:
878 ch->ioctrl = cmt->mapbase + 0x10 + ch->hwidx * 0x10; 874 /*
879 break; 875 * The 32-bit "fast" timer has a single channel at hwidx 5 but
880 case SH_CMT_32BIT_FAST: 876 * is located at offset 0x40 instead of 0x60 for some reason.
881 /* 877 */
882 * The 32-bit "fast" timer has a single channel at hwidx 878 ch->ioctrl = cmt->mapbase + 0x40;
883 * 5 but is located at offset 0x40 instead of 0x60 for 879 break;
884 * some reason. 880 case SH_CMT_48BIT_GEN2:
885 */ 881 ch->iostart = cmt->mapbase + ch->hwidx * 0x100;
886 ch->ioctrl = cmt->mapbase + 0x40; 882 ch->ioctrl = ch->iostart + 0x10;
887 break; 883 break;
888 case SH_CMT_48BIT_GEN2:
889 ch->iostart = cmt->mapbase + ch->hwidx * 0x100;
890 ch->ioctrl = ch->iostart + 0x10;
891 break;
892 }
893 } 884 }
894 885
895 if (cmt->info->width == (sizeof(ch->max_match_value) * 8)) 886 if (cmt->info->width == (sizeof(ch->max_match_value) * 8))
@@ -900,12 +891,7 @@ static int sh_cmt_setup_channel(struct sh_cmt_channel *ch, unsigned int index,
900 ch->match_value = ch->max_match_value; 891 ch->match_value = ch->max_match_value;
901 raw_spin_lock_init(&ch->lock); 892 raw_spin_lock_init(&ch->lock);
902 893
903 if (cmt->legacy) { 894 ch->timer_bit = cmt->info->model == SH_CMT_48BIT_GEN2 ? 0 : ch->hwidx;
904 ch->timer_bit = ch->hwidx;
905 } else {
906 ch->timer_bit = cmt->info->model == SH_CMT_48BIT_GEN2
907 ? 0 : ch->hwidx;
908 }
909 895
910 ret = sh_cmt_register(ch, dev_name(&cmt->pdev->dev), 896 ret = sh_cmt_register(ch, dev_name(&cmt->pdev->dev),
911 clockevent, clocksource); 897 clockevent, clocksource);
@@ -938,60 +924,12 @@ static int sh_cmt_map_memory(struct sh_cmt_device *cmt)
938 return 0; 924 return 0;
939} 925}
940 926
941static int sh_cmt_map_memory_legacy(struct sh_cmt_device *cmt)
942{
943 struct sh_timer_config *cfg = cmt->pdev->dev.platform_data;
944 struct resource *res, *res2;
945
946 /* map memory, let mapbase_ch point to our channel */
947 res = platform_get_resource(cmt->pdev, IORESOURCE_MEM, 0);
948 if (!res) {
949 dev_err(&cmt->pdev->dev, "failed to get I/O memory\n");
950 return -ENXIO;
951 }
952
953 cmt->mapbase_ch = ioremap_nocache(res->start, resource_size(res));
954 if (cmt->mapbase_ch == NULL) {
955 dev_err(&cmt->pdev->dev, "failed to remap I/O memory\n");
956 return -ENXIO;
957 }
958
959 /* optional resource for the shared timer start/stop register */
960 res2 = platform_get_resource(cmt->pdev, IORESOURCE_MEM, 1);
961
962 /* map second resource for CMSTR */
963 cmt->mapbase = ioremap_nocache(res2 ? res2->start :
964 res->start - cfg->channel_offset,
965 res2 ? resource_size(res2) : 2);
966 if (cmt->mapbase == NULL) {
967 dev_err(&cmt->pdev->dev, "failed to remap I/O second memory\n");
968 iounmap(cmt->mapbase_ch);
969 return -ENXIO;
970 }
971
972 /* identify the model based on the resources */
973 if (resource_size(res) == 6)
974 cmt->info = &sh_cmt_info[SH_CMT_16BIT];
975 else if (res2 && (resource_size(res2) == 4))
976 cmt->info = &sh_cmt_info[SH_CMT_48BIT_GEN2];
977 else
978 cmt->info = &sh_cmt_info[SH_CMT_32BIT];
979
980 return 0;
981}
982
983static void sh_cmt_unmap_memory(struct sh_cmt_device *cmt)
984{
985 iounmap(cmt->mapbase);
986 if (cmt->mapbase_ch)
987 iounmap(cmt->mapbase_ch);
988}
989
990static int sh_cmt_setup(struct sh_cmt_device *cmt, struct platform_device *pdev) 927static int sh_cmt_setup(struct sh_cmt_device *cmt, struct platform_device *pdev)
991{ 928{
992 struct sh_timer_config *cfg = pdev->dev.platform_data; 929 struct sh_timer_config *cfg = pdev->dev.platform_data;
993 const struct platform_device_id *id = pdev->id_entry; 930 const struct platform_device_id *id = pdev->id_entry;
994 unsigned int hw_channels; 931 unsigned int mask;
932 unsigned int i;
995 int ret; 933 int ret;
996 934
997 memset(cmt, 0, sizeof(*cmt)); 935 memset(cmt, 0, sizeof(*cmt));
@@ -1003,10 +941,9 @@ static int sh_cmt_setup(struct sh_cmt_device *cmt, struct platform_device *pdev)
1003 } 941 }
1004 942
1005 cmt->info = (const struct sh_cmt_info *)id->driver_data; 943 cmt->info = (const struct sh_cmt_info *)id->driver_data;
1006 cmt->legacy = cmt->info ? false : true;
1007 944
1008 /* Get hold of clock. */ 945 /* Get hold of clock. */
1009 cmt->clk = clk_get(&cmt->pdev->dev, cmt->legacy ? "cmt_fck" : "fck"); 946 cmt->clk = clk_get(&cmt->pdev->dev, "fck");
1010 if (IS_ERR(cmt->clk)) { 947 if (IS_ERR(cmt->clk)) {
1011 dev_err(&cmt->pdev->dev, "cannot get clock\n"); 948 dev_err(&cmt->pdev->dev, "cannot get clock\n");
1012 return PTR_ERR(cmt->clk); 949 return PTR_ERR(cmt->clk);
@@ -1016,27 +953,13 @@ static int sh_cmt_setup(struct sh_cmt_device *cmt, struct platform_device *pdev)
1016 if (ret < 0) 953 if (ret < 0)
1017 goto err_clk_put; 954 goto err_clk_put;
1018 955
1019 /* 956 /* Map the memory resource(s). */
1020 * Map the memory resource(s). We need to support both the legacy 957 ret = sh_cmt_map_memory(cmt);
1021 * platform device configuration (with one device per channel) and the
1022 * new version (with multiple channels per device).
1023 */
1024 if (cmt->legacy)
1025 ret = sh_cmt_map_memory_legacy(cmt);
1026 else
1027 ret = sh_cmt_map_memory(cmt);
1028
1029 if (ret < 0) 958 if (ret < 0)
1030 goto err_clk_unprepare; 959 goto err_clk_unprepare;
1031 960
1032 /* Allocate and setup the channels. */ 961 /* Allocate and setup the channels. */
1033 if (cmt->legacy) { 962 cmt->num_channels = hweight8(cfg->channels_mask);
1034 cmt->num_channels = 1;
1035 hw_channels = 0;
1036 } else {
1037 cmt->num_channels = hweight8(cfg->channels_mask);
1038 hw_channels = cfg->channels_mask;
1039 }
1040 963
1041 cmt->channels = kzalloc(cmt->num_channels * sizeof(*cmt->channels), 964 cmt->channels = kzalloc(cmt->num_channels * sizeof(*cmt->channels),
1042 GFP_KERNEL); 965 GFP_KERNEL);
@@ -1045,35 +968,21 @@ static int sh_cmt_setup(struct sh_cmt_device *cmt, struct platform_device *pdev)
1045 goto err_unmap; 968 goto err_unmap;
1046 } 969 }
1047 970
1048 if (cmt->legacy) { 971 /*
1049 ret = sh_cmt_setup_channel(&cmt->channels[0], 972 * Use the first channel as a clock event device and the second channel
1050 cfg->timer_bit, cfg->timer_bit, 973 * as a clock source. If only one channel is available use it for both.
1051 cfg->clockevent_rating != 0, 974 */
1052 cfg->clocksource_rating != 0, cmt); 975 for (i = 0, mask = cfg->channels_mask; i < cmt->num_channels; ++i) {
976 unsigned int hwidx = ffs(mask) - 1;
977 bool clocksource = i == 1 || cmt->num_channels == 1;
978 bool clockevent = i == 0;
979
980 ret = sh_cmt_setup_channel(&cmt->channels[i], i, hwidx,
981 clockevent, clocksource, cmt);
1053 if (ret < 0) 982 if (ret < 0)
1054 goto err_unmap; 983 goto err_unmap;
1055 } else {
1056 unsigned int mask = hw_channels;
1057 unsigned int i;
1058 984
1059 /* 985 mask &= ~(1 << hwidx);
1060 * Use the first channel as a clock event device and the second
1061 * channel as a clock source. If only one channel is available
1062 * use it for both.
1063 */
1064 for (i = 0; i < cmt->num_channels; ++i) {
1065 unsigned int hwidx = ffs(mask) - 1;
1066 bool clocksource = i == 1 || cmt->num_channels == 1;
1067 bool clockevent = i == 0;
1068
1069 ret = sh_cmt_setup_channel(&cmt->channels[i], i, hwidx,
1070 clockevent, clocksource,
1071 cmt);
1072 if (ret < 0)
1073 goto err_unmap;
1074
1075 mask &= ~(1 << hwidx);
1076 }
1077 } 986 }
1078 987
1079 platform_set_drvdata(pdev, cmt); 988 platform_set_drvdata(pdev, cmt);
@@ -1082,7 +991,7 @@ static int sh_cmt_setup(struct sh_cmt_device *cmt, struct platform_device *pdev)
1082 991
1083err_unmap: 992err_unmap:
1084 kfree(cmt->channels); 993 kfree(cmt->channels);
1085 sh_cmt_unmap_memory(cmt); 994 iounmap(cmt->mapbase);
1086err_clk_unprepare: 995err_clk_unprepare:
1087 clk_unprepare(cmt->clk); 996 clk_unprepare(cmt->clk);
1088err_clk_put: 997err_clk_put:
@@ -1133,7 +1042,6 @@ static int sh_cmt_remove(struct platform_device *pdev)
1133} 1042}
1134 1043
1135static const struct platform_device_id sh_cmt_id_table[] = { 1044static const struct platform_device_id sh_cmt_id_table[] = {
1136 { "sh_cmt", 0 },
1137 { "sh-cmt-16", (kernel_ulong_t)&sh_cmt_info[SH_CMT_16BIT] }, 1045 { "sh-cmt-16", (kernel_ulong_t)&sh_cmt_info[SH_CMT_16BIT] },
1138 { "sh-cmt-32", (kernel_ulong_t)&sh_cmt_info[SH_CMT_32BIT] }, 1046 { "sh-cmt-32", (kernel_ulong_t)&sh_cmt_info[SH_CMT_32BIT] },
1139 { "sh-cmt-32-fast", (kernel_ulong_t)&sh_cmt_info[SH_CMT_32BIT_FAST] }, 1047 { "sh-cmt-32-fast", (kernel_ulong_t)&sh_cmt_info[SH_CMT_32BIT_FAST] },